JPS6161088B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a camera malfunction prevention device that electrically detects a malfunction in an electric shutter camera and prevents malfunction of the internal mechanism of the camera. Generally, in an electric shutter camera, the shutter button is operated to perform photometric calculations, then the shutter is released, the aperture is narrowed down and the mirror is raised, and the electromagnet for holding the shutter is energized to open the shutter. After a certain period of time, the shutter is closed by controlling the shutter holding electromagnet. Therefore, shutter control cannot be performed unless the electromagnet operates normally because the power supply battery is exhausted or because the battery has been forgotten to be inserted. For this reason, in conventional cameras, the power supply voltage is checked, and when the power supply voltage is below a predetermined level, the release is locked and the release operation is disabled. However, in such conventional cameras, if there is an abnormality in the coil section of the electromagnet for holding the shutter, related wiring sections, switching circuits such as transistors, the camera may not operate normally. I couldn't do it. That is,
Even though conventional cameras have an abnormality in the shutter holding circuit as described above, if the power supply voltage is above a certain level, the camera will start and the shutter will operate without being held. Therefore, the closing operation starts at the same time as the opening operation of the shutter, and the operation ends with the shutter mechanism remaining closed. When such a situation occurs, the operating time of the shutter often ends within a very short period of time, so the user often continues shooting without noticing this abnormality. The present invention was developed in view of the above circumstances, and before the shutter is opened based on the release operation, a pulse current is applied to the coil of the electromagnet for closing the shutter for a predetermined period of time to check for disconnection of the coil, so that no current flows through the coil. An object of the present invention is to provide a camera malfunction prevention device that can sometimes stop the shutter sequence and prohibit the opening and closing of the shutter to prevent malfunctions of the camera. An embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows the automatic exposure control circuit of an aperture-priority camera. In the figure, the symbol OP is an operational amplifier, CP is a comparator, CT is a counter, and G
are various gates, FF is a flip-flop, AS is an analog switch, DL is a delay circuit, Tr is a transistor, and SW is a switch. The input/output to each circuit is indicated by an arrow, and the name of each input/output signal is written here. The parts surrounded by dotted lines in the figure are blocks showing the functions of each part, where A is the photometry section, B is the calculation section, C is the display section, D is the analog-to-digital converter, and E is the storage and counting section including the logic circuit. , F is the seconds mode selection section,
G is the display section for self-timer shooting, H is the second/real time expansion section, I is the clock signal generation section, J is the first tension magnet control section, K is the trailing curtain holding magnet control section, and L is the various switch operation circuits. , M is a photometry range out-of-range display section, N is a seconds correction circuit, O is a power supply holding and battery check circuit, and P is a strobe control circuit. Among the various switches, SW ₁ is a release switch that is turned on by the first step of the shutter button's release operation, SW ₂ is a switch that is turned on by the second step of the same release operation, and SW ₃ is a main switch that is turned on. When switched, all circuits are powered and
When switched to the BC position, a check of the power supply voltage is performed. SW ₄ is a count switch, SW ₅ is a winding completion switch, SW ₆ is an information setting switch that is turned off during aperture metering, SW ₇ is a self-timer switch that is turned on when shooting with the self-timer, SW ₁₀ is a switch that is turned on when correcting exposure value, SW ₁₄ is synchro
The contacts SW ₁₅ and SW ₁₆ are correction switches for the second adjustment value, and SW ₁₇ is a remote switch that is turned on when using the remote control device. Among the digital counters used in this circuit, CT1 is a presettable 8-bit counter that controls A/D conversion, storage, and self-timer time and self-display, while CT2 inputs clock pulses and divides them. CT3 is a counter that outputs 2 ⁿ series signals. Note that DE1 is a 4-wire to 16-wire decoder. Figure 2 shows the internal mechanism of a camera equipped with the exposure control circuit shown in Figure 1. Here, each switch and other operating parts shown in Figure 1 will be explained. The description will be given using the same reference numerals. SW ₁ and SW ₂ are shutter release button 1
The release switch turned on by the first and second strokes of 0 and the main switch _SW3 are opened and closed in conjunction with the dial DM, which will be described later. SW ₄ is a count switch, and this count switch SW ₄ is always on, and is turned off by the operation of the front curtain tensioning lever 23 to start counting seconds. SW ₆ is a switch for switching between aperture metering and aperture metering. It is on during aperture metering, and can be turned off and switched to aperture metering mode by operating the lever LEV. In the open photometry mode, variable resistors AVC and _ΔAv are connected to the circuit as shown in FIG. 1, and the open F-number and aperture value of the lens are set using these. SPC is a photoelectric conversion unit, for example, a silicon photodiode and its amplifier circuit are integrated into an IC.
It is placed above the eyepiece of the viewfinder. S _v is a variable resistor for setting film sensitivity, DG1
is the conductor pattern of the manual second mode set part, and these are the conductor patterns of the ASA installed on the top of the camera.
The set dial _Ds and manual set mode switching dial DM are operated independently to set the ASA, manual seconds, etc. 25
is the movable contact piece of switch _SW3 , and ₂₅₁ is its fixed contact. This movable contact piece 25 slides on the fixed contact ₂₅₁ in conjunction with the dial DM, and operates the switch.
SW ₃ is the setting of dial DM to BC, which is shown in Figure 1.
When set to OFF, it is connected to the OFF contact in Figure 1, and when set to AUT, B, 30 to 1000, it is connected to the ON contact. The MET is a meter that displays the shutter time within the viewfinder, and the movement of the pointer causes the shutter time at the time of shooting to be displayed on the shutter scale placed around the viewfinder. LED3 is a light emitting diode for displaying flash photography and also serves as meter illumination.
T _x ′ and T _c ′ are the contact points of the accessory shoe placed on the top of the camera, T _x ′ is the synchronization contact, and T
_c ' is a contact point for the strobe control signal. Mg ₂ is a magnet for electromagnetic release with a permanent magnet. This magnet Mg ₂ always attracts the armature with the magnetic flux of the permanent magnet, and when the coil is excited, the magnetic flux caused by it and the magnetic flux of the permanent magnet cancel each other out. This is to release the armature from adsorption. 11 is a start lever that is linked to the armature of the release magnet. Mg ₃ is a shutter control magnet that holds the rear curtain of the shutter, 12 is an aperture ring for setting the aperture value, and 13 is an aperture preset ring. This determines the rotation of the crank. This bell crank controls the rotation of an aperture drive ring (not shown) and determines the opening degree of the aperture. Reference numeral 14 denotes a pin implanted in the aperture drive ring, and this pin 14 engages with an automatic aperture lever 15. 16 is sector gear 17
This signal lever 16 is engaged with the aperture preset ring 13. The sector gear 17 is equipped with a slider having a variable resistance ΔAV. Reference numeral 18 denotes a transmission lever provided with a variable resistance AVC slider, and this transmission lever 18 is rotated in accordance with an opening correction pin 19 on the lens side.
20 is a mirror, 21 is a front curtain gear, 22 is a rear curtain gear, 23 is a front curtain tension lever, and 24 is a rear curtain signal lever. The other parts are omitted because they are not directly related to the present invention. Next, the operation of the above configuration will be explained. First, when the aperture ring 12 is rotated to match the desired aperture value with the index, the aperture preset ring 13 is rotated by the spring to follow the rotation of the aperture ring 12. This rotation is transmitted to the sector gear 17 via the signal lever 16, and the variable resistance Δ corresponding to the aperture value is
AV resistance value can be determined. Further, the resistance value of the variable resistance AVC is determined by rotating the transmission lever 18 in accordance with the open correction pin 19 of the attached lens. When an index is set on the dial DS according to the film sensitivity value of the film loaded in the camera, a resistance value corresponding to the film sensitivity is set on the variable resistor SV. Characters on dial DM
When AUT is adjusted to the index, contacts _{S 1 ,} S ₂ ,
_S3 is turned off. At the same time, switch SW ₃ contact piece 25
is switched to the conductor portion of contact ₂₅₁ and turned on. Therefore, the V _BAT signal is applied to each section shown in FIG. When the release button 10 is pressed, the switch SW ₁ is closed by the first stroke of the release button 10, and the transistor
Tr ₁ turns on. As a result, a voltage _E1 is generated across the capacitor _C1 , and this voltage _E1 is applied to each circuit shown in FIG. 1, such as each gate, each amplifier, and each flip-flop. As a result, the operational amplifier OP ₂ outputs brightness information according to the output of the light receiving element SPc that receives the light transmitted through the photographing lens. In other words, the voltage corresponds to the BV of the apex display. Amplifier OP ₁ receives constant voltage VC from constant voltage circuit VC′
and a constant voltage KVC higher than VC from amplifier OP ₄ are input, and the current of KVC-VC/R _BV is input to the feedback diode D ₁ of amplifier OP ₁ , and the non-inverting input of amplifier OP ₂ is input. Determine the potential of By determining the value of this resistor R _BV , the output of the amplifier OP ₂ can be set in the form of V _C +(B _VO −K ₁ )·V _step (1). Here, B _VO is B _VO =B _V −A _VO −A _VC , and B _V , A _VO , and A _VC are brightness information, respectively.
_K1 is a constant, and V _step is an output difference with respect to a step of change in subject brightness. amplifier
OP ₃ has V _C + (B _VO −
K ₁ )・V _step signal is input, and the calculation is performed between it and the constant voltage V _C of the non-inverting input, and the output is V _C −(B _VO +K ₁ )・V _C /14 ………(2 ) is obtained. In equation (2), the number of steps is set to "14". Amplifier OP ₄ is an operational amplifier that receives a constant voltage _VC as input and generates a voltage _KVC higher than _VC , and its output is the amplifier OP ₁ and the amplifier for A _VC and ΔA _V calculations. input to device OP ₅ . Here, _ΔAV is an apex value indicating the deviation of the aperture value of the lens from its maximum aperture value. A constant voltage V _C is input to the non-inverting input of amplifier OP ₅ , and A _VC , ΔA applied to its inverting input
Calculation is performed between _{the V} information setting value and the amplifier
As the output of OP ₅ , information of V _C +(ΔA _V −A _VC +K ₂ )·V/14 (3) is obtained. Output equation (2) of the above photometric circuit and output of the information setting circuit
Equation (3) and the film sensitivity information S _V are applied to the inverting input of the amplifier OP ₆ and calculated together with the constant voltage V _C to the non-inverting input, and the amplifier OP ₆ outputs the apex value T _V of the second time information. Output. That is, {(B _VO +K ₁ )V _C /14−(ΔA _V −A _VC +K ₂ )V _C /14+(S _V +K ₃ )V _C /14}×2+V _C =(B _V −A _VO −ΔA _V +S _V +K) V _C /7+V _C = (B _V −A _V +S _V +K) V _C /7+V _C = (T _V +K) V _C /7+V _C …(4) Here, K is K=K ₁ −K ₂ + K ₃ is a constant and A _V = A
_VO +ΔA _V , T _V =B _V −A _V +S _V. Switch SW ₆ is a switch that is turned off during aperture metering, and switch SW ₁₀ is a switch that is used to compensate for backlight, etc. By turning on SW ₁₀ , the output of amplifier OP ₆ is changed to ( _TV +K- α) V _C /7 +V _C Only α can be corrected. In addition, in the aperture metering mode with switch SW ₆ turned off, the output of amplifier OP ₃ is V _C − (B _V − A _V +
K ₁ )V _C /14, so the output of OP ₅ is V _C +K ₂・V _C
/14, and the output of the amplifier OP ₆ at this time is V _C + (B _V − A _V + K ₁ − K ₂ + S _V +
K ₃ ) V _C /7=V _C + (T _V +K) V _C /7, (4)
The same calculation output as the expression can be obtained. As described above, the second analog information _TV in the natural light condition is output from the amplifier _OP6 , is displayed on the display meter MET in the viewfinder via the analog switch AS1, and is input to the next stage analog-to-digital conversion circuit D. Ru. Next, the operation after the analog-to-digital conversion circuit that does not use a self-timer will be explained with reference to the timing chart shown in FIG. When the switch _SW1 is turned on, the 8th bit of the storage counter CT1 is at the "0" level, and the 8MSE signal is at the "0" level. Since the self-timer switch _SW7 is off, SLFS is "0", the output SLFM of the gate _G7 is "0", and the output of the gate _G6 to which these signals are input is also "0". This “0” signal causes two buffer amplifiers OP ₈ ,
Among OP ₉ , amplifier OP ₈ is activated and amplifier OP ₉ is inactivated. In this state, the output of amplifier OP ₉ becomes an infinite impedance, and if the amplifier OP ₈ outputs a signal of (T _V -10) V _C /14 + V _C , the result shown in Fig. 3C is shown. As shown, since the amplifier OP ₁₀ constitutes a Miller integration circuit with the capacitor C ₂ in the feedback path, the output of the amplifier OP ₁₀ increases linearly from the constant voltage V _C ( time a
From b). This signal is input to the comparator CP1, compared with the constant voltage V _C of its non-inverting input, and output. The output voltage of amplifier OP ₁₀ is constant voltage V _C
Since it is higher, the output ADE of comparator CP1 becomes "0". Furthermore, as described above, since the SLFM signal is "0" due to the self-disuse, the gate _G1 passes the 16384 Hz pulse from the counter frequency divider CT2 and sends it to the gate _G3 . At this time, gate G ₂ is
Since the SLFM signal is “0”, it is in a prohibited state,
Therefore, the clock input CP to counter CT1 is
A pulse of 16384Hz is input. At this time, if the shutter information manual setting dial DM is in the "Aut" position, all inputs of gate _G16 are "1", so the output of gate _G16 is "0", which is transmitted through gate _G18 . input to the preset enable PE of counter CT1 and prohibit presetting to counter CT1.
Counter CT1 will only accept clock input. That is, the counter CT1 counts in synchronization with the fall of the clock input, and the time for the 8th bit output 8MSE to become "1" is approximately 8 ms. The capacitor C ₂ of the integrating circuit charged from time a to b in Fig. 3C has a signal of 8 MSE
When becomes “1” (b) Output of gate G ₆ becomes “1”
Therefore, the input of the integrating amplifier OP ₁₀ is the amplifier
The output of OP ₈ is switched to the output of amplifier OP ₉ ,
The voltage KV _C (>V _C ) at the non-inverting input level of OP ₉ starts discharging the capacitor C ₂ (the third
(From point b in Figure C). As a result, the output level of the amplifier _OP10 drops as shown in Figure 3C, and when it becomes lower than the constant voltage V _C (point c), the output signal of the comparator CP1
ADE becomes “1”. This signal is input to gate _G4 . At this time, the input of gate G ₄ has SLFM "0", which becomes "1" as described later, so gate G ₄ generates an ADR signal of "1" at its output.
Since this is SLFR "0", it is input to the reset terminal R of counter CT1 through gate _G5 ,
The count is reset at the moment the signal ADR becomes "1" (Fig. 3E). Therefore, at this time, the 8th bit output 8MSE becomes “0” and the integrating capacitor
_C2 is charged again as shown in FIG. 3C, and this cycle is repeated. In this state, the counter CT1 does not store any information, but continues to repeatedly count the input digital information. During this period, as shown in FIG. 3, the waveform due to charging and discharging of the capacitor _C2 changes in accordance with the change in luminance information. Next, switch SW ₂ is activated by the second stage release operation.
The operation of the circuit when the camera turns on and moves to photographing operation will be explained. Switch SW ₅ is turned on when the film winding operation is completed, and signal ₅ becomes "0". In this state, when release switch SW ₂ is turned on by the second stroke of the shutter button, a signal is generated.
₂ becomes “0”. When _SW2 is off, flip-flop _F7 is reset by the power-up clear signal PUC to gate G72, and the Q output of flip-flop _F7 is "0". Turning SW ₅ on flip-flop F ₇ D
"1" is input to the input, and PUC of the input of gate G70 becomes "0", and ₂ becomes "0", and the clock input CP of flip-flop _F7 becomes a delay circuit.
At DL ₁ , “1” is input after a certain time delay. At this time, since the hour/second selection dial DM is not exposed to the bulb, the Bulb signal among the inputs of gate G71 is "0", and if the power supply voltage _E1 is higher than the set prohibition voltage, the output of comparator CP3 is also "0". Therefore, the output of the gate G72 becomes "0", and therefore the Q output of the D-type flip-flop _F7 becomes "1" in synchronization with the rising edge of the CP input. (Figure 3G,
H, I) SW ₅ when the film winding operation is not completed.
is off and ₅ is “1”, so even if release switch SW ₂ is turned on, the flip-flop will not be activated.
The D input of _F7 is “0” and the flip-flop _F7
Q output does not become "1", and even if film winding is completed with release switch SW ₂ on, when D input of flip-flop _F7 becomes "1", CP input remains "1". Therefore, the Q output of flip-flop _F7 does not become "1". As a result, even if an automatic winding device is used, if the release switches SW ₁ and SW ₂ remain on, the automatic winding device will not perform continuous release operations, and once winding is complete, the next release will not be performed and this state will be held. be done. Therefore, to perform the next photograph, it is only necessary to turn off the switch SW ₂ and then turn it on. It should be noted that the switch SW17 is a remote control release switch and is used to perform a camera release operation at a position far away from the camera. When power switch SW ₃ is in the on position, switch SW
When transistor Tr 17 is turned on, transistor Tr ₁ is turned on via diode D ₄ in the same manner as when release switch SW ₁ is turned on. This turns on the power supply holding circuit, and if winding is completed at that time, the D input of flip-flop _F7 becomes "1" at the same time as the power is turned on, and the output of gate G70 rises after a time delay of the power up clear PUC. This is delayed again by the delay circuit _DL1 and input to the CP terminal of the flip-flop _F7 . As a result, a trigger signal is applied to the CP terminal of the flip-flop _F7 when the initial PUC reset becomes stable, and the Q output of the flip-flop _F7 becomes "1". Even if the switch SW17 is turned off after this state is reached, the Q output of the flip-flop _F7 is "0", so the transistor _Tr3 remains on and the power supply is latched. At this time, if the power supply voltage falls below the set value, the output of comparator CP3 of the prohibition circuit becomes "1", and as will be described later,
Before the signal RELS that starts storing the calculated value TV rises to 1, (gate circuit G73,
G72) Set the Q output of flip-flop _F7 to “0”
Let it be. In this way, when the Q output of flip-flop _F7 becomes "1", the Q output of flip-flop _F7 is input to one side of gate G61, and the other input of gate G61 is connected to the flip-flop.
Since the Q output of _F7 is applied through the delay circuit _DL2 , an instantaneous pulse signal RELR is sent to the output of the gate G61 in synchronization with the rising edge of the flip-flop _F7 as shown in FIG. 3 I, J and K. occurs. This RELR signal is input to counter CT2 via gate G44 and resets frequency division counter CT2. The Q output of the flip-flop _F7 is also input to the reset terminal R of the D-type flip-flop _F5 via an inverter, and the flip-flop _F5 is always reset when the Q output of the flip-flop _F7 is "0". When the Q output of the flip-flop _F7 becomes "1", the gate G6 of the control circuit K of the shutter speed control magnet
The output of Tr 3 becomes "1", which is input to the transistor Tr ₄ via the gate G64 and
Since Tr ₄ is turned on, magnet Mg ₃ is energized. Note that one input M3EN of the gate G64 is always at "0" as described later. When the magnet _Mg3 is energized, the MG35 signal becomes "1", the output of the gate G62 becomes "1", and this inputs "1" to the D terminal of the flip-flop _F5 . The input of gate G60 connected to the CP input of flip-flop _F5 is a delay circuit.
The output of DL ₂ and the 64 Hz output of the counter CT2 are input, so that the output of the gate G60 outputs the 64 Hz output of the counter CT2 after the counter CT2 is completely reset. Therefore, the Q output of flip-flop _F5 becomes "1" at the rising edge of 64 Hz, that is, about 8 ms after flip-flop _F5 is reset. Therefore, the rear curtain holding magnet
Mg ₃ is energized only for 8 ms until the Q output of flip-flop F ₅ becomes "1".
If the power supply voltage drops below the prohibited voltage during this time, the Q output of flip-flop _F7 becomes "0" and all sequence operations end at this point. Furthermore, if the coil of magnet Mg ₃ becomes disconnected for some reason, magnet Mg ₃ is not energized and the MG35 signal remains "0", so the output of gate G62 does not become "1" and the output from flip-flop F The Q output of ₅ never becomes "1". “1” of this flip-flop _F5
The Q output becomes the release signal RELS, and the next sequence operation is started. Gate G73 is
Even in cases where extreme power deterioration may occur, such as in the case of long-term exposure, the system is configured to operate without taking this into account. On the other hand, the SR type flip-flop _F2 is reset by the power-up clear PUC signal when the power is turned on. Also counter CT2 is gate G4
It is reset by PUC input of 4. Since the self-timer is not used, one input SLFM of gate G14 is "0", and gate G14 is set at the rising edge of the 8Hz signal from counter CT2.
The output becomes “1”. i.e. flipflop
The Q output of _F2 becomes "1" approximately 60ms after the power is turned on. This is to ensure that even if switches SW ₁ and SW ₂ are turned on momentarily due to a sudden press of the shutter button, etc., the memory operation will be performed after a minimum time of 60 ms, especially when the subject brightness is low. This is to ensure that the storage operation is performed reliably even in cases where it takes time for the output of the operational amplifier _OP2 to become stable. As described above, when the above-mentioned release signal RELS becomes "1" 60 ms after the power is turned on, the output of the gate G13 becomes "0", which is input to the gate _G4 and puts the gate _G4 in an inhibited state.
At the same time, the output of the gate G13 is inverted by the inverter to become "1" and is applied as the MEOK signal to the D input of the flip-flop _F3 . Gate G ₄ is disabled due to gate G ₄ being disabled.
The output ADR signal of the A/D conversion comparator CP1 does not become "1" even at the end of the AD conversion when the output signal ADE of the A/D conversion comparator CP1 becomes "1", so the counter CT1 is reset by the output of the gate _G5 . is not carried out. Also, in this state, since the signal ADE is "1", the output of the gate _G1 becomes "0", and the counter CT1 stores the A/D conversion information at this time. FIGS. 3D, E and M are timing charts showing this state. On the other hand, since both 8MSE and ADE of the input to the gate G12 are "1", the gate G45 generates a short pulse MG2R, which is sent to the counter CT via the gate G44.
2 (Figure 3 N). The D-type flip-flop _F3 , which receives the signal inverter output MEOK signal as its D input, outputs Q in synchronization with the rise of the output of gate G12 when MEOK becomes "1".
becomes “1”. When this Q output is input, the output of gate G10 is countered by the output of DL ₃ .
CT2 is inhibited for a period of time to reset, then CT2
“0” from G10 until 64Hz signal is output from
is output. The output of gate G10 is a counter
The rise of the 64Hz signal from CT2, that is about 8m
After s, it becomes "1" and this resets the flip-flop _F3 via the gate G11. That is, the Q output of flip-flop _F3 generates "1" for only 8 ms (FIG. 3O). The Q output MS2S of this flip-flop _F3 is applied to the release magnet _Mg2 via an inverter and a buffer. Therefore, the magnetic flux of the magnet Mg ₂ caused by the excitation of the coil and the magnetic flux of the permanent magnet cancel each other out, thereby releasing the armature from adsorption.
Therefore, the start lever 11 is actuated to start the mechanism shown in FIG. 1, which drives the automatic aperture lever 15 to actuate the pin 14 and rotate the aperture drive ring. Therefore, the aperture drive ring narrows down the aperture blades according to the position of the bell crank based on the aperture value set by the aperture ring 12. Further, after the mirror 20 is raised, the front curtain tensioning lever 23 is operated and the count switch SW ₄ is turned off, at the same time the front curtain of the shutter mechanism starts. The Q output MG2S of the flip-flop _F3 is RS
The PUC input of gate G46 is led to the set input S of type flip-flop _F4 to set flip-flop _F4 , which is reset at power-on. The gate G of the strobe control circuit P is controlled by the "1" signal of the Q output M3EM of the flip-flop _F4 .
M3EN "0" is input to 65, and the strobe charging completion signal CCEF is inhibited. Moreover, this "1" signal of M3EN restarts the energization to the shutter time control magnet _Mg3 via the gate G64 (FIG. 3L, P). As will be described later, the output of gate G47 is input to the reset terminal of flip-flop _F4 through gate G46, and one of the inputs of gate G47, that is, exposure time completion signal CNTE, is "1".
When this happens, the flip-flop _F4 is reset and the power to the shutter control magnet _Mg3 is cut off. Therefore, the armature of the magnet Mg ₃ is released from adsorption, rotates the rear curtain gear 22, runs the rear curtain of the shutter mechanism, and closes the shutter. As a result, the signal lever 243 is actuated and the second
The mechanism shown in the figure is driven to return the mirror 20, and the automatic aperture lever 15 is also returned to return the aperture blades to their original open state. When the dial DM is set to valve mode, the output BULB of gate G17 becomes "1", so the CNTE input of gate G47 is prohibited, and the switch operates on the second release stroke.
When SW ₂ is turned off by pressing down and released, the output of gate G71 becomes "1", the power latch is released, and when switch SW ₁ is turned off and the power is turned off, the rear curtain of the shutter runs and the bulb shooting operation starts. Complete. Also, when storing the above information, the counter
Since the 8th bit output 8MSE of CT1 is always "1", the output of amplifier OP10 of the memory integration circuit is connected to the amplifier OP9 side, and capacitor C ₂
is charged in the opposite direction to that described above. However, when the voltage of capacitor C ₂ reaches a constant value due to the action of diode D ₅ , the charging current flows toward diode D ₅ , so that capacitor C ₂ is no longer charged. Here, a case will be described in which the digital information stored in the storage counter CT1 is read out by the real time extension and second correction circuit to determine the shutter second.

【table】

[Table] As shown in Table 1, the digital information of counter CT1 is shutter seconds in multiples from 1/1000 seconds to 4 seconds. As will be described later, Table 1 is designed to avoid long exposures of 4 seconds or more. In addition, B1/2 of the 1st, 2nd, and 3rd bits of the counter,
In B1/4 and B1/8, the information for one stage is divided into eight. Note that when the mode selection dial DG1 is set to a value other than "Aut", the counter CT1 releases the memory of the A/D conversion information when the electromagnetic release magnet _Mg2 is turned on by a signal from the gate G18, and the conductor pattern DG1 It is now possible to directly preset the seconds and time information. In addition, if the flash is not in bulb shooting mode, a signal will be sent when the flash is fully charged.
Since CCEF becomes "0", the gate G18 is disabled, and 1/60 second, which is the output of the amplifier OP7, which is set to the strobe-only seconds, is stored. After the release magnet Mg ₂ is released as described above, when the first curtain starts due to the mechanical sequence operation, the count switch SW ₄ is turned off, and the gate G 44 outputs a short pulse using Delay 4 and gate G 59 to reset the counter CT 2. (Fig. 3 Q, R). When both hour/second correction switches SW ₁₅ and SW ₁₆ are turned on, gates G49 and G50 are opened, and the 1024 Hz and 2048 Hz signals from counter CT2 are input to gate G57 via gates G55 and G56. . Therefore, the output of gate G57 is input to CP of D-type flip-flop _F6 via G58. The clock pulse input of this flip-flop _F6 is set at the rising edge of 1024Hz x 2048Hz after the reset of the flip-flop _F6 is released (CNTR falls), so the time is approximately
It becomes 250 μS (S in Figure 3). The moment the Q output PRCT of this flip-flop _F6 becomes "1",
Gate G73 by Delay5 and gate G73
A reset pulse PRER is output to the output of the counter CT2, and the counter CT2 is reset via the gate G44 (T in FIG. 3).

[Table] The combination of opening and closing of the above seconds correction switches SW ₁₅ and SW ₁₆ creates the seconds correction time shown in Table 2. Since the seconds correction obtained by the switches SW ₁₅ and SW ₁₆ is discontinuous as shown in Table 2, fine adjustment during this time can be performed using a mechanical governor. The mechanical parts in this case are 250
Since the adjustment can be made within μs, the member can be made smaller. By using such a mechanical member and an electric correction circuit together, it is possible to continuously correct over a wide range of 250 .mu.s to 1250 .mu.s. Gate G
When counter CT2 is reset by the PRER signal from 73, the actual shutter time is counted based on the information from counter CT1. As an example, the stored information of counter CT1 is sequentially "0, 0, 1, 0, 0,
0,0''. At this time, the output terminal "0" of the 4-wire-16-wire decoder DE1 becomes "1". As a result, gate G35 is opened and counter CT2 is input to gate G35.
The output of 8192Hz is countered via gate G36.
Input to CT3. Counter CT3 performs counting in synchronization with the fall of the pulse from gate G36, and when it counts up to 8, the output CT8E from terminal 8 becomes "1", and when it counts 4 more, 3 EX -OR gate G
The two inputs of each of 38, G39, and G40 match. As a result, the gate G41 becomes "1", the output CNTE of the gate G43 becomes "1", and the RS
Flip-flop _F4 is reset. This turns off the shutter control magnet Mg ₃ and ends the exposure. The actual time given in this example is 1/8192 x 12 = 1/68
It will be 3 seconds. This real-time counting circuit can be expressed by the following equation. That is, if the memory of the counter CT1 is 10A for the integer part and B for the decimal part, the TV will be A+B/8, and the actual time will be 1/8×2A·(8+B). Here, A is -2≦A≦10, and B is 0≦B≦7. The counter CT3 is released from the reset state by the output of the gate G37 when the signal PRCT becomes "1" after the exposure time correction count. Also a decoder
If the output of DE1 becomes 12 or more, gate G
22 output OV4S becomes “1” and the counter
The CNTE signal is set to "1" after 16 counts of 4Hz output (after 4 seconds) on CT3. As a result, the exposure time is 4 as shown in Table 1.
It is designed so that it does not become longer than seconds. Next, the operation during self-timer shooting will be explained. Switch SW ₇ is turned on during self-timer shooting. When the switch _SW1 is turned on by the first release stroke, the signal _SW1S becomes "0". At this point, switch SW ₂ is off.
SW ₂ S is "1". When the switch _SW7 is turned on and _SW7S becomes "0", the output SLFR of the gate G68 becomes "1". This signal is input to one side of the gate _G5 of the A/D conversion circuit, and its output is the counter CT.
Reset all 1. In other words, A/D conversion is prohibited in this state. At the same time, the outputs of gates _G7 and _G6 become "1", and the input of amplifier OP10 of the Miller integration circuit is connected to amplifier OP9, and the diode is connected as described above.
Due to the action of _D5 , the output of the amplifier OP10 is maintained at a constant voltage lower than the constant voltage Vc. Then, when switch SW ₂ is turned on by the second release stroke,
Both the signals SW ₁ S and SW ₂ S become "0", current is passed through the shutter control magnet Mg ₃ for 8 ms in the operation described above, and after checking the prohibition voltage, etc., the Q output RELS of the flip-flop F ₅ is turned on. becomes “1”. This RELS rising signal causes D
The Q output SLFA of the type flip-flop _F1 becomes "1" (V, W, X, Y in FIG. 3). At the same time, gate G68 is inhibited by this RELS signal "1" and its output SLFR becomes "0". At this time, the output of gate _G6 continues to be "1", counter CT1 is released from reset, and CP input is
When SLFM becomes “1”, this becomes a gate.
Counter CT1 with 4Hz signal via G ₃ and G ₂
Enter. At this time, the counter CT2 is at the moment when the Q output RELS of the flip-flop _F5 becomes "1", that is, only the 64 Hz bit becomes "1". Therefore, the counters are sequentially started from this state, and when the bits B1 and B4 of the counter CT1 are set, that is, about 10 seconds, the gates G ₉ and G ₈ are activated.
The output of SLFA becomes "1", the flip-flop _F1 is reset, and the Q output SLFA becomes "0". This time, that is, the time when SLFA is "1" is the self-timer time. Gate G in this self time
19, the gate is opened by the signal SFLA at G20, and by bit B4 of the counter CT1,
Signals of each frequency pass through gate G20 for the first 8 seconds and then through gate G19 for the next 2 seconds, but the duty at this time is gate G20.
Since the 2 Hz of G19 operates with a duty of 1/4 and the 8 Hz of G19 with a duty of 1/4, the self-display LED 1 is driven by the output via the gate G21 and the buffer amplifier (FIG. 3 Z). When the self time period ends as described above, the signal SLFA becomes "0", so that the same sequence operation as the above-described sequence operation when the self is not used is performed. In addition, the counter
In CT2, the Q output of flip-flop _F1
When SLFA is "0", that is, at the end of the self time, all bit outputs are "0", so until the next 8Hz output becomes "1" (about 60ms)
Flip-flop _F2 is not set. Therefore, after approximately 60ms, the D input of flip-flop _F3
MEOK becomes "1" and the sequence shifts to memory/exposure control. Next, the outside photometry range display section M will be explained.
If the film used in the camera is of high sensitivity, or when performing aperture metering photography, even if the appropriate exposure time is within the usual range, the light actually received by the photovoltaic element (for example, SPC) may be very weak. In general, the photometry accuracy of a light receiving element deteriorates in the case of such weak light, making it difficult to take a photograph at an appropriate exposure value. This circuit is for displaying a warning on the display element LED2 in the display section M in FIG. 1 in such a state. That is, the photoelectric signal BVO from the photometry section A and the calculation section B is sent to the comparator CP of the display section M.
2 to the inverting input and compared with a reference voltage V _c to the non-inverting input. When the incident light to the light receiving element SPC is small, the non-inverting input of comparator CP2 becomes higher than the inverting input, and comparator CP
The output of 2 becomes "1". Gate G66 inputs 4 Hz and 8 Hz from counter CT2, and generates a 4 Hz duty 1/4 signal to its output. When the output of CP2 is "1", this flows to display element LED2 via gate G67. Display blinking. Note that the Q output of flip-flop _F7 is input to gate G67, and when switch SW ₂ is turned on by the second stroke of the release and the camera starts the release operation, the warning display by LED 2 will turn off. ing. As described in detail above, according to the present invention, based on the release operation, pulse current is first applied to the coil of the shutter closing electromagnet for a predetermined period of time to check for wire breakage in the coil, and current is applied to the shutter closing electromagnet. When the current flows, the shutter sequence proceeds, and when no current flows, the shutter sequence stops, so the shutter does not open or close, giving the photographer the ability to detect a malfunction. It is possible to provide a camera malfunction prevention device that can make reliable judgments and has the advantage of not wasting film.

[Brief explanation of the drawing]

Fig. 1 is an exposure control circuit diagram of a camera equipped with a malfunction prevention circuit according to an embodiment of the present invention, Fig. 2 is an internal configuration diagram of the camera shown in Fig. 1, and Fig. 3 is shown in Fig. 1. This is a timing chart of each part of the circuit. 10...Release button, SW ₁ ...Switch,
SW ₂ ...Switch, Mg ₂ ...Magnet for electromagnetic release, Mg ₃ ...Magnet for shutter control, F ₅
...flip-flop, TR ₄ ...transistor,
G62...Gate.

Claims (1)

[Claims] 1. The first switch is operated by the first stroke operation of the release button to start supplying power to the circuit, and the second switch is operated by the second stroke operation, and the second switch is activated by the second stroke operation. In a camera that advances the shutter sequence by controlling the operation of a release electromagnet that subsequently opens the shutter and the operation of a shutter closing electromagnet that closes the shutter by the operation of the switch, the release button a detection energization circuit that supplies an energization pulse for a predetermined time to the coil of the shutter closing electromagnet based on the operation signal of the second switch due to the second stage stroke operation; and when the detection energization circuit is activated. , a detection circuit that generates a first signal when the current due to the pulse flows through the coil, and generates a second signal when the current does not flow due to disconnection of the coil, etc.; An electromagnet control circuit that starts the shutter sequence based on a first signal and stops the shutter sequence based on the second signal from the detection circuit. Camera malfunction prevention device.