JPS6160518B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory suitable as a memory (memory device) using a MOS transistor (also referred to as an insulated gate field effect transistor).

In this type of semiconductor memory, the column lines of the cell array may be left in an electrically floating state when they are not selected, and in MOS memory in particular, high-speed operation of the memory may be inhibited due to fluctuations in substrate voltage, etc. , malfunctions were occurring.

FIG. 1 shows a semiconductor memory formed by integrated circuits on a semiconductor substrate, where 1 ₁ , 1 ₂ , . . . are row lines in a cell array, 2 are address inputs A ₀ , A ₁ , A ₂ .
A row decoder that selects one of the row lines 1 ₁ , 1 ₂ , ... based on , 3 ₁₁ , 3 ₁₂ ..., 3 ₂₁ , 3 ₂₂ ,
... are memory cells made of MOS transistors, and the memory cells are driven by the corresponding row lines. Among these memory cells, those whose one ends (drains) are connected to the column lines 4 ₁ , 4 ₂ .
For example, cell 3 ₂₂ which is open corresponds to "1" storage. The other ends of these memory cells are connected to a source potential supply terminal V _S (ground). column line 4
₁ , 4 ₂ , ... are column selection transistors 5 ₁ , 5
₂ , . . . are inserted, and the gates of these transistors are connected to the column decoder 6. The column decoder 6 selectively drives one of the transistors 5 ₁ , 5 ₂ , . . . based on address inputs a ₀ , a ₁ , a ₂ , . The voltage sense circuit 7 detects whether the output data to the selected column line is "1" or "0" and outputs the detected data via the buffer circuit 8. The source and gate of the depletion transistor 9 as a load element are connected to the drain side common connection terminal (sense input) of the column selection transistor, and the drain is connected to the supply terminal 10 of the power supply voltage _Vc . Here, all the MOS transistors used are N-channel type, and the transistors other than the load MOS 9 are enhancement type, and the power supply voltage V _c can be considered to be at a higher level than the ground potential.

By the way, in the case of a memory configured as shown in Fig. 1, when there is power supply noise, the potential of the electrically floating column lines will change due to fluctuations in the substrate potential, and internal nodes (for example, the row lines) will fluctuate. ), the potential of the column line fluctuates through the gate of the cell. In addition, when a column line is not selected and the column line is electrically floating, if a separate substrate bias is applied (three power supply system), the column line or the memory cell connected to the column line The potential of the column line tends to fall to the substrate potential due to leakage current of the PN _junction at the drain _{, etc. of} Then, when the column line potential drops to "V _G - V _th ", the column selection transistor turns on, the leakage current is guaranteed by the load transistor 9, and the column line potential becomes the source potential (usually 0 volts). On the other hand, it is maintained at a certain constant negative voltage. Also EPROM (Erasable)
In devices that are directly exposed to external light such as ROM (Programmable ROM), nodes (e.g. column lines) that are electrically floating due to photocurrent in the PN junction, etc. The potential becomes negative by the amount of voltage. When the above state occurs, the selected column line must be charged from a negative potential, and the data read speed is reduced accordingly. For example, if the substrate becomes negative potential due to noise or the like during data reading, all non-selected column lines that are in an electrically floating state become negative potential due to the coupling capacitance with the substrate, and as a result, the column selection transistor that was in the off state becomes When turned on, each column line must be completely charged by the load transistor 9, which results in charging a very large capacitance, and therefore the data read speed becomes extremely slow. Furthermore, when the substrate potential decreases after data reading and becomes the same state as above, if the potential of the node 11 is in the "1" state due to the column selection transistor being turned on, the voltage sense circuit 7 becomes "1" as the level decreases. 0" and outputs erroneous data until the node 11 is charged to "1", resulting in malfunction.

The timing at which such column line or substrate potential fluctuations occur is not constant, and may cause a delay in so-called access operations or various malfunctions.

The present invention has been made in view of the above-mentioned circumstances, and solves the above-mentioned conventional problems by providing a memory main body with means for maintaining the column line near the source side potential of the memory cell when the column line or substrate potential changes. The aim is to provide a semiconductor memory that can be completely wiped out.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit used to explain the same embodiment, but here it is an example of a memory that corresponds to that in FIG. Explanation will be omitted. The feature here is that the drain of the N-channel transistor 21 ₁ is connected to the column line 4 in order to maintain the column line near the voltage V _S when the column line 4 ₁ , 4 ₂ , ... is in an electrically floating state.
₁ , the drain of the N-channel transistor 21 ₂ is connected to the column line 4 ₂ , and the drain of the transistor corresponding to each column line is similarly connected to the output terminal 23 of the voltage supply circuit 22 to the transistor 21 ₁ , 21 .
_2. Commonly connected to the gates of... Further, the sources of _{the transistors} 21 ₁ , 21 ₂ , . type transistors 25 are connected in series, and transistors 24
The gate of the transistor 25 is connected to the source of the transistor 25, and the gate of the transistor 25 is connected to the drain of the transistor 25, that is, the output terminal 23. Note that here the transistor 21
₁ , 21, ₂ ,...25, etc. are formed simultaneously in the integrated circuit manufacturing process, and have the same shape (characteristics), and the output potential of the output terminal 23 of the voltage supply circuit 22 is slightly higher than the threshold voltage of the transistor 25. The value is high.

If the configuration is as shown in FIG. 2, even if the column line ₄₁ among the column lines is in a voltage floating state and has a negative potential, the transistor ₂₁₁ becomes conductive and the voltage on the V _S side increases. It is quickly transmitted to the column line _4-1 , and the column line _4-1 becomes the source side potential V of the memory cell.
It becomes approximately the same value as _S. This operation is performed in the same way even if the column line ₄₁ becomes negative potential for any of the reasons mentioned in FIG. 1, and since the column line ₄₁ is charged from near the V _S potential, Access time can be shortened, and row line 4
This also prevents malfunctions such as "1" data obtained at ₁ becoming "0" midway through. Note that after the column line ₄₁ is brought to the V _S level by the transistor ₂₁₁ , the transistor ₂₁₁ is turned off.
It does not cause any trouble to the circuit operation.

FIG. 3 is a concrete circuit diagram of the voltage supply circuit 22, which is practical. However, here the second
Contrary to the case shown in the figure, transistors 21 ₁ , 21
The driving voltages of transistors ₂ , . . . are set to be lower than the threshold voltage V _th of these transistors.
This can be roughly explained as follows. That is, the third
If each transistor used in the circuit shown in the figure is formed simultaneously with the transistors 21 ₁ , 21 ₂ , etc. in the integrated circuit manufacturing process and has the same shape (characteristics) as these, then the connection end 36 is formed by the transistors 31 and 32.
The potential of the connecting end 23 becomes 2V _th , and therefore the potential of the connecting end 23 becomes V _th due to the transistor 34, but the output potential of the connecting end 23 becomes less than V _th due to the presence of the transistor 35. Here, transistors 31, 32, 34, and 35 are of N-channel enhancement type, and transistor 33 is of depletion type (load).

It should be noted that the present invention is not limited to the above-described embodiment, and may be configured, for example, by using a P-channel type MOS transistor. Furthermore, the present invention is applicable not only to static ROM, but also to dynamic ROM, and even RAM (Random Access
The present invention can also be applied to memory devices by providing specific parts of the circuit of the present invention in these column lines.

As explained above, according to the present invention, a means is provided to maintain the column line near the source side potential of the memory cell when the column line or substrate potential changes.
We can provide semiconductor memory that operates at high speed and prevents malfunctions.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional semiconductor memory.
FIG. 2 is a circuit diagram used to explain one embodiment of the present invention, and FIG. 3 is a circuit diagram showing a specific example of the main part of the same circuit. 1 ₁ , 1 ₂ ... row line, 2 ... row decoder, 3 ₁₁ - 3
₂₂ ...Memory cell, 4 ₁ , 4 ₂ ...Column line, 5 ₁ , 5
₂ ... Column selection transistor, 6... Column decoder, 7...
Voltage sense circuit, 9...Load MOS transistor,
DESCRIPTION OF SYMBOLS 10... Power supply, 11... Node, V _S ... Source potential supply end, 21 ₁ , 21 ₂ ... Transistor for column line potential stabilization, 22... Voltage supply circuit.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory formed by an integrated circuit on a semiconductor substrate, a plurality of row lines, a row decoder that selects the row lines, and memory cells driven via the decoder and the row lines are provided. a plurality of column lines provided to receive data from this memory cell, a column decoder that selects this column line, a voltage sense circuit that detects the voltage of the column line, and a load connected to the column line. a MOS element, one end of which is connected to a column line and the other end of which is connected to a source-side potential supply end of the memory cell;
1. A semiconductor memory comprising: holding means for holding a gate of an element at a potential near a threshold value of the MOS element. 2. The holding means includes a load transistor provided between a power source and an output terminal, and a MOS transistor whose gate and drain are connected to the output terminal and whose source is connected to a source-side potential supply terminal of the memory cell. , the potential of the output terminal is
2. The semiconductor memory according to claim 1, comprising a MOS circuit whose voltage is slightly higher than the threshold voltage of a MOS element.