JPS6159775A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to an improvement in an electrode lead-out portion of a transistor in a bipolar semiconductor integrated circuit device (hereinafter referred to as BIP-IC).

[Prior art 1 In short, transistors in BIP/IC are pnn
Junction separation 1 Oxide film separation using selective oxidation technology.

Alternatively, it is formed into an electrically independent island by a method using 3ffl expansion. Here, a method for forming an npn)-transistor using the oxidation misdistribution m method will be described. Of course, when using the above-mentioned various separation methods other than this, it can also be applied to pnp transistors.

FIGS. 1A to 1E are cross-sectional views showing the main process steps of a conventional semiconductor device manufacturing method. The conventional method will be briefly explained below with reference to this figure. Decrease 11
! After selectively forming a p-type (p-type) silicon substrate 1 with a high concentration of materials, an n''-type layer 2 with a high level of consumable materials and becoming a collector buried layer, an n-type epitaxial layer 2 is formed on them. j
Grow l13 [Figure 1(a)].

Next, an isolated oxide layer 111 is placed on the row-type epitaxial layer 3.
Form 02. That is, selective oxidation is performed using the enriched III 201 formed on the underlying oxide film 101 as a mask. At this time, a p-type layer 4 for channel cut is simultaneously formed under this isolation oxide 5102 [FIG. 1(b)]
].

Next, the nitride film 2 used as a mask for the selective oxidation described above is
01 along with the underlying oxide film 101, a new ion implantation protection oxide film 103 is formed, and the photoresist Il! (The photoresist film at this stage is not shown) is used as a mask to remove the p+ type layer 5, which will become the external base layer.The above photoresist film is then removed, a new photoresist fi1301 is formed, and this is used as a mask. A p-type layer 6, which will become an active base layer, is formed by ion implantation [FIG. 1(C)].

Next, photoresist! 1301 is removed, a passivation film 401 generally made of phosphosilicate glass (PSG) is deposited, and heat treatment is performed to anneal the base ion-implanted layers 5 and 6 and to finish baking the PSG film 401. After forming the external base layer 51 and the active base layer 61, PSGI! ! 401CP) NEi1
7) [Form L70 and 8°, and form a 0+ type layer 7 to become an emitter layer and an n+ type layer 8 to become a collector electrode extraction layer by ion implantation [Fig. 1 (d)
)].

Thereafter, each ion implantation layer is annealed to complete the external base layer 52 and active base layer 62, as well as forming the emitter layer 71 and collector electrode extraction layer 81, and then base 1! An opening 50 for taking out the electrode is formed, and each opening 50, 70 and 80 is filled with metal silicide [platinum silicide (Pt -8+), palladium silicide <Pct -8i), etc. to prevent the electrode from being handled.
After forming the base electrode wiring 9. with a low resistance metal such as aluminum (AfL). Emitter electrode wiring 1
0 and collector electrode wiring 11 [FIG. 1<e
)].

FIG. 2 is a plan pattern diagram of a transistor manufactured by this conventional method. Figure 2(a) is a single base structure corresponding to Figure 1(e), and Figure 2(b) is a multi-base structure.
It has an emitter structure.

By the way, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these to improve the frequency characteristics. For this reason, in the above-mentioned W structure, a p+ type external space layer 52 is provided in order to reduce the base resistance, but this has the drawback of increasing the base-collector capacitance. The base resistance is between the emitter layer 71 and the base ff1ffi extraction hole 50.
In the conventional type, the distance between the base electrode wiring 9 and the emitter electrode wiring 1i 110 and the protrusion from each opening 50.70 of each electric bridge arrangement 119° 10 is the total distance. , and photoetching F#
Even if the electrical conductivity is improved and the spacing between the electric conductors is reduced, the protrusion described above will inevitably remain.

Furthermore, as is well known, in order to reduce the base resistance and increase the current drive ability, the
) may have a multi-emitter structure as shown in (). At this time, compared to the emitter length in Fig. 2(a), M
The emitter length L2 in FIG. 2(b) may be slightly smaller since it is considered that only the edge portion of the emitter facing the base electrode moves during high current/high frequency operation. However, if a multi-emitter structure is adopted, a base electrode is required between the emitters, resulting in a significant increase in base area. Furthermore, the base distribution fa@ area also increases.

[Overview of the Invention] The present invention has been made in view of the above-mentioned circumstances, and includes a method in which the base electrode is taken out directly from the active base closed region through a superimposed layer of a polysilicon film and a metal silicide layer. By forming a part of the emitter electrode with a polysilicon film and using this polysilicon film as a mask to open a contact for forming the base metal silicide, the distance between the emitter layer and the base electrode opening is There is no need to incorporate protruding portions of both electrode wirings from each hole, and the above-mentioned distance can be shortened.Furthermore, an increase in base-collector capacitance does not occur because an external base layer with a high impurity concentration is not used. Base as emitter structure @
It is an object of the present invention to provide a method for manufacturing semiconductor Bi that does not cause an increase in base-collector capacitance by minimizing the increase in product.

[Embodiment of the Invention] FIGS. 3(a) to 3(a) are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and show the same parts as the conventional example shown in FIG. are indicated by the same symbol. First, up to the state shown in FIG. 1(b), a p- type silicon substrate 1 is formed with an 0+ type collector buried layer 2. n-type epitaxial layer 3. After forming the channel cut p-type layer 4 and the isolation oxide [102], the first
Nitride film 201 and underlying oxide 1101 in figure (b)
is removed, an oxide film 103 for ion implantation protection is formed again, and a p-type layer 6, which will become an active base layer, is formed by ion implantation through a photoresist mask (not shown).
The above oxidation III near the region that should become the base N electrode opening
103 is removed, and polysilicon 110601 is deposited on the entire upper surface including the removed portion [FIG. 3(a)].

Next, p-type impurities are introduced into the entire surface of the polysilicon 111601, and sintering is performed to make the Cp-type dopant 6 an intermediate active base region 61, and then the polysilicon film 601 is selected. Etching is removed and oxidation is performed again to remove oxide film 1 at the location where oxide film 103 was.
05. Oxidized lQ1 is deposited on the remaining polysilicon film 601.
06e is formed, and 'PSGII!' is also printed on the entire top surface. J401
[Fig. 3(b)].

Next, selective etching is performed using a photoresist mask (not shown) to remove the oxide film 105 and PSGIi in the areas to become the emitter layer and collector electrode extraction layer.
401 is removed and a polysilicon film 602 is deposited.
After ion-implanting n-type impurities into this polysilicon film at a high concentration, driving is performed to diffuse them from the polysilicon film to form an emitter layer. 81 [Fig. 3(C)].

Next, the expanded polysilicon portion 602, which served as the above-mentioned diffusion source.
After selectively etching so as to leave only 603, a base contact window is formed using the resist table 302 as a mask [FIG. 3(d)].

At this time, the resist film 302 is placed inside the polysilicon 1!602 forming the emitter layer, and the polysilicon film 302 is partially used as a mask to form the base contact and the subsequent oxidation 11! on the polysilicon M601. J10
6. PSGII401 is removed by etching. A thick oxide M10 is formed on the n+ layer polysilicon G1602.603 by performing 6 oxidation at low temperature (approximately 800°C to 900°C).
8, and a thin oxide film 107 is formed on the p-temperature silicon substrate 62 and the p+ layer polysilicon film [FIG. 3(e)]
].

This is based on the well-known fact that silicon and polysilicon containing high concentrations of impurities such as phosphorus and arsenic undergo accelerated oxidation at low humidity.

Next, wash out only the oxidized IPJ107 and P
After forming a metal layer (not shown) that forms a metal silicide between the silicon and polysilicon films such as T, Pd, Ti, W, and MO on the entire upper surface by vapor deposition or sputtering, sintering is performed to form a metal layer. Silicide 1II 501.502 is formed on the exposed surface of the silicon substrate and the surface of polysilicon film 601, and then the metal silicide film is removed and the metal layer is removed by etching with aqua regia or the like [FIG. 3 (1')].

Next, nitriding for passivation! After depositing 1202 (la film may also be used), selective etching is performed on the nitrided FF202 and oxidized 11J108 to form a paste.
Contact hole 50 for R pole. After forming the emitter electrode contact hole 70 and the collector electrode contact hole 80, base electrode wiring 9. is formed using a low resistance metal such as AfJ. Emitter electrode wiring 10 and cholera)
Electrode wirings 11 are formed respectively [FIG. 3(g)].

Furthermore, as another example, when forming polysilicon l11601 that will become a part of the base electrode, as shown in FIG. The polysilicon film 601 comes into contact with the side wall of the island 3, and the contact surface 90 of the polysilicon 1601 with the base layer 62 in FIG. Etching is best if the diffusion J!163 from the polysilicon film 601 is at the same depth as the base layer 62 in terms of breakdown voltage. The depth of the base layer can be controlled and crystal defect prevention can be improved.

FIG. M5 (a) is a plan pattern diagram of a transistor manufactured in this way and corresponding to FIG. 2 of the conventional method.

As shown in FIG. 5(a), the emitter layer 71 and the base 1! Polysilicon Ml 601 connected to l pole 9
The distance D2 between j3 and the metal silicide m501 is determined by the overlapping part of the window opening for J diffusion (corresponding to 71) and the polysilicon 11602 that becomes the expansion 1aiIi, so the distance D2 is the same as the conventional distance shown in Fig. 12. You can make it smaller than you like. Not only does the base resistance become smaller by that amount,
Conventional p+ type external base layer 52 (several tens of Ω/mouth ~ 100
Low non-resistance metal silicide film 50' instead of
l (several Q/hole to several tens of Ω/hole) is used, so it is small.

Furthermore, without using the p+ type external base layer 52, the base layer 6
Since 2 itself is slightly smaller, the base-collector capacitance also becomes smaller, and the frequency vl characteristics of the 1-transistor are improved.

However, as shown in No. 61ffl (a),
The polysilicon film 601 that will become the base 1f pole is aligned with the separation edge (arrow A in the figure), the emitter contact is also aligned with the separation edge (arrow B in the figure), and the emitter polysilicon film 11802 is aligned with the contact (arrow A in the figure). C) In order to
Evil Figure 6 (b).

As in the case (0), the corner between the polysilicon films greatly changes from 0 to three times the normal value. Therefore, Figure 5 (
By adopting a double structure as shown in b), the base 1m-emitter dispersion distance 11fi D t remains as designed, even if the photolithography becomes the worst, as shown in Figure M7.

Furthermore, unlike the conventional double base structure, as shown in FIG.
Since the base electrode 1f is formed on three sides around the base electrode 1- and is connected to the polysilicon films serving as base electrodes on both sides, the base resistance can be reduced without increasing the base electrode 1f. Furthermore, the collector mff1601 is formed at a position facing the base emitter.

Note that although the polysilicon films of the base electrodes on both sides are connected by the A north wiring, the same performance can of course be obtained even if the polysilicon films made low in resistance by silicide are directly connected and then the Ai electrode wiring is performed.

[Effects of the Invention] As described above, according to the present invention, the base 1f pole is formed with a polysilicon film and a metal silicide film on both sides of the emitter.
f! The portion adjacent to the lead-out base layer is formed on the monolayer film, a part of the emitter 1 pole is formed with a polysilicon film, and this polysilicon film is used as a mask to form a base metal silicide film. - Since the contact is opened, the distance between the base electrode extraction region and the emitter layer can be reduced, and the base resistance can be reduced. Furthermore, in the multi-emitter structure, three sides around the emitter are connected to the base electrode by a metal silicide film so that a dedicated base electrode is not provided between each emitter, so the base area can be significantly reduced. Furthermore, since an external base layer with a high impurity concentration is not provided, the base-collector capacitance can be reduced, and a transistor with good frequency characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the main steps of a conventional manufacturing method. FIG. 2 shows a plane pattern of a transistor manufactured by a conventional method. FIG. 3 is a cross-sectional view showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a sectional view showing the main steps in manufacturing an embodiment of the present invention using another manufacturing method. FIG. 5 is a plan pattern diagram of an embodiment of the present invention. , FIG. 6, and FIG. 7 are cross-sectional views showing variations in 02 due to presetting accuracy in photolithography. In the figure, 1 is a p-type silicon substrate, 3 is an n-type epitaxial FIFf, 6.61.62 is a base layer, and 7.
71.71- is the emitter layer, 8.81 is the collector 'Il
tm extraction layer, 9 is a base electrode, 10 is an emitter electrode, 1
1 is the collector Iu1ti1102 is the isolation oxide film, 101
, 105, 106, 107.108 are silicon oxide films,
201 and 202 are nitride films, 302 is a resist film, 401
is PSGII, 600°601.602 is silicone,
500.501 indicates a metal silicide film. Representative Masuo Daiiwa Figure 1 Figure 1 Figure 21 Sono 3 old 302 Nire list A1 107, 108: Silicone drunken AL calculation 3 difficulty 501.502: 4-λ heshiri "S'ir-A"'X
50 寞 6 eyes 71 矧

Claims (2)

[Claims] (1) In a semiconductor device including at least two emitter layers formed by introducing impurities from a silicon film into an opening of an insulating film in a region where a base layer is formed, three sides of the emitter layer are made of silicon. A semiconductor device characterized by being surrounded by a metal silicide film connected to a base electrode made of a film. (2) The semiconductor device according to claim 1, wherein the connection to the emitter electrode is made through the silicon film, and no material other than the metal silicide film is formed between the respective emitter layers.