JPS6157710B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage divider for an A/D converter or a D/A converter, and particularly to a voltage divider with a MOS structure, in which each divided voltage is output. This article relates to a voltage divider that combines E-MOS and D-MOS switch configurations.

Conventionally, a voltage divider with a MOS structure has the configuration shown in FIGS. 1 and 2. In Figure 1, 1 is a terminal connected to the reference voltage (power supply voltage) of the voltage divider, 2 is a terminal connected to another reference voltage (ground voltage) of the voltage divider, and 3 is between terminals 1 and 2. This is an output terminal that outputs a divided voltage of the voltage. R ₁ ~ _{R i}
is a diffused resistance layer placed between terminals 1 and 2, and R ₁
is a first diffused resistance layer whose one end is connected to terminal 1;
_R2 is a diffused resistance layer whose one end is connected to the other end of the diffused resistance layer _R1 , and _R3 is a diffused resistance layer whose one end is connected to the other end of the diffused resistance layer _R2 . Thereafter, the diffused resistance layers are sequentially connected, and R _i is a diffused resistance layer whose one end is connected to the other end of the diffused resistance layer R _i-1 and the other end is connected to the terminal 2. Each of the diffused resistance layers R ₁ to _{R i} has a specific resistance value r ₁ to
A resistor r _i is configured and the voltage between terminals 1 and 2 is divided according to each resistance value r ₁ to _{r i} . S ₁₁ to S _i indicate the first stage switch configuration. S ₁₁ has one end with a diffused resistance layer
The switch _S12 connected to the connection point of R ₁ and R ₂ is a switch that connects one end to the connection point of the diffused resistance layers R ₂ and R ₃ and the other end to the other end of the switch S ₁₁ . _Each switch is successively connected to the connection _point of each _{diffused resistance} layer. This is a switch whose other end is connected to the other end of switch S1i _-1 . S ₂₁ to S ₂ 〓 indicate the second stage switch configuration. S ₂₁ is a switch that connects one end to the common connection point of switches S ₁₁ and S ₁₂ , and S ₂₂ connects one end to the common connection point of switches S ₁₃ and S ₁₄ , and the other end to the other end of switch S ₂₁ . It is a switch to do this. The following switches have the same configuration in sequence: S ₂ 〓 is a switch that connects one end to the common connection point of switches S _1i-3 and S _1i-2 , and S ₂ 〓 is a switch that connects one end to the common connection point of switches S _1i-1 and S _1i. This is a switch that connects to the common connection point of the switch S 2 〓 and the other end of the switch S ₂ 〓. S _j1 and S _j2 indicate the j-th switch configuration. S _j1 has one end switched to S _j-
1 , a switch connected to the common connection point of ₁ and S _j-12 , S _j
2 is a switch whose one end is connected to the common connection point of switches S _j-13 and S _j-14 , and whose other end is connected to the other end of switch S _j1 and the output terminal 3.

S1, 1, S2, 2, ~Sj, are control signals that control the conduction and non-conduction of the switches.
are mutually inverted signals. For example, when outputting the voltage at the connection point between the diffused resistance layers _R1 and _R2 , the control signals S1, S2...Sj are made conductive, and the control signals 1,
2. Make ... non-conductive.

FIG. 2 shows a pattern diagram of a MOS configuration of a portion of the circuit of FIG.

In Figure 2, R ₂ and R ₃ are the diffused resistance layers l2 and l, respectively.
It has resistance values r2 and r3 between 3. S1,1 represents a control signal line and is made of an Al layer due to the structure of the manufacturing process. Portions E1, E2, E3 indicated by diagonal lines
constitutes a switch with an Al gate MOS structure. G1, G2, and G3 are Al wirings for connecting the control signal lines S1 and S2 to each Al gate. C
1, C2, C3 are control signal lines S1, S2 and each Al
This is a contact that connects the wirings G1, G2, and G3. For example, when outputting the voltage at the connection point between the diffused resistance layers R2 and R3, in the n channel, the control signals S1, 2, ... are at "L" level, and the control signals 1, S2, ..., Sj are at "H" level. is applied and switched.

As mentioned above, in the conventional Al gate MOS structure voltage divider, the Al control signal line had to be made in a region different from the region of the diffused resistance layer.
The disadvantage was that the chip area became large. In particular, when constructing a voltage divider that outputs the contact voltages of a large number of diffused resistance layers, the chip area becomes extremely large. Another drawback was that the Al gate of the MOS structure and the Al control signal line had to be connected by Al wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS voltage divider with a small chip area.

The feature of the present invention is that a control signal line layer is formed on the divided voltage lead line of a voltage divider made of a diffused resistor or a capacitor, each intersection part is formed as a switch of MOS structure, and the control signal line layer of these MOS structure switches is The reason is that we used E-MOS for those that we wanted to turn on and off, and used D-MOS for those that we wanted to keep on regardless of the control signal.

Examples of the present invention will be described below.

In FIG. 3, 1 is a terminal connected to the reference voltage (power supply voltage) of the voltage divider, 2 is a terminal connected to another reference voltage (ground voltage) of the voltage divider,
3 is an output terminal that outputs a divided voltage of the voltage between terminals 1 and 2. R ₁ to _{R i} are diffused resistance layers arranged between terminals 1 and 2 or ion-implanted diffused resistance layers, R ₁ is the first diffused resistance layer whose one end is connected to terminal 1, and R ₂ is the first diffused resistance layer whose one end is connected to terminal 1. A diffused resistance layer whose one end is connected to the other end of the diffused resistance layer _R1 , and the subsequent diffused resistance layers are successively connected, and the i-th R _i has one end connected to the other end of the diffused resistance layer R _i-1 , and the other This is a diffused resistance layer whose end is connected to terminal 2. Each of the diffused resistance layers R ₁ to R _i has a specific resistance value.
r ₁ to r _i and the voltage between terminals 1 and 2 to each resistance value r ₁ to
Partial pressure is applied according to r _i . In the figure, T ₁₁ to T _12i constitute the first stage switch row. _T11 is a switch that connects one end to the connection point of the diffused resistance layers _R1 and _R2 ,
T ₁₂ is a switch that connects one end to the other end of switch T ₁₁ , T ₁₃ is a switch that connects one end to the connection point of diffused resistance layers R ₂ and R ₃ , and T ₁₄ connects one end to the other end of switch T ₁₃ . _T15 is a switch that connects one end to the connection point of diffused _resistance layers _R3 and _R4 , and _T16 connects one end to the other end of switch _T15 . The switch _T17 connects to the connection point between the diffusion resistance layers _R4 and _R5.The switch _T18 connects one end to the other end of the switch 17 and the other end to the other end of the switch _T16 . Switches are sequentially connected to the connection points of the diffused resistance layers, and T _12i-3
T i,2i-2 is a switch whose one end is connected to the connection point of the diffused resistance layers R _i-1 and R _i , and T _i,2i-3 is a switch whose one end is connected to the connection point of the diffused resistance layers R _{i-1 and R i.}
T _12i-1 is a switch that connects one end to terminal 2, T _i2i is a switch that connects one end to terminal 2, and T _12i-1 is a switch that connects one end to terminal 2.
This is a switch connected to the other end, and the other end is connected to switch T12i _-2 . These switch rows are
Consists of transistors with MOS structure, each of which is an enhancement type MOS transistor (E-
MOS) and a depletion type MOS transistor (D-MOS).
That is, in the first row of switches, T ₁₁ , T _1(i) , T _1(i+1) (1) Here, the relationship i=4t (t=1, 2, 3,...) A satisfying switch MOS is constructed from E-MOS, and the following relationship is established: T _1(i) T _1(i+1) (2) where, i=2t (t=1, 3, 5, 7,...) A switch MOS that satisfies the following is configured with D-MOS.

T ₂₁ to T _2i constitute the second stage switch row.
T ₂₁ is a switch that connects one end to the other end of switch T ₁₂ , T ₂₂ is a switch that connects one end to the other end of switch T ₂₁ , T ₂₃ is a switch that connects one end to the other end of switch T ₁₆ , T ₂₄ is a switch whose one end is connected to the other end of switch T ₂₃ and the other end is connected to the other end of switch T ₂₂ .
_2i-3 is a switch that connects one end to the other end of switch T _12i-6 , T _2i-2 is a switch that connects one end to the other end of switch T _2i-3 , and T _2i-1 is a switch that connects one end to the other end of switch T _{12i- 2}
The switch T _2i connects one end to the switch T _2i-
1 and the other end is connected to the other end of switch T _2i-2 . These switch rows are also E-
T ₂₁ , T _2(i) , T _2(i+1) (3) Here, the relationship i=4t (t=1, 2, 3, 4,...) is A satisfying switch is composed of E-MOS and satisfies the relationship T _2(i) , T _2(i+1) (4) where i=2t (t=1, 3, 5, 7,...) The switch consists of D-MOS.

T _j1 to T _j4 constitute a j-th switch row.
T _j1 is a switch connecting one end to the other end of T _{j- 1,2} ;
T _j2 is a switch that connects one end to the other end of switch T _j1 and the other end to output terminal 3, T _j3 is a switch that connects one end to the other end of switch T _j-16 , and T _j4
is a switch whose one end is connected to the other end of the switch T _j3 and the other end is connected to the output terminal 3.

These switch rows are also made of a combination of E-MOS and D-MOS; for example, T _j1 and T _j4 are E-MOS and D-MOS.
MOS, T _j2 and T _j3 are composed of D-MOS.

S1, 1, S2, 2, . . . , Sj are control signals for making each switch row conductive or non-conductive, and S1, S2, . For example, when outputting the voltage at the connection point between the diffused resistance layers R ₂ and R ₃ , S
Apply "Low" level to 1, 2,...,
A "High" level is applied to 1, S2, . . . Sj.

Here, the switch composed of D-MOS is always in a conductive state regardless of the control signal.

Figures 4a and b are MOS parts of the circuit in Figure 3.
A structural pattern diagram and cross-sectional structure are shown.

In Fig. 4a, R ₂ , R ₃ , _and R ₄ are diffused resistance layers, respectively.
Represents the resistance values r _{2 ,} r ₃ , r ₄ between l 3 and l ₄ , and S1, 1
are signal line patterns that provide mutually inverted control signals. The part where the S1,1 signal line and the diffusion layer intersect (indicated by diagonal lines in the figure) is the switch, but the S
The 1,1 signal line and the gate layer of the switch MOS are made of the same material, that is, polycrystalline silicon, and the diffusion layer extending from the connection point of the diffused resistance layers _R1 and _R2 intersects with the signal line S1,1. M.O.S.
Each transistor is E-MOS (or D
-MOS) E11, D-MOS (or E-
MOS) D11 structure. The MOS transistors formed by the intersection of the diffusion layer extending from the connection point of the diffusion resistance layers R ₂ and R ₃ and the signal lines S1, 1 are called D-MOS (or E-MOS) D12, E-, respectively.
It has a MOS (or D-MOS) E12 structure.
Similarly, the MOS transistors formed by the intersection of the signal lines S1 and S1 with the diffusion layers extending from the connection points of the diffusion resistance layers R ₃ and R ₄ and R ₄ and R ₅ are E-MOS transistors, respectively.
(or D-MOS) E13, D-MOS (or E-MOS) D13, D-MOS (or E-MOS)
MOS) D14, E-MOS (or D-MOS)
It becomes E14.

Therefore, “High” is now applied to the control signal line S1.
When “Low” level is applied to level 1, P
1 terminal and P2 terminal each have a diffused resistance layer R ₁
The contact voltage of R ₂ and the contact voltage of the diffused resistance layers R ₃ and R ₄ are output.

By combining E-MOS and D-MOS in this way and using the same material for the control signal line layer and the switch MOS gate layer, the control signal line can be overlapped on the diffusion layer, and the control signal line can be overlaid on the diffusion layer. Since contact between the line and the gate layer is eliminated, the area of the control signal line and the contact, and the required design (manufacturing) distance between the contact and each layer are reduced, so the chip area of the voltage divider is reduced.

FIG. 4b shows a cross-sectional structure of the pattern configuration shown in FIG. 4a, where 10 is the substrate, 11 is the diffused resistance layer, and the drain end (or source end) of the switch E-MOS (or D-MOS). 12 is a diffusion layer that constitutes the source end (or drain end) of E-MOS (or D-MOS) and the drain end (or source end) of D-MOS (or E-MOS), 13 14 is the gate oxide film of the switch MOS, 15 and 16 are the polycrystalline silicon gate layers of the switch MOS, 19,2
0 is the channel of the switch MOS.

Here, the channels 19 and 20 formed under the gate layers 15 and 16 have an E-MOS (or D-MOS) and a D-MOS (or E-MOS) structure, respectively.

Generally, in order to accurately transmit the potential at the drain end (or source end) to the source end (or drain end) of a MOS transistor, V _GS - V _th = (V _G - V _Ri ) - V _th > 0 (5) must be established. Here V _GS is MOS
The gate-source voltage of the transistor, V _th is the threshold voltage, V _Ri is the contact voltage of the i-th and i+1-th diffused resistance layers, and V _G is the gate voltage. Therefore, depending on the voltage level of the control signal, D-
Lower the threshold voltage of MOS.

The drain currents of D-MOS and E-MOS with respect to V _GS are expressed in the form shown in FIG. In Figure 5, V _th
E , V _thD and V _thD1 are E-MOS and D-, respectively.
It represents the threshold voltage of MOS and D-MOS, which has a lower threshold value.

Similarly, in order to output an accurate contact voltage in E-MOS, equation (5) must be satisfied, but in the case of E-MOS, the voltage level of the control signal must be increased.

Figure 6a shows a cross section of a conventional MOS switch structure, with PSG (phosphosilicate glass) 17 as an insulating layer on top of the E-MOS or D-MOS structure.
Since there are Al wiring layers G1 to G3 on top of the Al wiring layers G1 to G3, it is not possible to provide any other wiring layer on the voltage divider. On the other hand, in the above embodiment, a part of the polycrystalline silicon control signal line layer is a gate layer, and this control signal line layer and gate layers 15, 1
Since there is no Al layer etc. on the PSG 17 that covers the PSG 17, as shown in Figure 6b,
If the Al layer 18 is provided and grounded, it will have the effect of preventing noise. Furthermore, since another wiring layer can be provided instead of the entire Al layer, the degree of freedom in arranging the voltage divider on the chip increases.

FIG. 7 is a diagram explaining the wiring and arrangement advantages of the voltage divider of the present invention, and FIG.
where 100 represents an integrated circuit chip, and x ₁ and y ₁ represent dimensions, respectively. 200 is a logic circuit used in the integrated circuit and related circuits, 300
indicates a voltage divider. Figure 7a shows the control signal line.
In the case of a conventional chip structure including an Al layer, the voltage divider 300 has a structure as shown in FIG. 7b. Here, 301 is a portion including the diffused resistance layer, switch row, and control signal layer of the voltage voltage divider, and 302 is a wiring that supplies control signals to the portion 301 including the diffused resistance layer, switch row, and control signal layer of the voltage voltage divider. In the layer portion, an area for the wiring layer portion 302 is required.

FIG. 7c is a diagram showing the arrangement of a voltage divider configuration according to an embodiment of the present invention, in which a diffused resistance layer,
Wiring layer section 3 in Figure 7b that does not require a wiring layer section for a voltage divider other than the switch row and control signal layer.
A circuit for improving other functions can be inserted into the section 02. Furthermore, if there is no circuit to be inserted into the wiring layer portion 302 of FIG. 7b, the chip size can be reduced. In FIG. 7d, the area corresponding to the wiring layer portion 302 is removed to reduce the chip size, and the logic circuit and related circuit portions are divided into two parts 201 and 202, and between them, the voltage according to the embodiment of the present invention is Although the configuration is shown in which a voltage divider 301 is arranged, even in such a case, the signal line connecting the circuits 201 and 202 can be placed on the PSG of the voltage divider.

Generally, the on-resistance _Rpo of a MOS transistor is expressed by the following equation.

R _po =1/β・W/L・(V _GS −V _th ) (6) Here, β is the channel conductance constant,
L is the channel length of the MOS transistor, W is the MOS
The channel width of the transistor, V _GS is the gate-source voltage of the MOS transistor, and V _th is the threshold voltage of the MOS transistor.

As is clear from equation (5), the on-resistance of a MOS transistor decreases in inverse proportion to (channel width/channel length).

FIG. 8 shows the on-resistance characteristics of the E-MOS and the on-resistance characteristics of the D-MOS with respect to the W/L. In the switch configuration of the above embodiment, the resistance of the switch per stage is the sum of the on-resistance of the E-MOS and the on-resistance of the D-MOS. For example, if the MOS dimensions of the first stage switch row are selected as the W/L of the first stage in Figure 8a, the on-resistance of the first stage unit switch is (r _E1 + r
_D1 ). Therefore, if all of the switch rows up to j stages are configured with the W/L dimensions of the first stage, the resistance will be J(r _E1 +r _D1 ), and the resistance from each connection point of the diffused resistance layer to the output terminal will become large.

In the voltage divider according to the above embodiment, as the number of stages in the switch array increases, the number of switches decreases by 1/2 per stage, so the area of the switch portion becomes available, and the size of the MOS for the switch can be increased. Therefore, if the W/L of the switch MOS in each stage is increased as the number of stages increases as shown in FIG. 8b, the on-resistance of the switch MOS decreases for each stage.

In this case, for each stage of switches from the diffused resistance layer.
The characteristics of the total on-resistance up to the MOS are as shown in Figure 8b, and the total on-resistance _ΣRpo is only decreases.

FIG. 9 shows a configuration pattern diagram of a voltage divider when the switch MOS dimensions of each stage are changed.
1 is a terminal connected to a reference voltage (power supply voltage) of the voltage divider, 2 is a terminal connected to another reference voltage (ground voltage) of the voltage divider, and 3 is an output terminal of the voltage divider. R ₁ to _{R i} are diffused resistance layers each having a length l ₁ to
It has a specific resistance value corresponding to l _i . E ₁₁ ~ _{E 1
i} , D ₁₁ to _{D 1i} are E-MOS and D-MOS that constitute the first stage switch row, and the dimensions of each MOS are as follows.
W ₁ /L ₁ . E ₂₁ to _{E 2} 〓, D ₂₁ to _{D 2} 〓 are E-MOS and D-MOS that constitute the second stage switch row.
The dimensions of each MOS are W ₂ /L ₂ . Thereafter, the number of stages of the switch row increases sequentially, and the dimensions of the E-MOS and D-MOS of the j-th switch row are each W _j /L _j . Here, the MOS dimensions of each stage are W ₁ /L ₁ <W ₂ /L ₂ <...<W _j /L in order to reduce the total on-resistance of all switch MOSs inserted between the diffused resistance layer and the output terminal. _j (8) is satisfied.

According to the above embodiment, the impedance between the diffused resistance layer and the output terminal of the voltage voltage divider is lowered by changing the switching MOS for each stage of the voltage voltage divider having a multi-stage switching configuration.

E- used in the voltage divider according to the above embodiment
A unit switch that combines MOS and D-MOS is connected in series between the diffused resistance layer and the output terminal, but the E
- It is also possible that switches using a combination of MOS and D-MOS are connected in parallel. FIG. 10 shows an embodiment in which the circuits are connected in parallel.

In the same figure, M ₁ connects one end to the diffused resistance layers R ₁ and R ₂
M ₂ is a switch connected to the connection point of the diffusion resistance layers R ₂ and R ₃ and the other end is connected to the output terminal 3, and the other end is connected to the output terminal 3. Each switch is sequentially connected to the diffused resistance layer and the output terminal, and M _i-1 connects one end to the diffused resistance layer R _{i-1
M i is} a switch that connects one end to the terminal 2 and the other end to the output terminal 3. I ₁ to I _i respectively conduct the switches M ₁ to _{M i} ;
This is a control signal for making it non-conductive.

When the switch configuration of FIG. 10 is constructed with a MOS structure and the control signal wiring layer is wired in the same layer as the gate layer, each control signal layer intersects with a layer extending from the connection point of each diffused resistance layer. For example, control signal I ₁
intersects with i-1 layers (points marked with x in Figure 10). Therefore, the x mark in Figure 10 is D-MOS.
The switches M ₁ to _{M i} have an E-MOS structure, and the E-MOS is connected in parallel to the diffused resistance layer and the output terminal.
This is a switch row that combines D-MOS and D-MOS.

FIG. 11 is a partial MOS structure pattern diagram of FIG. 10, where R ₂ , R ₃ , and R ₄ represent diffused resistances, and M ₁ ,
M ₂ and M ₃ are of E-MOS structure, and all other switches are of D-MOS (D1, D2, and D3 in the figure) structure.

Although each of the above embodiments has been described using a resistive voltage divider using a diffused resistor as an example, a capacitive voltage divider comprising a capacitor made of a gate oxide film or the like can be similarly implemented.

As described above, the present invention combines the control signal line layer and the MOS
The gate layers of E-MOS and D are made of the same material, and the E-MOS and D
- By combining MOS, it is possible to use a part of the control signal line layer as it is as a gate layer, eliminating the need for dedicated space for the control signal line layer and reducing the chip area of the voltage divider. can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a partially omitted diagram showing a conventional voltage divider circuit, FIG. 2 is a partial diagram showing a chip pattern for realizing the circuit of FIG. 1, and FIG. 3 is a diagram showing an embodiment of the present invention. 4a is a partial diagram showing a chip pattern for implementing the circuit of the embodiment in FIG. 3; FIG. 4b is a partial cross-section of the chip in FIG. 4. Figure 5 shows the _VGS -I _D characteristics of a MOS transistor, Figure 6a is a partial cross-sectional view of the chip in Figure 2, Figure 6b shows the present invention in which the entire surface of the chip is covered with an aluminum layer. FIG. 7 is a diagram showing the area ratio of the voltage divider on the integrated circuit chip, and a is an example diagram showing the ratio of the conventional voltage voltage divider to the entire circuit, b is an example diagram showing the ratio of wiring layers in a conventional voltage voltage divider, c is a diagram showing the ratio of a voltage voltage divider in an embodiment of the present invention, and d is a diagram showing how the integrated circuit chip is made smaller by the unnecessary wiring layer. FIGS. 8a and 8b are diagrams showing an embodiment of the present invention in which the channel dimensions are
A diagram explaining the on-resistance of a MOS transistor, FIG. 9 is a diagram showing chip patterns of embodiments of the present invention in which the channel dimensions of the MOS switch are sequentially changed, and FIG. 10 is a diagram illustrating the voltage according to another embodiment of the present invention. 11 is a diagram showing a voltage divider circuit partially omitted, and FIG. 11 is a diagram showing a chip pattern for realizing the circuit of FIG. 10. R ₁ to R _i ...diffused resistance layer, S ₁₁ to S _j2 , T ₁₁ to _{T j
4} , M ₁ to M _i ... switch, 1, 2 ... reference power supply terminal, 3 ... output terminal, 10 ... board, 11, 1
2, 13...Diffusion layer, 14...Gate oxide film, 1
5, 16...gate layer, 17...PSG layer, G1~
G3...Al wiring layer, 18...Full surface Al layer, S1~
Sj, 1~...Control signal (line), _I1 ~ _Ii ...Control signal (line), _E1 ~ _E3 , _E11 ~ _E14 , _E11 ~ _E1i ,
E ₂₁ ~E ₂ 〓, E _j1 ~ E _j2 ...E-MOS, D ₁₁ ~
_D14 , _D11 ~ _D1i , _D21 ~ _D2〓 , _Dj1 ~ _Dj2 , _D1 ~ _D3
...D-MOS.

Claims (1)

[Claims] 1. A reference voltage is applied to both ends of a resistor array made of a plurality of diffused resistors or a capacitor array made of a plurality of capacitors made of gate oxide film, etc., and the resistor is connected via a switch that is turned on and off by a control signal. In a voltage divider that outputs each divided voltage of a column or a capacitor column, a control signal line layer is formed on each leader line layer for taking out each divided voltage, and a control signal line layer is formed at each intersection point. A MOS structure switch is constructed using the intersection of layers as a gate layer. Among these MOS structure switches, those that are turned on and off by a control signal are called E-MOS, and those that remain on regardless of the control signal are called D. - A voltage divider that is characterized by being MOS. 2. In the voltage divider according to claim 1, a plurality of voltage dividers are provided between each connection point for extracting each divided voltage and the output terminal of the voltage divider.
A voltage divider in which the MOS dimensions of the MOS structure switches are increased in order toward the output terminal, and the on-resistance of each MOS structure switch is successively lowered. 3. In the voltage divider according to claim 1, each divided voltage is connected to an E-MOS switch and a D-MOS switch, respectively.
The terminals are drawn out through a series circuit of MOS switches, each two adjacent terminals are connected in common, and each common connection end is drawn out through a series circuit of an E-MOS switch and a D-MOS switch. A voltage divider in which the lead ends are connected in common to every two adjacent ones, and the following connections are made in the same way to obtain the final output. 4. In the voltage divider according to claim 1, the leader wire layers for drawing out each divided voltage are formed in parallel with each other, and the other ends of each leader wire layer are connected in common to serve as an output terminal, A plurality of control signal line layers are formed on each leader line layer to intersect therewith, and among these control signal line layers, a first control signal line layer intersects with all the leader line layers, and a second control signal line layer intersects with all the leader line layers. The layer intersects other leader layers except the first leader layer, the third control signal layer intersects other leader layers except the first and second leader layers, and so on. A voltage divider in which the number of intersections between the control signal line layer and the leader line layer is gradually reduced. 5 A reference voltage is applied to both ends of a resistor string made of multiple diffused resistors or a capacitor string made of multiple capacitors made of gate oxide films, etc., and each resistor string or capacitor string is connected via a switch that is turned on and off by a control signal. In a voltage divider designed to output divided voltages, a control signal line layer is formed on each leader line layer for extracting each divided voltage to intersect with these, and the intersection portion of the control signal line layer is gated at each intersection point. Of these MOS structure switches, those that are turned on and off by control signals are E-MOS, and those that remain on regardless of the presence or absence of control signals are D-MOS. A voltage voltage divider characterized in that the surface of the voltage voltage divider including these control signal line layers is covered with an insulating layer, and further a metal layer is formed over the entire surface of the insulating layer.