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JPS6157542U - - Google Patents

Info

Publication number
JPS6157542U
JPS6157542U JP14110384U JP14110384U JPS6157542U JP S6157542 U JPS6157542 U JP S6157542U JP 14110384 U JP14110384 U JP 14110384U JP 14110384 U JP14110384 U JP 14110384U JP S6157542 U JPS6157542 U JP S6157542U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
utility
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14110384U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14110384U priority Critical patent/JPS6157542U/ja
Publication of JPS6157542U publication Critical patent/JPS6157542U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ〜ｅは本考案の一実施例の混成集積回
路装置の製造工程について説明するための斜視図
ａ，ｂ，ｃ断面図ｃ，ｄである。 １…厚膜基板、２…半導体チツプ、３…チツプ
保護用樹脂、４…治具、５…半田バンプ、６…リ
ード端子、７…ケース。 1A to 1E are perspective views a, b, c and sectional views c and d for explaining the manufacturing process of a hybrid integrated circuit device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Thick film substrate, 2... Semiconductor chip, 3... Chip protection resin, 4... Jig, 5... Solder bump, 6... Lead terminal, 7... Case.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板の両面に半導体チツプが搭載されてい
ることを特徴とする混成集積回路装置。 A hybrid integrated circuit device characterized by having semiconductor chips mounted on both sides of an insulating substrate.
JP14110384U 1984-09-18 1984-09-18 Pending JPS6157542U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14110384U JPS6157542U (en) 1984-09-18 1984-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14110384U JPS6157542U (en) 1984-09-18 1984-09-18

Publications (1)

Publication Number Publication Date
JPS6157542U true JPS6157542U (en) 1986-04-17

Family

ID=30699448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14110384U Pending JPS6157542U (en) 1984-09-18 1984-09-18

Country Status (1)

Country Link
JP (1) JPS6157542U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS641269A (en) * 1987-06-24 1989-01-05 Hitachi Ltd Semiconductor device
JPH0320051A (en) * 1989-03-20 1991-01-29 Seiko Epson Corp semiconductor equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS641269A (en) * 1987-06-24 1989-01-05 Hitachi Ltd Semiconductor device
JPH0320051A (en) * 1989-03-20 1991-01-29 Seiko Epson Corp semiconductor equipment

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