JPS6155708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an access control scheme, in particular when reading from multiple vector data memories and setting them in vector registers, in order to reduce the number of accesses, a single request is made to the memory. The present invention relates to an access control system that performs access (hereinafter referred to as para-access) that allows reading a plurality of pieces of data.

When performing vector operations, the vector data required for the vector operations is typically stored in a relatively slow access memory storage unit (MSU). If the arithmetic unit sequentially reads these vector data directly from the MSU and performs calculations, the calculation speed will be slow. Therefore, a vector register that can be accessed at high speed is provided, and a large amount of vector data required for calculation is stored in the vector register.
Read it from MSU in advance and set it.
Vector operations are performed using this set vector data.

FIG. 1 shows an example of a system configuration, where 1 is a central processing unit and 2 is a vector processing unit. Vector processing device 2 executes vector instructions. Based on this vector command, the command control unit 5 sends the logical address LA of vector data a ₀ ,
Vector data a ₀ , a ₁ , a ₂ ...inter-element distance a indicating the interval at which a _o is stored, the number of vector data to be read VL, the vector register number of the vector register 7 to which the read vector data is to be set. , access operation, etc., to the access control unit 6. The access control unit 6 thereby sequentially creates addresses for vector data a ₀ , a ₁ , ...a _o from the logical address LA and the value of the inter-element distance d, and provides the memory control device 3 with the required number of vector data. Make an access request. The memory control unit 3 selects either the central processing unit 1 or the vector processing unit 2 in response to requests from the central processing unit 1 or the vector processing unit 2.
Sends the read request address to MSU4. The vector data a ₀ , a _{1 .} Therefore, in order to read the vector data a ₀ , a _{1 .} . Another drawback is that a large amount of material is required to increase the amount of data transferred.

Therefore, the present invention provides an access control method that reduces the number of accesses by performing para-access when accessing an MSU, and further increases the amount of transfer without increasing the amount of material. To this end, the access control method of the present invention includes a memory in which vector data is stored, a vector register in which vector data read from this memory is set, and a vector register in which vector data is set. In a data processing device equipped with an arithmetic means for performing an arithmetic operation based on the vector data, an address is generated based on the inter-element distance of the vector data and the address of the first element,
A data access control method for accessing vector data, which includes a plurality of address generation means, a plurality of corresponding request means, and a means for detecting that the distance between elements of vector data is less than or equal to a predetermined size. The present invention is characterized in that when it is detected that the distance between data elements is less than or equal to a predetermined size, one set of a plurality of address generation means and request means performs para-access control.

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a schematic diagram of an embodiment of the present invention, FIG. 3 is a detailed diagram of its data system, and FIG. 4 is a detailed diagram of its address generation system.

In the figure, the same reference numerals as in other figures indicate the same parts, 3' is a memory control device, 5 is an instruction control section, 5-1 is an inter-element distance identification section, 5-2 is an instruction transmission control section, and 6' is an access section. 1 is a control unit; 9 is an access pipe A data processing unit; 10 is an access pipe B data processing unit;
1 is an address sending unit, 12 is an address generation control circuit, 13-0 to 13-7 are error check circuits,
14-0~14-7 are error correction units, 15-0~
15-7 is each bus port, 16-0 to 16-3
is an address calculation circuit, 17-0 to 17-3 are logical address registers, 18-0 to 18-3 are distance registers, 19-0 to 19-3 are address conversion circuits, and 20-0 to 20-3 are addresses. It is an output register.

In FIG. 2, the memory control device 3' performs access control to the MSU 4 like the memory control device 3, but based on the control signal from the address generation control circuit 12, the memory control device 3' performs access control to the MSU 4 in addition to normal access control. This makes it possible to perform para-access control. Here, para-access refers to simultaneously accessing a plurality of pieces of data stored at addresses within a certain range from the access destination address in parallel with a single access request. In the illustrated example, access pipes A 0 and B ₀ each consisting of four buses are provided between the access pipe A data processing section 9 and the access pipe B data processing section ₁₀ and the memory control device 3'. , the bus width of each access bus is, for example, 8 bytes. Therefore, in the case of para-access, the data transmitted from these four access buses in response to a single access request is, for example, 32 bytes. At this time, the number of elements is
In the case of an 8-byte instruction that handles data in 8-byte units, if the inter-element distance is 8 bytes, the maximum number of elements that can be transferred is 4 elements, and in the case of a 4-byte instruction that handles data in 4-byte units, the inter-element distance If is 8 bytes, the maximum number of elements that can be transferred is 4 elements, and if the distance between elements is 4 bytes, the maximum number of elements that can be transferred is 8 elements. Similarly, the maximum number of elements is 32. One element of the vector register 7 is, for example, an 8-byte unit, so when it is processed as a 1-byte instruction, "0" is written in the upper 7 bytes, and when it is processed as a 4-byte instruction, the upper 4 bytes or the lower 4 This will write ``0'' into the byte and set it in the vector register. Furthermore, since four buses each having a width of 8 bytes are provided for the vector register 7 from the access pipe A data processing section 9 and the access pipe B data processing section 10, four buses for the vector register 7 are provided at one time. This means that elements can be transmitted.

In this way, if the distance between elements is, for example, 8 bytes or less, it is possible to transmit a plurality of elements in response to one access request, and this is referred to as a para-access as described above. On the other hand, accesses where the distance between elements exceeds 8 bytes, for example, are accesses in element units where one element is transferred in response to one access request because the data stored in the MSU is discrete. do. At this time, the access request to MCU3' is
It is possible to make as many access requests as the number connected by the bus from the MCU 3' and the address generation section (the addresses generated by the address generation section 11 are 4 sets A to D), for example, the access pipe A data processing section 9 This makes it possible to generate access requests commensurate with the amount of data transferred.

As shown in FIG. 4, the address generation section A includes an address calculation circuit 16-0, a logical address register 1
7-0, a distance register 18-0, an address conversion circuit 19-0, and an address output register 20-0. Now, the command control unit 5
, when the logical address LA indicating the vector data to be accessed and the inter-element distance d are applied, these data are respectively stored in the logical address register 1.
7-0 and distance register 18-0. Based on this, address calculation circuit 1
6-0 sequentially performs address calculation, and the result of this calculation is set in the logical address register 17-0. At this time, address calculation circuit 16-0, logical address register 17-0, distance register 1
When sequential address calculation is performed by 8-0, the address generation control circuit sends an access pipe A address generation operation signal to the instruction generation control unit 5-2 to inform that the address generation unit is in operation. Alternatively, the address generation section B is notified by the access pipe B address generation operation signal.

When the operation result is set in the logical address register, the logical address is converted into a physical address by the address conversion circuit 19-0, and the physical address of the MSU that is the access destination obtained in this way is transferred to the address output register 20-0. This physical address will be sent to address bus _A1 . The address generating sections B to D are also constructed in the same manner as the address generating section A described above.

The address generation control circuit 12 is the address sending section 1
1, it generates an access request signal to the memory control device 3' and a bus control signal for controlling the data bus, and also identifies whether or not the access command has an inter-element distance of, for example, 8 bytes or less. An identification circuit 12-0 is provided. And when the distance between elements is less than 8 bytes, 1
In response to an access request, multiple elements read from the MSU 4 are processed by the access pipe A data processing unit or the access pipe B data processing unit. The access pipe A data processing section processes the plurality of elements, and para-access control is performed so that they can be further processed by the access pipe B data processing section.

Also, if the distance between elements exceeds 8 bytes,
Since the data stored in the MSU 4 is discrete, each element is accessed in response to one access request, such as transferring one element. In this case, for example, data processed by the access pipe A data processing section is controlled so that access requests corresponding to a plurality of elements are issued using all address generation sections A to D. The address generation control circuit is
It controls whether an access request is made to the MCU 3' by para-access or element-by-element access.

When a start signal is generated from the command control section 5 during data processing, the inter-element distance of the access command to be transmitted is identified in the command control section 5 by the inter-element distance identification section 5-1. If the para-access is 8 bytes or less, either the access pipe A address generation operation signal indicating whether the address generation section A corresponding to the access pipe A data processing section is free is not operating, or the address generation section B It is checked whether the access pipe B address generation operation signal indicating whether the access pipe B is vacant or not is active, and if both signals are active, the command transmission is suspended by the command transmission control section 5-2. Ru. When it is determined that one of the access pipes is not active, a command is issued to the access pipe that is not active. If the number exceeds 8 bytes, the transmission is performed when both access pipe address generation operation signals are not active.

An activation signal is transmitted from the command transmission control unit 5-2 of the command control unit 5, and at the same time, the start address (logical address) LA of the vector data to be accessed, the inter-element distance d, and the number of elements are sent to the access control unit 6'.
VL, vector register number, access operation, etc. are transmitted. As a result, the distance identification circuit 12-0 of the address generation control circuit 12 identifies whether the distance between the elements is 8 bytes or less. If the number is 8 bytes or less, control is performed by the address generation control circuit 12 so that para-access is performed.

(1) When this para-access is performed, the instruction control unit 5 detects in advance that the distance is 8 bytes or less at the time of transmission by the inter-element distance identification unit 5-1, and then generates an access pipe A address generation operation signal or , access pipe B address generation operation signals are not in operation, or none of them are in operation, and an operation is transmitted to the address generation section of the access pipe that is not in operation. If the transmitted operation is transmitted to access pipe A, address generation section A is used to generate an address, and the operation transfers data using bus _A0 of access pipe A data processing section. will be carried out. At this time, the address generation control circuit 12 notifies the memory control device 3' that the command is being executed using only the address bus _A1 . At this time, address generation section A
Then, based on the start address LA, the distance between elements d, and the number of elements VL, the address calculation circuit 16-0 sequentially calculates the logical address of the access destination, and this logical address is converted into a physical address by the address conversion circuit 19-0. be done. While the logical address of the access destination is being calculated sequentially, the address generation unit A is connected to the access pipe A.
The command transmission control unit 5 indicates that the command is being used by the
-2 is notified by the access pipe A address generation operation signal. The physical addresses sequentially obtained in this way are sent to the address bus _A1 via the address output register 20-0.
At the same time, the access request signal is transmitted to
Communicate RQA and bus control signals to the memory controller. Based on this, the memory control device 3'
Access MSU4 and sequentially read the required vector data. As shown in FIG. 3, the MSU 4 has multiple memory modules 4-0 and 4-1.
. . 4-7, and the stored data is interleaved as indicated by the numbers in the figure, and is stored in each memory module at double word addresses. The vector data read from the MSU 4 is then stored at 13-0, 13-1, . . . 13 in the memory control device 3'.
-7, and if there is a correctable error in the vector data read based on this, the error correction unit 14-0,
Errors are corrected in steps 14-1, . . . , 14-7. and port 15-0, 15-2, 15-
4 and 15-6 by the bus control signal sent together with the access request signal, and is transmitted to the access pipe A data processing unit 9 via the transfer bus _A0 of access pipe A. and set in vector register 7. In this way, 32 bytes of vector data from transfer bus _A0 of access pipe A can be read out in response to one access request. Of course, if address generating section A is not activated but address generating section B is activated, vector data is sent out using transfer bus _B0 of access pipe B as described above. Of course, in this case, execution of the command is transmitted to the memory control device 3' by the address bus _B1 , the request signal RQB, and the bus control signal, and the para access is transmitted from the address bus B1 to the address information transmitted from the address bus _B1 . The memory control device 3' recognizes that the process is executed by the process.

As is clear from the above description, access pipe A and access pipe B can each independently perform para-access for different operations.

(2) However, if the inter-element distance identification unit 5-1 identifies an access operation that exceeds the inter-element distance by 8 bytes, para-access control is not performed, and address generation units A to D are used to
Discrete addresses are generated so that access is performed for each element, such as transferring one element of data in response to one access request. Therefore, the command transmission control unit 5-2 can transmit an access command when both the access pipe A address generation operation signal and the access pipe B address generation operation signal are not in operation. In this case, the address generation control circuit 12 receives four element addresses at once from the address generation sections A to D (first LA, LA+D, LA+2D, LA+3D, then LA+4D, LA+5D, LA+6D, LA+7D). Occur. At this time, address buses A ₁ to D ₁ corresponding to each of the four buses and access request signals RQA to
The address is transmitted by the RQD, and the bus control signal is used to recognize that the data is being executed in the access pipe A, and the data is controlled to be transferred to the access pipe A data processing section at the time the data is transferred. Ru. Data is accessed in correspondence with the four request means RQA to RQD, and data for four elements is processed at one time. However, if the address conflicts with the memory, access will be delayed. In the case of the above-mentioned para-access, it is an access to a continuous area of memory, so there is no chance of conflict with your own access.

As explained above, according to the present invention, para access is performed according to the distance between elements to be accessed, and multiple pieces of data can be accessed simultaneously in parallel in response to a single access request, thereby reducing the number of accesses. data processing efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of conventional vector data access, Fig. 2 is a schematic diagram of an embodiment of the present invention, Fig. 3 is a detailed diagram of the data system, and Fig. 4 is a detailed diagram of address generation. It is. In the figure, 1 is a central processing unit, 2 is a vector processing unit, 3 and 3' are memory control units, 4 is a memory storage unit, 4-0 to 4-7 are memory modules, 5 is an instruction control unit, and 6 , 6' is an access control unit, 7 is a vector register, 8 is an arithmetic execution unit,
9 is an access pipe A data processing section, 10 is an access pipe B data processing section, 11 is an address sending section, 12 is an address generation control circuit, 13-0 to 1
3-7 is an error check circuit, 14-0 to 14-
7 is an error correction unit, and 15-0 to 15-7 are ports, respectively.

Claims (1)

[Claims] 1. In a data processing device equipped with a memory in which vector data is stored, a vector register in which vector data read from this memory is set, and an arithmetic means for performing an operation based on the vector data set in this vector register, A data access control method that generates an address based on the inter-element distance and the address of the first element and accesses vector data, which uses a plurality of address generation means, a plurality of corresponding request means, and an inter-element distance of vector data. is less than a predetermined size, and when it is detected that the distance between elements of vector data is less than a predetermined size, one of the plurality of address generation means and request means is provided. An access control method characterized by performing para-access control using one set.