JPS6153778A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a GaAs FET having a high surge resistance in a semiconductor substrate, by providing a region to be P-N joined with a source region in contact with the source region, and by connecting the region to a gate electrode. CONSTITUTION:An active channel layer 32, a source region 33 and a drain region 34 are selectively formed on a semi-insulating substrate 31, by means of the ion implantation. The regions 33 and 34 are of N<+> type and have a sufficient concentration of impurity to provide an N<+> type layer of a diode in a part of the region 33. A P<+> type region 40 of the diode is formed by the ion implantation. After annealing, ohmic contacting metals 35, 36 and 41 are provided on the regions 33, 34 and 40, while a Schottky contacting gate electrode 37 is provided on the active channel layer 32, and the electrode 37 is connected with the metal 41. In such a manner, the source region is also used as one region of the protective diode, and the parasitic resistace or inductance due the wiring is substantially reduced. Moreover, the required chip area is also reduced substantially.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a field effect transistor, and particularly to a structure of a field effect transistor made of a gallium arsenide all-semiconductor material, in order to ensure drowsiness surge resistance. The present invention relates to a field effect transistor having a protection element.

(Prior Art) Field effect transistors (hereinafter referred to as GaAsFETs) using gallium arsenide as a semi-quartet material have recently been developed.

It has come to be applied not only to microwave band applications, but also to consumer equipment such as television tuners.

In such consumer devices, especially television tuners, the electrical surge resistance of the gate insulating film of the device may become a problem in actual use. q! fiC1GaAs
In the FET Tic, the surge resistance is approximately several ergs, and the surge resistance is generally improved by providing a protection element between the gate and the source. The protection element is of the pn a pnp type.

There are npn type diodes, but the pn type is advantageous in order to not impair the characteristics of the GaAs FET and to obtain sufficient surge resistance.

This protective diode has gold () a A 5
An example of a conventional FET structure is shown in FIG. In the structure shown in FIG. 2, an FET region and a protection diode region are formed separately on a semi-insulating GaAs substrate 11 and connected by electrode wiring. Namely.

An electrode 23 on the p-region 21 of the protection diode and a gate electrode 17 on the channel region 12. The electrode 22 on the n-region 20 of the storage diode and the source electrode 18, which is connected to the source region 13 through an ohmic connection metal 152, are connected to each other by means of metal scrap wiring. The drain region 14 is led out from a drain electrode 19 on the ohmic connection metal 16 in contact therewith.

At such a groove bottom, sufficient surge resistance may not be obtained due to wiring resistance, inductance, etc. of the metal wiring. That is, protection diode kGaAs FET
In order to improve the surge withstand capability, it is necessary to make the reverse breakdown voltage of the protection diode lower than the gate breakdown voltage of VatPET, and to lower the four-way operating resistance Rs. 11. When connecting these two, the parasitic components (resistance, inductance, etc.) associated with the metal wiring must be lowered, otherwise the surge will not be sufficiently absorbed by the protection diode.

1! ' is applied to the gate of ET, and as a result, the FET section is destroyed. Further, if a structure is adopted in which the two are connected by the above-mentioned wiring, the area increases, and there is a drawback that a reduction in the price of the product cannot be achieved.

(Problems to be Solved by the Invention) An object of the present invention is to eliminate the drawbacks of the structure according to the prior art described above, and to provide a low-cost GaAsFET that has sufficient electrical surge resistance. be.

(Means for Solving All Problems) According to the present invention, semi-insulating property 2) A semiconductor substrate has a source region, a drain region, and a gate electrode, and further, a PN junction is formed in contact with the source region. A field effect transistor is obtained in which the region forming the PNw: junction is connected to the gate electrode.

(Function) In the present invention, since the C 1/f source region also serves as one region of the gold protection diode, parasitic resistance and inductance due to wiring are extremely small.

QaA requires less chip area and has excellent surge resistance
sFET'ft can be realized.

(Example) The present invention will be explained in detail below with reference to one drawing.

FIG. 1 shows a pictorial representation of a GaAsFET according to one embodiment of the invention. On the semi-insulating G a As substrate 31 , an active channel layer 32 . ．． Source area 33
The fabricated drain region 34 was selected using gold ion implantation technology (
;<Make a target. In this case, the source region 33 and L
The low drain region 34 is formed with a sufficient impurity concentration so that a portion of the N-type source region 33 becomes the opening layer of the diode. 7) After that, the entire p-region 40 of the diode is formed by ion implantation, and after annealing, gold M35, 36.41 is deposited on the active channel layer 32 to make ohmic connection to the source and drain regions 33, 34 and the p-region 40. Schottky contact M 1-gate polarity 37T
Complete the h formation, and connect the pole 37 to the gate 1 and the metal 41 to the t-contact Il.
i do

Also, the source and drain electrodes 38 and 39 are metal 35°3.
Form on 6. In this way, Ga
AsFET i'j conventional structure GDGaAsFE'l
” can be achieved using almost the same process.

In the structure according to one embodiment of the present invention shown in FIG. 2, the n+ layer of the diode and the source region of the FET are in the same region 33 and are electrically identical. Therefore, the raw resistance, inductance, etc. caused by the electrode wiring connection in the conventional structure can be ignored. For this reason,
By fully optimizing the reverse breakdown voltage and operating resistance of the diode element portion, sufficient electrical surge resistance can be obtained regardless of parasitic components.

Further, according to the present invention, the wiring area between the diode and the FET can be reduced, and the chip area can be suppressed from increasing.

(Effect of the invention) As explained above, according to the structure according to the present invention.

``G
aAsPET can be realized.

In addition, in the examples, a single gate type G a A
Although this is a case of 5FET, the present invention can also be applied to a differential gate type GaAs FET used in a TV tuner.

4 Drawing 1.・Explanation for own vehicle Figure 1 is a cross-sectional view of a GaAs field effect transistor according to Akira Hongen's unsaturated example, and Figure 2 is a conventional GaAs field effect transistor.
FIG. 3 is an i17'r plane view of the field effect transistor.

11.31...Semi-insulating substrate + 18.38
...Source-pole, 19.39...Drain 4-pole, 17°37...Ge htun 4L 12. 32...
... Changyi Lu reconnaissance area, 13.33... Source area, 14.34... Drain area, 40...
...p region, 15,16°35.36...ohmic connection metal, 41...wiring.

Claims (1)

[Claims] In a field effect transistor in which a source region and a drain region are formed in a semi-insulating semiconductor substrate, a region is provided in the semi-insulating semiconductor substrate in contact with the source region to form a PN junction with the source region, and the PN junction is formed. A field effect transistor characterized in that a region to be formed is connected to a gate electrode.