JPS6151940A - Wiring structure of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the electrical connection of parts of through-holes by smoothing the insulation film and thinning the interlayer insulation film, by a method wherein a metallic wiring of the first layer is provided with an oxide film of low temperature vapor growth and a plasma nitride film, which are coated with silica film, and a plasma nitride film is grown again. CONSTITUTION:After formation of the metallic wiring 23 of the first layer, the oxide film 29 of low temperature vapor growth is deposited to approx. 2,000- 4,000Angstrom , and the plasma nitride film 24 is grown thereon to approx. 2,000Angstrom . Then, the silica film 25 is applied, and a plasma nitride film 26 is grown again to approx. 2,000-3,000Angstrom . A metallic wiring 28 of the second layer is deposited. The multilayer wiring thus produced can be reduced in film thickness because an oxide film of low temperature vapor growth with a small dielectric constant lies on the metallic wiring of the first layer. Therefore, the hole depth of the through -hole part does not become deeper so much, and it electrical connection can be easily made.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to the wiring structure of a semiconductor integrated circuit device.
In particular, it relates to multilayer wiring (single construction) of semiconductor integrated circuit devices.

(Prior Art) Conventionally, as the density of semiconductor integrated circuit devices increases, the wiring structure thereof has changed from a single layer wiring to a multilayer wiring.

The problems in forming a multilayer wiring structure are the method of forming the interlayer insulating film between the first layer metal wiring and the second layer metal wiring, and the electrical connection between the first layer metal wiring and the second layer metal wiring. This is a method of forming connection windows and through holes. In other words, if an interlayer insulating film is grown as it is on the step between the part with and without metal wiring in the first layer, this step will be removed when the second layer gold r1 wiring material is formed by vapor deposition or sputtering. A defect occurs in which the second layer metal wiring becomes a dashed line. In addition, a method of forming the first interlayer insulating film was devised to reduce the level difference in the first layer of metal wiring.

FIG. 1 shows the manufacturing process of this improved multilayer wiring formation method for a semiconductor integrated circuit device.

In Fig. 1, there are 11 semiconductor substrates, 12 parts, 7 parts.
Covered with silicon oxide film. Further, 13 is a -J100 metal wiring, and 14 is a first layer silicon nitride film (hereinafter referred to as plasma nitride film) formed by plasma vapor phase chemical reaction.
This is a silica film prepared by dissolving 15I/'i silicon oxide in an organic solvent, and 16 is a plasma nitride film further deposited on this 150 silica film.

Reference numeral 18 indicates a second layer of metal wiring, and 17 indicates a through hole for establishing an electrical connection between the first layer of metal wiring and the second layer of metal wiring.

Multilayer layout #i made in this way! In the structure, as shown by the figure in FIG. 1, a silica film 14 is filled on the plasma nitride film 14 in the area between the first layer metal wiring 13 and the metal wiring. The plasma nitride film 16 is deposited.

Smoothly. Therefore, the second layer of metal wiring 18 above it
will not break at the step.

By the way, as the N-interlayer insulating film, a silicon oxide film grown by a low temperature vapor phase growth method (hereinafter referred to as a low temperature vapor growth oxide film) or a plasma nitride film has conventionally been used. As shown in FIG. 2, this plasma nitride film is completely filled with the first step B, which is one tenth of 1j13. On the contrary, in low temperature vapor phase grown oxide films, the third
As shown in the figure, the metal wiring of the second step C was not sufficiently applied, and even if the price was sold out, the thickness of the saponified film by low-temperature vapor phase growth was insufficient at the end of step &6. Therefore, considering only the memory retention of the first step, the plasma nitride film is preferable.

However, the one-layer insulating film cannot be determined only by the cover state of one step, and the wiring capacitance must also be taken into consideration. When a wiring capacity of 1K is added between metal wirings, the operating speed of the semiconductor integrated circuit device becomes slow.

Therefore, it is necessary to reduce the wiring capacitance as much as possible. The wiring capacitance between the first layer metal wiring and the second layer gold tilted wiring can be calculated assuming that a parallel plate capacitor is formed. That is, the gland answer htC can be expressed as follows.

C=6・S/1...(1) Here, 8: Parallel plate part +t<, ζ: Electricity rate.

1: Distance between electrodes. In this equation (1), either S is made small, t is made small, or 17il is made large.

Among these three methods, the area of S is determined by the level of photoetching technology at the time, so
The area of S cannot be reduced blindly.

Further, the distance y 1 of the electrode +=j becomes jH insulation film thickness on the semiconductor integrated fit circuit, but if the thickness of this layer 1μj insulation film is too thick, it becomes 17 as shown by 17 in FIG. The depth of the hole in the through-hole portion becomes deep, and disconnection at the second step portion occurs due to variations in the manufacturing process, making it difficult to establish an r −1′:L air connection.

In the third method, the dielectric constant E can be reduced by changing the material of the 1w4 insulating film. If: The above-mentioned low-temperature vapor phase growth 1 which is generally used as the material for the inter-i insulating film.
A comparison of the dielectric constant 6 of the plasma nitride film and that of the plasma nitride film is as follows.

Ratio + J 'IW 'J = (I MHz) Plasma nitriding 7.0 Low temperature vapor phase growth saponification 1A 3.7 As will be seen from now on, for a film of the same thickness, the plasma formation will be much lower in temperature. The interconnect capacitance is twice that of a vapor-grown silicide film. Therefore, in order to make the wiring capacitance attached to the plasma magnetized film the same as the wiring capacitance to the low-temperature vapor phase growth saponification ε, the film thickness 1 of the plasma nitriding film must be approximately doubled. At this time.

As mentioned above, it becomes difficult to make electrical connections through the through holes.

As described above, the multilayer wiring method of adding 18 circuits to the semiconductor device shown in FIG.

Chestnut film, plasma shop 1'r'p! Since it has a sandwich structure, will there be a non-event on the insulating film between Jg? i? However, in order to reduce the wiring capacitance, the thickness of the interlayer film was increased, and the 1L contact area of the through hole was reduced by 1.

(Object of the Invention) The object of the present invention is to eliminate two or more drawbacks, to make the top of the interlayer insulating film clear and thin, and to reduce the thickness of the first interlayer insulating film.

This is achieved by providing a multilayer wiring structure that is easy to maintain at temperatures of 100°C for electrical connection of through-hole portions.

(Fourth Part of the Invention) After forming the structure of the multilayer wiring of the present invention, a thin low-temperature vapor phase grown oxide film is grown, and a thin plasma nitride film is formed on it. Let it grow.

A silica film is applied on top of this, and a living room insulating film structure consisting of four layers of plasma nitride film grown is completed.

(Explanation based on examples) Next, two embodiments of the present invention will be implemented and explained using 1j.

FIG. 4 is a sectional view of a multilayer wiring structure according to an embodiment of the present invention. In FIG. 4, 21 is a semiconductor substrate, 22
2 is a silicon oxide film, and 23 is a first layer metal wiring. After forming this first layer of gold h1 key, 29 low temperature vapor phase grown oxide film is applied at 2000 to 4000 on guest o-
24 thin plasma nitride films of about 2000 angstroms are grown on the wafer. Then, apply a silica film of 25 and plasma nitridation of 26 of 2000 to 3000.
Angstrom Chengbo is grown in an outer box. and.

Attach the second layer of metal wiring No. 28.

Since there is a film formed by low-temperature vapor phase growth with a small dielectric constant on top of the multi-lu wiring made in this way, the multi-layer wiring shown in Fig. 1 is formed. Compared to the structure, if the same arrangement is used, the film thickness can be made thinner. Therefore, the depth of the hole in the through-hole portion is not very deep, and the r''111 air connection can be easily established.

(Effects of the Invention) If the present invention described above is also used, the surface of the interlayer insulating film is smooth and the thickness of the interlayer insulating film is small.

Multilayer wiring with low wiring capacitance and good electrical connection at through-hole portions can be obtained. In addition, two things in the present invention.

For the sake of clarity, the explanation was given using a two-layer wiring structure.

The present invention can also be applied to multilayer wiring having three or more layers.

[Brief explanation of drawings]

FIG. 1 is a #Fr plane view showing the structure of an interlayer insulating film in a conventional multilayer wiring structure. Figure 2 shows the state of the interlayer insulating film when a plasma-treated film is deposited as a 1j-interval insulation film on the first layer of metal wiring.
FIG. FIG. 3, dimension 11, is a cross-sectional view showing the state of the interlayer insulating film when a vapor-phase grown oxide film is deposited as the interlayer insulating film on the top of the first layer of metal columns. Figure 4 shows the structure of the present invention. 6 is a cross-sectional view showing the wiring structure when the interlayers are separated. 11... Hemilateral substrate, 21... Semiconductor internal 1, 12... Thermal oxide film, 22... Heat t
? Bakage, 1:3...The first layer of gold books (,23
・・・・・・First layer gold cherry blossom arrangement 21.14・・・・・・
Plasma nitride film, 24... Plasma nitride film, 1
5-- Silica film, 25... Silica film A. Mu, 16... Plasma socialization theory, 26...
...Plasma'FA JR? , 17...
Through hole, 27...Through hole, 18.
...Second layer metal wiring, 28...Second layer metal wiring 6.19...Low temperature micro (phase growth oxide film,
29...Low temperature vapor phase grown oxide film. Agent Patent Attorney Uchihara Formerly 2, \-I = 2 (

Claims (1)

[Claims] In a multilayer metal wiring of a semiconductor device, a first metal wiring for electrical connection between each element of a semiconductor integrated circuit device is provided on an insulating film provided on a semiconductor substrate, and a metal An oxide film grown using low-temperature vapor phase growth is formed on the insulating film without wiring, and then a first layer of silicon nitride film is formed using a plasma vapor phase chemical reaction. 1. A wiring structure for a semiconductor device, characterized in that a film is applied, a silicon nitride film is provided on the film by a second plasma vapor phase chemical reaction, and a second metal wiring is provided on the film.