JPS6148777B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device used in a high-density integrated circuit.

In a large-scale integrated circuit, two layers of wiring perpendicular to one main surface of a semiconductor substrate constitute the necessary wiring for circuit elements formed within the substrate. In conventional integrated circuits, an interlayer insulating film is used to ensure insulation between wiring in different layers that are orthogonal to each other, and when wiring in an upper layer is connected to the substrate surface through an opening, the wiring in the lower layer is connected to the opening. It is necessary to make the interval larger than the margin in the production process. However, this margin is an impediment to increasing the density of integrated circuits, and as the chip size of integrated circuits increases, the operating speed decreases, power consumption increases, and productivity decreases.

An object of the present invention is to provide a semiconductor device having a high-density integrated circuit structure.

A feature of the present invention is that a pair of lower electrode wiring layers are provided on one principal surface of a semiconductor substrate with an interval between them via an insulating film, and the upper surface of the lower electrode wiring layer and the side surface facing the interval are is provided with an insulating layer obtained by altering the surface portion of the lower electrode wiring layer, an interlayer insulating layer is provided on the lower electrode wiring layer, and the interlayer insulating layer has openings larger than the above-mentioned interval. a large aperture provided in the interlayer insulating layer; An upper wiring layer formed between the two insulating layers and filling the opening provided in the insulating film is connected to an impurity region of the semiconductor substrate exposed to the opening provided in the insulating film. Found in semiconductor devices.

FIGS. 1A to 1D are cross-sectional views of main steps in an embodiment of the present invention. That is, in the semiconductor device of this example, one main surface of a P-type silicon substrate 101 is selectively oxidized to form a 1.0 μm thick SiO ₂ film 102, and the Si ₂ N ₄ film used for selective oxidation is selectively etched. to form diffusion masks 103 and 104, and use these diffusion masks to form N-type regions 105 and 105 on one main surface.
106 [FIG. 1A]. Next, the Si ₃ N ₄ film is removed, wiring electrodes 107 and 108 of a first layer of aluminum with a thickness of approximately 1 μm are formed, and the surrounding surfaces of these are anodized and coated with non-porous alumina 109 and 110. Figure 1B]. A mixture of ethylene glycol and ammonium borate was used for this chemical formation, and a 9000Å
Obtain an anodized film. Next, a phosphor glass layer 11 on the surface
1 is vapor-phase grown at 400 DEG C. to 450 DEG C., and a photoresist film 112 is formed on the surface thereof (FIG. 1C). This resist film 112 is provided with an opening pattern 113 extending over the upper surface of the pair of aluminum electrode wirings 107 and 108, and chemical selective etching is performed in a weak hydrofluoric acid solution through this opening. Compared to alumina, the 400 Å SiO ₂ film on the surface of phosphor glass and the substrate has a hydrofluoric acid chemical etching rate of about 30 to 50 times, about 5 times, so selective etching by the hole pattern 113 exposes the surface of the substrate. In addition, the covered state of the electrodes 107 and 108 is maintained. Finally, as shown in FIG. 1D, in this embodiment, a pair of electrode wirings 107 of aluminum which can be anodized are extended parallel to each other on one surface of the silicon substrate 101 via a SiO ₂ film 114 which is a silicon oxide. , 108, there are self-aligned openings insulated from these wirings to provide electrical connection between the upper wiring layer 115 and the surface of the substrate (FIG. 1D).

This embodiment achieves a very high density integrated circuit structure because it does not require any allowance for openings in the substrate between the underlying electrode traces. In addition, tantalum can be used as the metal that can be anodized, and a conductive material made by mixing aluminum or tantalum with other materials such as silicon or copper can also be used.

[Brief explanation of the drawing]

FIGS. 1A to 1D are sectional views showing main steps of an embodiment of the present invention. In the figure, 101...
...Semiconductor substrate, 107, 108... Lower layer wiring electrode that can be anodized, 109, 110... Anodized film, 111... Phosphorous glass layer, 113... Opening pattern spanning the upper surfaces of a pair of wiring electrodes, 114 ……
SiO ₂ film, 115... Upper layer wiring.

Claims (1)

[Claims] 1 A pair of lower electrode wiring layers are provided on one main surface of a semiconductor substrate with a gap between them via an insulating film, and the lower electrode wiring layer is provided on the upper surface of the lower electrode wiring layer and the side surface facing the gap. An insulating layer obtained by altering the surface portion of the layer is provided, an interlayer insulating layer is provided on the lower electrode wiring layer, an opening larger than the interval is provided in the interlayer insulating layer, and the pair of holes is provided. An opening is provided in the insulating film with the same dimensions as that between the two insulating layers provided on each side of the lower electrode wiring layer, and a large opening provided in the interlayer insulating layer is provided between the two insulating layers. An upper wiring layer formed to fill an opening provided in the insulating film is connected to an impurity region of the semiconductor substrate exposed to the opening provided in the insulating film. Semiconductor equipment.