JPS6146614A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit technology, and is a technology that is effective when applied to, for example, a semiconductor integrated circuit device incorporating a chopper type comparison circuit or an A/D conversion circuit using the same. Regarding.

[Background Art] Conventionally, in a circuit such as a successive approximation type A/D converter,
For example, a chopper type comparison circuit as shown in FIG. 1 has been proposed (IEEE Journal of 5
olid-8tate C1rcuits, Vol.
5C-13+ pp. 785-791, December 1978)
.

This chopper type comparator circuit includes a pair of switches S1 . S2 and this switch S1.
It consists of a plurality of AC amplification stages 1a, lb, Ic, and Id connected in series between the common connection point NO of S2 and the output terminal OUT. Each of the amplification stages 1a to 1d is composed of capacitors C1 to C4 and inverters 28 to 2d, respectively.

In addition, - reporter capacitors C1 to C4 and inverter 28
The connection points N1 to N4 with ~2d are connected to switch groups 811 to 811.
In step S14, a bias voltage VB for determining the operating points of the inverters 28 to 2d is supplied.

The switch S1 and the switch groups 811 to S14 are controlled on and off by a control signal φ, and the switch S2 is controlled to be turned on and off by a control signal T having an opposite phase to the control signal φ.

Therefore, for example, when the control signal φ is set to high level and the switch S2 and the switch groups Sll to S14 are turned on,
A bias voltage Vn is supplied to nodes N1 to N4 of each amplifier circuit 1a to 1d.

Further, at this time, since the switch S2 is turned off by the control signal T, the input analog voltage V is applied to the node No.
i n is supplied.

Next, when the control signal φ is changed to a low level, the switch S1 and the switch group Sll to S14 are turned off, and the switch S2 is turned on by the control signal φ. Then, the reference voltage V r e f is supplied to the node No, and the input analog voltage V i n is supplied between the terminals of the capacitor C1.
A differential voltage (Vin-Vref) between the reference voltage Vref and the reference voltage Vref is generated. This differential voltage (Vin-Vref) is amplified by the inverter 2a and supplied to the second amplification stage 1h. In this way, the input analog voltage Vin
The difference voltage between the reference voltage V r e f and the first to fourth
The signals are successively amplified by the AC amplification stages 1a to 1d.

By the way, the chopper-type comparator circuit described above is constructed of elements of the same size as the inverters 2a to 2d constituting each of the amplification stages 1a to 1d, and the logical threshold voltage is determined by feeding back the output voltage to the input terminal. The bias circuit 3 was constituted by an inverter 3a that generates a bias voltage Vs equal to .

Therefore, such a chopper type comparison circuit can be integrated into an LSI (LSI) such as a microcomputer with a built-in A/D conversion circuit.
When used as a comparator in a large-scale integrated circuit (large-scale integrated circuit), a through current will always flow through the inverter 3a constituting the bias circuit 3 even when the A/D conversion circuit is not operated.

In addition, when the A/D conversion circuit is not operated, switch group 8
Even if the amplifier stages 11 to S14 are turned off, the amplifier stages 1a to
Since the potential of each of the connection points N1 to N4 of the inverter 1d becomes unstable due to the charge charged in the capacitance parasitic thereto, there is a possibility that a through current may flow through each of the inverters 28 to 2d.

Therefore, in order to reduce the power consumption of the entire LST,
The LSI with a built-in D conversion circuit is a CMO3 (complementary MO8)
), a non-negligible through-current flows through the chopper comparison circuit when the A/D conversion circuit is not used, resulting in a problem of extremely wasteful power consumption.

[Object of the invention] The object of the invention is to provide an A/D using a chopper type comparison circuit.
A to reduce power consumption in LSI with built-in conversion circuit.
An object of the present invention is to provide a semiconductor integrated circuit technology that can be realized without deteriorating the characteristics of a /D conversion circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, between the input terminal of the inverter that generates the bias voltage at the connection point of each AC amplifier stage constituting the chopper comparison circuit and one power supply voltage terminal of the circuit, and from the output terminal of the inverter constituting the bias circuit to the input terminal. By providing switch means in each of the feedback paths through which the A/D conversion circuit is inactive, the switch means on the input terminal side of the bias circuit is made conductive, and the switch means in the feedback path is cut off. The output voltage of the inverter is fixed at high or low level to cut through current, and all the switches provided to supply bias voltage to the connection points of each amplification stage are made conductive to reduce the potential at each connection point. The purpose of the second objective is to fix the voltage so that no through current flows to the inverter that makes up the amplifier stage, thereby powering down the R-SR that has a built-in A/D conversion circuit and has a chopper type comparison circuit. It is something to be achieved.

The present invention will be described in detail below along with examples.

[Embodiment] FIG. 2 shows an embodiment of the present invention, and the chopper type comparison circuit of this embodiment has the following features except for the configuration of the bias circuit.
It has substantially the same configuration as the circuit shown in FIG.

That is, the input terminal ■N1. ■A pair of sampling switches S1 connected to N2. S2 common connection point NO.
Although not particularly limited, four AC amplification stages 1a to 1d each including capacitors 01 to C, 1 and inverters 2a to 2d are connected between the output terminal OUT and the output terminal OUT. And, at each connection point N1 to N4 of the amplification stages 1a to 1d,
Bias voltage VB output from bias circuit 3 can be supplied via switch groups 811 to 814. Further, although not particularly limited, each inverter 2 a - configuring the amplification stages 1 a to 1 d and the bias circuit 3
2d and 3a are composed of CMOS inverters.

Further, in this embodiment, the input terminal of the inverter 3a constituting the bias circuit 3 is connected to a connection point of the circuit via a switch S3.

In addition, the output voltage of the inverter 3a (bias voltage V B
) is fed back to the input terminal, and a second switch S4 is provided in the middle of the path.

Therefore, the bias circuit 3 of this embodiment becomes exactly the same circuit as the circuit shown in FIG. 1 by turning on the switch S4 provided therein and turning off the switch S3. In other words, the inverter 3a constituting the bias circuit 3 is activated and its output voltage is applied to the input terminal, so an output voltage equal to the logic threshold voltage is generated, which is the bias voltage. It is supplied as VB to each connection point N1 to N4 of the amplification stages 18 to 1d via switch groups 811 to 814, and determines the operating point thereof.

However, the bias voltage VB that determines the operating point is such that the inverter 3a of the bias circuit 3 is composed of elements having the same size as the inverters 28 to 2d forming each of the amplification stages 1a to 1d. Therefore, each inverter 28 to 2d
is now operated near its logical threshold voltage, resulting in excellent responsiveness and a large amplification factor.

On the other hand, when it is not necessary to operate the A/D conversion circuit including the chopper type comparison circuit, the switch group 811
The control signal φ for turning on and off S14 is fixed at a high level (therefore, the control signal T is at a low level) as shown in FIG. In addition, each switch S in the bias circuit 3
3. The power down signal PWD that controls S4 is changed to a high level to turn off switch S4 and turn on switch S3 instead.

Then, the ground potential is applied to the input terminal of the inverter 3a, and since no feedback is applied, the output voltage of the inverter 3a is fixed at a high level (Vcc). This prevents a through current in the inverter 3a made of a CMOS inverter. In addition, switch group 8
11 to S14 are turned on by the fixed control signal φ as described above, so the high level output voltage of the inverter 3a is supplied to each connection node N1 to N4 of the amplification stages 1a to 1d. As a result, amplification stages 18 to 1d
The input voltages of the inverters 28 to 2d constituting the circuit are fixed at a high level, so that no through current flows.

Moreover, in the above embodiment, the bias circuit 3 has a switch 5.
3tS4 is provided, and AC amplification stages 1a to 1a during non-operation are provided.
Since the potential of each connection node N1 to N4 of 1d is fixed, there is no risk of deterioration of circuit characteristics. In other words, in order to fix the potential of each connection node N1 to N4 of AC amplifier stages 1a to 1d, it is also possible to provide a switch between each connection node and the ground point or power supply voltage terminal and turn it on when not in operation. Conceivable. However, if this is done, the parasitic capacitance of each connection node will increase, and there is a risk that the A/D conversion accuracy will decrease; however, according to the above embodiment,
There is no risk of such deterioration of characteristics.

In the above embodiment, since the ground potential is applied to the input terminal of the inverter 3a constituting the bias circuit 3 when the circuit is not in operation, the switch S3 can be configured with an N-channel MOSFET. . On the other hand, the switch s4 transmits a potential intermediate between the power supply voltage Vcc and the ground potential, so in order to prevent a voltage drop, it is preferable to use a CuO2)-transmission gate as shown in FIG. P channel type M
An O8FET may also be used. Sampling switch S
1. S2 is constituted by a CMOS transmission gate, and switch groups 811 to S, 4 are each constituted by an N-channel type MO8FET.

Further, in the above embodiment, a ground potential is applied to the input terminal of the inverter 3a constituting the bias circuit 3, and the potentials at the connection points N1 to N4 of the amplifier stages 1a to 1d are fixed at a high level when the amplifier stages 1a to 1d are not in operation. However, the power supply voltage Vcc may be applied to the input terminal of the inverter 3a to fix the connection points N, to N4 at a low level during non-operation.

Even in this case, the characteristics of the CMOS inverter prevent a through current from flowing through the inverters 3a and 2a to 2d. However, in this case, it is preferable to configure the switch S3 with a P-channel type MO8FET so that the power supply voltage Vcc can be applied to the input terminal of the inverter 3a without dropping it.

[Effect] Between the input terminal of the inverter that generates the bias voltage at the connection point of each AC amplifier stage that makes up the chopper comparison circuit and one power supply voltage terminal of the circuit, and from the output terminal of the inverter that makes up the bias circuit. Since switch means are provided in each feedback path to the terminal, when the A/D conversion circuit is not operating, the switch means on the input terminal side of the bias circuit is made conductive, and the switch means on the feedback path is cut off. , the output voltage of the inverter of the bias circuit is fixed at a high level or low level to cut through current, and all the switches provided to supply the bias voltage to the connection points of each amplification stage are rendered conductive. This fixes the potential at each connection point and prevents any through current from flowing into the inverter that makes up the amplification stage, thereby powering down an LSI that has a built-in A/D conversion circuit with a chopper comparison circuit. It has the effect of being able to 112= Moreover, since the bias circuit is provided with a switch means to fix the potential at each connection point of the AC amplifier stage during non-operation, there is no possibility that the characteristics will be deteriorated by the parasitic capacitance of the switch.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the configuration of an AC amplifier circuit that operates in response to a bias voltage from a bias circuit is not limited to the embodiment shown in FIG. In order to cancel the noise coming into N1 to N4, a circuit in which an MO8 capacitor is connected at each connection point, and a signal φ having the opposite phase to the control signal φ is applied to the gate. , various modifications are possible.

[Field of Application] In the above description, the invention made by the present inventor will mainly be described as a CMO8 incorporating a successive approximation type A/D conversion circuit using a Chotsuba type comparison circuit, which is the field of application that formed the background of the invention.
- Although the explanation has been made regarding the application to LS I, it is not limited thereto, and the LSI having a chopper type comparison circuit has been described.
ST can be used generally.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional chopper-type comparison circuit, FIG. 2 is a circuit diagram showing an embodiment of a chopper-type comparison circuit according to the present invention, and FIG. 3 is a control signal in the circuit. Timing Charts 1 to 4 showing the timings of FIG. 4 are configuration diagrams showing an example of switches used in the circuit.

Claims (1)

[Claims] 1. Consisting of a pair of sampling switches and an AC amplifier circuit connected in series between a common connection point of the switches and an output terminal, the control signal is supplied to the control terminal of the switch. The analog signal is alternately sampled by the AC amplifier circuit, and the difference voltage is amplified by the AC amplifier circuit, and a bias circuit that applies a bias voltage to the AC amplifier circuit is connected to an inverter circuit constituting the AC amplifier circuit. A semiconductor integrated circuit device having a chopper type comparison circuit having the same inverter circuit and configured such that its output voltage is fed back to an input terminal, the input terminal and circuit of the inverter circuit constituting the bias circuit. A semiconductor integrated circuit device characterized in that a switch means is provided between one power supply voltage terminal and in the middle of a feedback path. 2. The semiconductor integrated circuit device according to claim 1, wherein each inverter is a CMOS inverter. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the switch means provided in the middle of the feedback path in the bias circuit is a CMOS transmission gate.