JPS6145423B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data transmission system for an information transmission network between control devices scattered over a wide area.

[Background of the invention]

Recently, with the rapid development of microcomputers, so-called distributed control is progressing, in which a large number of microcomputers are installed in a distributed manner as various control devices in industrial fields such as steel and chemical plants. In order to transmit information between these many microcomputers or to a higher-level control computer that monitors and supervises the entire control device, a data highway, for example, a single coaxial line connected in a loop is used. In this way, when a single transmission line is shared to transmit information between each other, information transmission may become impossible due to a disconnection of the line at one point, a failure of a relay station, etc., and reliability may not be sufficient. do not have. As a method of improving the reliability of this information transmission, a method of configuring transmission lines in the form of a network as shown in FIG. 1 is used. ST ^k (however, k=1, 2, 3,
4, 5) are stations that perform data exchange, route control, etc., MC ^m (however, m = 1, 2, 3, 4,
5, 6, 7) are microcomputers scattered throughout the factory as control devices, l _1j (however, i=1,
2, 4, j=1, 3, 4, 5) are transmission lines. For example, even if transmission line _l13 is disconnected, MC1 and MC
It is possible to take a detour between ST1 to _l11 to ST2 _{to l23} to ST3 for transmission. ARPA (Advanced) is a computer network that has such a network of information transmission lines.
Research Projects Agnbcy) network is famous. (e.g. REKahn:Resource
sharing computer communications networks:
Procof IE ³ , Vol, 60, No.11, NOV.1972 pp1397
(Refer to ~1407) This type of network (hereinafter a network of information transmission lines is referred to as a network) uses a store-and-forward method because real-time performance is not required, or speed conversion and code conversion are required at each station. . In the store-and-forward system, the station is composed of a computer, and the data that arrives at the station is once taken into a storage device, subjected to the various conversions described above, and then sent to the next station.

By passing through a large number of stations with such accumulation, a transmission delay corresponding to the data length occurs at each station, resulting in a disadvantage that the time required for information transmission is long.

[Purpose of the invention]

An object of the present invention is to provide a data transmission system for an information transmission network that reduces delay time associated with data exchange.

[Summary of the invention]

A feature of the present invention is that fields constituting a unit of data transmission are provided with fields for the destination address and the number of data to be transferred indicating the data length, and when the station device receives these fields, it can immediately send information to the destination station. The purpose is to determine the address and start the transmission operation.

Another feature of the present invention is that all the data received while performing the transmission operation is stored in the storage device of its own station device, so that it can be retransmitted if the destination station is unable to receive the data normally. be.

One feature of the present invention is that after determining the destination station address and data length and initiating transmission, a direct memory access device (hereinafter referred to as DMA)
Direct Memory Access (abbreviated as "Direct Memory Access") enables high-speed transfer without using a processor.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a specific embodiment of the station device according to the present invention. The figure specifically illustrates the station 3 of FIG. 1 as an example. In order to construct the station apparatus at low cost, a microprocessor 10 is provided in order to configure the processing center with a microprocessor. 20 is a DMA control device which connects the HDLC transmission control device 40 (actually 40-1,
40-2, 40-3) and the storage device 30 at high speed. this
The DMA control device 20 can already be used as a peripheral LSI (Large Scale Integrated Circuit) for microcomputers. The storage device 30 is a storage device for storing programs and data. HDLC transmission control device 40
is a high-level transmission control procedure (HDLC procedure), which is an internationally standardized transmission control procedure.
High-Level Data Link Control (hereinafter abbreviated) is a peripheral for microcomputers.
It is already available as an LSI (large scale integrated circuit). 50 (actually, 50-1, 50-2, 50
-3) is a signal transmission device, and for long-distance transmission it is a MODEM (modulator/demodulator), and for short-distance transmission it is a simple integrated circuit T/R.
(abbreviation of Transmitter/Receiver) etc. are used. It goes without saying that a signal transmission device is not required when the microcomputer and the station device (in the case of MC4 in the figure) are placed close to each other.

FIG. 3 shows the transmission format used in the present invention based on the HDLC procedure. However, it will be clear from the following description that the transmission format realized by the present invention is not limited to that based on the HDLC procedure, but can be realized using any other procedure. The frames specified in the HDLC procedure are shown in the figure, including a frame start flag F, a station address field A, a control field C, and a frame check sequence.
The fields FCS, frame end flag F, destination MC address DA, transfer byte counter BC, and destination address SA are provided to realize the present invention. The flag F in the illustrated pattern (01111110) constitutes a frame, which is a unit of transmission.

The station address field A is the address of an adjacent transmission destination station, and the control field C is a field for issuing an operation command to the station indicated by the station address field A or for sending a response back. The frame check sequence FCS is a field for detecting transmission errors on the transmission path. HDLC
The procedure executes transmission control using these fields: station address field A, control field C, and frame check sequence FCS. Destination MC address DA is the destination MC address of the transmission frame, source MC address SA
is for informing the destination MC mentioned above which MC is the source. Transfer byte counter BC is station address field A
This indicates the number of bytes transferred between the DATA fields (1 byte is 8 bits, and a frame is generally composed of an integral multiple of bytes). A,
Although the C, DA, BC, and SA fields can be expanded in units of 8 bits, they will be explained here as 8 bits. The FCS field consists of 16 bits.

FIGS. 4 and 5 show processing flowcharts of the transmission and reception functions of the HDLC transmission control device 40 in FIG. 2. The operation of the HDLC transmission control device will be described below with reference to the frame structure shown in FIG.

The transmission operation is started when the processor 10 writes a start command to the HDLC transmission control device 40. When transmission is activated, a flag is sent (401), and then a data transfer request is made to the DMA control device 20 in order to send data (402). The starting address of the storage device 30 where transmission data is stored and the number of data to be transferred must be set in advance in the DMA control device 20. DMA control device 20
When the HDLC transmission control device 40 issues a transfer request, it requests the processor 10 to use the processor bus 60. When a request to use the processor bus is issued, the processor 10 immediately suspends use of the processor bus 60, and the DMA control device 20 is notified that the processor bus 60 can be used. As a result, the DMA control device 20 sends out the address of the storage device 30 where the transmission data is stored,
Data transfer is enabled between the storage device 30 and the HDLC transmission control device 40. This direct memory access method, which directly transfers data between input/output devices and storage devices, is commonly used in microcomputers,
Alternatively, it is commonly executed in electronic computers, and is not directly related to the present invention, so a detailed explanation will be omitted. In the processing flows shown in FIGS. 4 and 5, data from the station address field A to the DATA field in the frame structure shown in FIG. 3 is regarded as transmission data, and is stored in the storage device 30.

Before sending data to the line, the HDLC transmission control device 40 determines whether there is an ABORT sending request from the processor (403).
Processor 10 can invalidate the frame it is currently sending. From processor 10
If there is an ABORT transmission request, the HDLC transmission control device 40 transmits an ABORT pattern consisting of eight or more consecutive "1"s to the line (409).

If there is no ABORT transmission request from the processor, the data is sent to the line (404), it is determined whether it is the final data (405), and if it is the final data, a frame check sequence FCS is sent to the line (406); Subsequently, the flag F is sent (407), and the completion of frame sending is notified to the processor 10 by an interrupt signal, thereby ending the series of operations (408). Therefore, the processor 10 is involved in the transmission operation at the time of transmission activation, ABORT transmission, and completion of frame transmission.

The receiving operation is started every time one bit is received from the transmission line, as shown in the processing flow of FIG.
If an ABORT pattern is detected (420), the processor 10 is notified of ABORT reception (427), and the processor 10 invalidates the data received so far. If ABORT is not detected, determine whether flag F is detected (421),
If a flag is detected, the flag F detected flip-flop determines whether it is a frame start or end flag (422), and if it is a frame start flag, the flag detected flip-flop is set (423), and the flag is received by the processor 10. (424) to notify the processor 10 that frame reception has started. If the detected flip-flop flag is set, the frame end flag is set, error detection is performed, and the result is set in the status register read by the processor 10 (425), and the processor 10 is notified of completion of frame reception. (426)

If the flag is not detected, it is determined whether the flag-detected flip-flop is set (428), and if the flip-flop is set, the received bit is shifted into the shift register (429), and the 8-bit reception is completed (428). 430), requests data transfer to the DMA control device 20 (431). Therefore, the processor 10 is involved in receiving operations upon completion of ABORT reception, flag reception, and frame reception.

6A and 6B are flowcharts of reception processing in the data exchange function executed by the processor 10, and ◯◯ in Fig. A follows ◯◯ in Fig. 6. FIG. 7 is a transmission processing flow. Figure 7 shows station 3 shown in Figure 2.
This figure shows the temporal relationship of the transmitted frames. FIG. 8 shows how data from station ST1 is exchanged to station ST2 via ST3.

The frame sent from station ST1 is
The flag is received by the HDLC transmission control device 40-2, and at time _t1 in FIG. 8, the flag detection is communicated to the processor 10 in step 424 in FIG. Processor 1
0 sets a delay timer in step 101 and resumes operation after a certain time. In addition, as mentioned above, until the transfer byte counter BC is received, the DMA
This is because the number of data to be transferred cannot be set in the control device 20. Therefore, the time set to the delay timer is set to a time slightly larger than (t ₂ -t ₁ ).

When the processing of the processor 10 is started after a certain time, it is determined whether the station address field A is the self address (103), and if it is not the self address, the reception operation is stopped and the reception buffer in the storage device 30 is reset (102). ). If it matches the own address, it is determined by control field C whether it is a response frame (104), and if it is a response frame, reception of the frame has not yet been completed, so it waits for notification of completion of frame reception. If it is not a response frame, the destination station address is determined from the routing table based on the destination MC address DA (105). The routing table is set in advance in each station to determine which station should be sent for each destination MC address. Next, the processor 10 determines whether the line to the transmission destination station is in use (106), and if it is in use, it registers it in the transmission request queue (110), and if the line becomes free, it is immediately sent. If the line is not in use, the DMA control device 2
(107). Next, in order to monitor the response to the transmitted frame, a response monitoring timer is set (108) and transmission is activated (109). When transmission is activated, the HDLC transmission control device 40 starts transmitting data at time _t3 according to the processing flow shown in FIG. When the reception of the frame is completed at time _t4 , the processor 10 is notified (step 42 in FIG. 5).
6), the processor reads the status register in the HDLC transmission control device 40 (111) and determines whether there is an error in the received frame (112). If there is an error in the received frame, if the received frame is being transmitted (113), the sender will immediately notify the destination station of the invalidity of the frame.
The HDLC transmission control device 40 is requested to send ABORT, and the ABORT pattern is immediately sent at time _t5 , as shown in step 409 in FIG.
The ABORT pattern is not shown in FIG. If this received frame is not being transmitted, the received frame is reset in the receiving buffer in the storage device 30 (117). If there is no error in the received frame, it is determined whether the received frame is a response frame (115), and then it is determined whether the response frame from the other station is a normal reception or an abnormal reception response (116). In the case of a normal reception response, it indicates that the sent frame was correctly received by the destination station, and the frame reception buffer held in the storage device 30 is reset (117). If the response frame is not a normal reception response, a retransmission request is registered for retransmission (118). If it is not a response frame, a response transmission is requested to notify the other station that the frame has been successfully received and acknowledged (119).

The transmission processing flow in Figure 7 shows that the frame has been sent,
Started by response monitoring timer. When the sending of one frame is completed, the presence or absence of a registered transmission queue is checked in step 110 (120), and the presence or absence of a registered response sending request is checked in step 119 (121), and if there is a request, it is checked. DMA for
Indicates the start address where the data waiting for response or transmission is stored in the control device 20, and the number of bytes to be transferred.
The HDLC transmission control device 40 is set (123). At time _t5 in FIG. 8, a response frame is sent from station 3 to station 1. Since there is no data to be transmitted, the response frame consists only of a station address field A, a control field C, and a frame check sequence FCS. Continuing to set the response monitoring timer (124),
Transmission activation (125) is performed. If there is a retransmission request (129), the counter for the number of retransmissions is incremented (126), and if the retransmission is repeated a certain number of times or more (127), it is assumed that there is an abnormality in the other station or the transmission line, and abnormal processing is performed. Do (128). If the retransmission counter does not exceed a certain value, the start address of the reception buffer that holds the data to be retransmitted,
The number of bytes to be transferred is set in the DMA control device 20 (123) and transmission is started.

As shown in Figure 8, the reception of the frame from station ST3 to station ST2 is completed at time _t6 , and the response frame from ST3 to ST2 is delayed by the processing time of the processor at time _t7 if the line is not in use. In ST3, reception of the response frame is completed at time _t8 , and the reception buffer holding the data is cleared. Therefore ST3
The receive buffer of is occupied from time t ₁ to t ₈ . In addition, if the line to be transmitted is not in use, there will be a delay within the station for the time (t ₃ − t ₁ ), compared to the case where transmission is started after reception is completed after one frame. The delay time was reduced. Set the frame length to 256 for example
If it is on the order of bytes, the delay time at the station will be (5 bytes + processor processing time), and the delay within the station will be about 1/50 of the case where one frame is completely received and then sent.

Furthermore, since data is held in the reception buffer until a response frame is received from the other station, highly reliable data transmission is possible without losing frames within the network.

〔Effect of the invention〕

In this way, according to the present invention, even if the reception of the entire frame is not completed, the frame can be sent to the destination station immediately upon receiving the destination MC address A and the number of transfer bytes, reducing the transmission delay time within the station. can be made sufficiently small. Furthermore, the processor executes functions such as determining the destination MC address and starting and stopping the HDLC transmission control device, and allows high-speed data transfer by having the DMA device transfer data between the HDLC transmission control device and the storage device. The transmission speed of the transmission line can be increased. Furthermore, since the station shown in the embodiment can be realized entirely using a microcomputer and its peripheral LSI, it can be constructed at low cost, and has great industrial effects in this area.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a mesh information system, Fig. 2 is an example of the basic configuration of the present invention, Fig. 3 is a data format diagram, Figs. 4, 5, and 6 A, B, FIG. 7 is a flowchart diagram for explaining the operation of the present invention;
FIG. 8 is a time chart for explaining the operation of the present invention. ST1, ST2, ST3, ST4, ST5...Station, MC1, MC2, MC3, MC4, MC5,
MC6, MC7...Microcomputer, _l11 ,
_l13 , _l14 , _l23 , _l24 , _l25 , _l45 ...transmission line, 10...microprocessor, 20...DMA control device, 30
...Storage device, 40...HDLC transmission control device, 50...
Signal transmission equipment.

Claims (1)

[Claims] 1.Equipped with an information transmission network forming a network and a station provided at each connection point of the information transmission network, each station has a transmission control device that controls transmission with the information transmission network, and stores various information. A storage device, a direct memory access device that transfers data between the transmission control device and the storage device, and a processor that controls the operation of these devices and executes predetermined processing. A destination address and data for displaying the number of transferred data are provided in the transmission frame to be used, and the station determines the destination address when receiving the data of the transmission frame and directs the transmission frame being received to the corresponding station. The data being received while performing this transmission operation is stored in its own storage device, and is stored in the storage device when the destination station cannot receive the data normally and a retransmission request is made. A data transmission method for an information transmission network that sends data to a destination station.