JPS6141217A - Delay circuit - Google Patents

Abstract

PURPOSE:To decrease the number of component parts and to improve the rise or fall performance of a delay circuit by feeding positively a signal produced from the output signal of an FET back to the gate of the FET. CONSTITUTION:The drain potential of an FET1 is set approximately at 0V in an application mode of power supply. Therefore a Tr5 is kept OFF with the FET1 kept ON respectively. A capacitor 2 is charged continuously after application of the power supply. Then the Tr5 is turned ON when the drain potential of the FET1 gives the breakdown to a Zener diode 4. Thus the gate potential of the FET1 is also reduced. As a result, an electric field is applied to the FET1 to increase the internal impedance. Then the drain impedance of the FET1 rises up further. Thus the base current of the Tr5 flowing through the diode 4 is increased more. The Tr5 is turned ON suddenly owing to such a reproducing action. While the FET1 is suddenly turned OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for obtaining a desired output after a desired time has elapsed after a switch is turned on.

In general, in control equipment, etc., after the power is turned on, the operation of the first stage of the internal circuit is stabilized, and then the first stage circuit is connected to the subsequent circuit, and after confirming that the signal from other equipment is reliable, the main unit Delay times ranging from several seconds to several minutes are required for inputs to the circuit, delays in operation to determine the timing with other circuits even within the same device, and switches to emergency power after a desired time has elapsed after a power outage is detected. Many timers are in use.

The present invention was made in order to meet the above demand,
The present invention aims to provide a delay circuit that requires a small number of parts and has good output rise or fall.

Hereinafter, the configuration of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the delay circuit of the present invention.

In the surroundings, (1) is an N-channel junction FET, the source of this FET is grounded via a capacitor (2), and the drain of this FET is grounded via a resistor (3) and a Zener diode. (4) to the base of the transistor (5). The collector of this transistor (5) and the gate of the FET (1) are connected via a diode (6). In this circuit, the output is taken out from the collector of the transistor (5) to light up the LED (7).

Next, the operation of the embodiment shown in FIG. 1 will be explained.

In the circuit shown in Figure 1, when the power is turned on, the capacitor (2) is not charged and the source potential of the FET (1) is OV.
It is. Therefore, since the drain potential of the FET (1) is also approximately OV, no current flows to the base of the transistor (5), and this transistor (5) is turned off. Therefore, since the supply voltage V is applied to the gate of the FET (1), the gate potential of the FET (1) is higher than the source potential, and the FET (1) is in the ON state. After the power is turned on, the capacitor (2) continues to be charged through the resistor (3), and the source and drain potentials of the FET (1) rise.
The drain potential of the FET (1) is a Zener diode (
4), a current flows to the base of the transistor (5), and the transistor (5) begins to shift to the ON state, and the collector potential of the transistor (5) drops, and the gate potential of the FET (1) decreases. also descends. Therefore, the F
An electric field is applied to the ET (1), increasing the internal impedance of the FET (1), and the drain potential of the FET (1) further increases, so that the base current of the transistor (5) flowing through the Zener diode (4) further increases. To increase. Due to this regeneration effect, the transistor (5
) suddenly turns ON, and FET (1) suddenly turns OFF.

In Figure 2, transistor (5) is used to obtain a large load current.
The collector current of the transistor (8) is used as the base current of the transistor (8), and an output is obtained from the collector of the transistor (8).

In the embodiments of FIGS. 1 and 2 above, in order to lengthen the delay time without increasing the capacitance of the capacitor (2), it is necessary to increase the value of the resistor (3). 5) It is not possible to flow a sufficient amount of current to the base. Figure 3 shows FET (
The change in the drain potential of 1) is converted into a current change via the high input impedance element (9), and after a delay, the transistor (5)
This is an embodiment in which a sufficient amount of current can flow to the base of the circuit. In the embodiment shown in FIG. 3, a FET having a polarity different from that of the FET (1) is used as the high input impedance element (9), and when the drain potential of the FET (1) increases, the high input impedance element, that is, the FET (9) is used.
) increases, the internal impedance of the FET (9) increases and the source potential of the FET (9) increases, causing the Zener diode (4) to surrender. The above FET (
The value of the resistor (10) connected to the source of the resistor (3) is
), it is possible to supply a sufficient current to the base of the transistor (5).

As described above, the delay circuit of the present invention requires only a small number of components and has good output rise or fall.

[Brief explanation of the drawing]

1 to 3 show embodiments of the delay circuit of the present invention.

Claims (1)

[Claims] 1) One end of the channel of the FET is grounded via a resistor, and the other end of the channel of the FET is grounded via a capacitor, and after power is supplied, the potential at one end of the channel of the FET is a predetermined potential. When the feedback current from one end of the channel of the FET operates the transistor, the collector of the transistor is electrically coupled to the gate of the FET, and the FET is turned off or the transistor is turned on. A delay circuit characterized in that an output signal is obtained from a point where the potential changes in synchronization with.