JPS6141156B2 - - Google Patents
Info
- Publication number
- JPS6141156B2 JPS6141156B2 JP54138067A JP13806779A JPS6141156B2 JP S6141156 B2 JPS6141156 B2 JP S6141156B2 JP 54138067 A JP54138067 A JP 54138067A JP 13806779 A JP13806779 A JP 13806779A JP S6141156 B2 JPS6141156 B2 JP S6141156B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film semiconductor
- type
- semiconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 claims description 52
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 13
- 239000010408 film Substances 0.000 description 7
- CMSGUKVDXXTJDQ-UHFFFAOYSA-N 4-(2-naphthalen-1-ylethylamino)-4-oxobutanoic acid Chemical compound C1=CC=C2C(CCNC(=O)CCC(=O)O)=CC=CC2=C1 CMSGUKVDXXTJDQ-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/20—Electrodes
- H10F77/206—Electrodes for devices having potential barriers
- H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】
本発明は、薄膜太陽電池のメタル配線の方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of metal wiring for thin film solar cells.
従来の太陽電池は、シリコン単結晶にPN接合
を形成したものが用いられてきた。近年、応用面
においても時計、電卓、ラジオなど多くの方向に
用られるようになるにいたつて、低コスト、低温
プロセス、大面積のものが可能な薄膜太陽電池が
注目を集めている。 Conventional solar cells have been made using single crystal silicon with a PN junction formed thereon. In recent years, thin-film solar cells, which are low-cost, can be processed at low temperatures, and can be produced over a large area, have been attracting attention as they have come to be used in many applications such as watches, calculators, and radios.
薄膜太陽電池の一例として第1図にその断面図
を示す。ガラス基板1にネサ電極2を形成し、前
記ガラス基板1及びネサ電極2の上にN型の薄膜
半導体3を重ねて形成し、さらに前記N型の薄膜
半導体3の上にP型の薄膜半導体4を重ねて形成
することによりPN接合を形成する。前記N型及
びP型の薄膜半導体を所定のパターンに形成した
のち、全面に絶縁膜5を形成し、前記電極2及び
P型半導体4上にメタル配線とのコンタクトをと
るため穴を開けたのち配線6をして第1図の構造
となる。 FIG. 1 shows a cross-sectional view of an example of a thin-film solar cell. A NESA electrode 2 is formed on a glass substrate 1, an N-type thin film semiconductor 3 is stacked on the glass substrate 1 and the NESA electrode 2, and a P-type thin film semiconductor is further formed on the N-type thin film semiconductor 3. A PN junction is formed by stacking 4. After forming the N-type and P-type thin film semiconductors in a predetermined pattern, an insulating film 5 is formed on the entire surface, and a hole is made on the electrode 2 and the P-type semiconductor 4 to make contact with the metal wiring. After wiring 6, the structure shown in FIG. 1 is obtained.
P型及びN型の薄膜半導体の間に不純物をドー
プしないI型半導体をはさんだPIN型構造のもの
があるが、以後ここでは説明を簡単にするため
PN構造でPIN型構造をも含ませるものとする。 There is a PIN-type structure in which an I-type semiconductor that is not doped with impurities is sandwiched between P-type and N-type thin film semiconductors, but for the sake of simplifying the explanation hereafter, I will not use it here.
The PN structure also includes a PIN type structure.
第1図の第一層目のN型薄膜半導体及び第二層
目のP型薄膜半導体の膜厚は、アモルフアスSiの
場合で数百Å〜数千Åであり、第二層目の薄膜半
導体すなわちP型薄膜半導体4はピンホールが生
じやすく、前記第二層目の薄膜半導体4のコンタ
クト部にピンホールが生じた場合、メタル配線6
により前記ピンホールを通してPN接合が短絡さ
れてしまう。 The film thickness of the first layer N-type thin film semiconductor and the second layer P-type thin film semiconductor in FIG. 1 is from several hundred Å to several thousand Å in the case of amorphous Si, That is, the P-type thin film semiconductor 4 is susceptible to pinholes, and if a pinhole occurs in the contact portion of the second layer thin film semiconductor 4, the metal wiring 6
This causes the PN junction to be short-circuited through the pinhole.
本発明の目的は、前述の欠点をなくし薄膜太陽
電池の歩留の向上、信頼性の向上をはからんとし
たものである。 An object of the present invention is to eliminate the above-mentioned drawbacks and improve the yield and reliability of thin film solar cells.
第2図は本発明による薄膜太陽電池を示した断
面図である。 FIG. 2 is a sectional view showing a thin film solar cell according to the present invention.
絶縁基板1上にネサ電極2を所定のパターンに
形成する。絶縁基板1及びネサ電極2の全面に第
一の薄膜半導体3(例えばN型薄膜半導体)を形
成したのち所定の形状にパターンニングする。前
記第一の薄膜半導体と相異なる型の第二の薄膜半
導体4(例えばP型薄膜半導体)を前記第一の薄
膜半導体3、ネサ電極2、絶縁基板1の全面に形
成し、第二の薄膜半導体の一部Aが第二の薄膜半
導体と基板の間に電極及び第一の半導体が存在し
ない部分に形成されることを含む所定のパターン
を形成する。 Nesa electrodes 2 are formed in a predetermined pattern on an insulating substrate 1. A first thin film semiconductor 3 (for example, an N-type thin film semiconductor) is formed on the entire surface of the insulating substrate 1 and the NESA electrode 2, and then patterned into a predetermined shape. A second thin film semiconductor 4 of a type different from the first thin film semiconductor (for example, a P-type thin film semiconductor) is formed on the entire surface of the first thin film semiconductor 3, the NESA electrode 2, and the insulating substrate 1, A predetermined pattern is formed in which a portion A of the semiconductor is formed between the second thin film semiconductor and the substrate in a portion where the electrode and the first semiconductor are not present.
このとき第一の薄膜半導体3の電極2の引出し
部では、第二の薄膜半導体4と電極2が短絡しな
いようにマスク合わせ誤差以上の余裕を第3図に
示したようにとることが必要である。 At this time, in the lead-out portion of the electrode 2 of the first thin film semiconductor 3, it is necessary to provide a margin greater than the mask alignment error, as shown in FIG. 3, to prevent short circuit between the second thin film semiconductor 4 and the electrode 2. be.
全面に絶縁膜5を形成したのち、前記第二の薄
膜半導体の一部A上でメタル配線6とコンタクト
がとれるように所定の穴あけをしてさらに所定の
メタル配線6をして本発明の薄膜太陽電池が形成
される。 After forming the insulating film 5 on the entire surface, a predetermined hole is made on the part A of the second thin film semiconductor so as to make contact with the metal wiring 6, and further a predetermined metal wiring 6 is formed, thereby forming the thin film of the present invention. A solar cell is formed.
さらには、電極2の引出し部以外の部分では各
層の間で短絡しないように各層ごとに基板側をお
おつておくことが必要である。第3図、第4図は
それぞれ第2図の拡大図及び平面図である。 Furthermore, in areas other than the lead-out portion of the electrode 2, it is necessary to cover the substrate side of each layer to prevent short circuits between the layers. 3 and 4 are an enlarged view and a plan view of FIG. 2, respectively.
本発明のごとく、第二層目の薄膜半導体とメタ
ル配線とのコンタクト部で第二層目の薄膜半導体
と絶縁基板の間に電極及び電極とコンタクトされ
た第一層目の薄膜半導体が存在した構造とするこ
とにより、コンタクト部での短絡をふせぐことが
可能となり薄膜太陽電池の歩留を向上させ信頼性
を向上させることが出来る。 As in the present invention, there is an electrode and a first layer thin film semiconductor in contact with the electrode between the second layer thin film semiconductor and the insulating substrate at the contact portion between the second layer thin film semiconductor and the metal wiring. This structure makes it possible to prevent short circuits at the contact portion, thereby improving the yield and reliability of thin-film solar cells.
上記本発明の説明において絶縁膜5を層間絶縁
膜として使用したが、本発明の構造によれば層間
絶縁膜5を使用しなくともよい。またP型及びN
型について、相方いれかえた形でも本発明の効果
はかわらない。 In the above description of the present invention, the insulating film 5 was used as an interlayer insulating film, but according to the structure of the present invention, the interlayer insulating film 5 may not be used. Also P type and N
Even if the molds are replaced, the effects of the present invention remain the same.
またP型及びN型の薄膜半導体の間に不純物を
ドーブしないI型半導体をはさんだPIN型構造も
のがあるが、この構造に対しても本発明の効果は
かわらない。 There is also a PIN structure in which an I-type semiconductor not doped with impurities is sandwiched between P-type and N-type thin film semiconductors, and the effects of the present invention are the same even with this structure.
すなわち、基板と相対する端の層の薄膜半導体
における電極配線とのコンタクト部において、前
記薄膜半導体と基板との間にすくなくとも絶縁物
以外は存在したこと、また薄膜半導体と接続され
た基板側の電極引出し部においては各層間で短絡
しないようにアライメント誤差以上に合わせしろ
をもうけること、また前記電極引出し部以外の部
分においては各層間で短絡しないよう各層ごとに
基板側の層をおおう構造とする。 That is, at the contact portion with the electrode wiring in the thin film semiconductor of the end layer facing the substrate, at least something other than an insulator existed between the thin film semiconductor and the substrate, and the electrode on the substrate side connected to the thin film semiconductor In the lead-out part, an alignment margin greater than the alignment error is provided to prevent short-circuiting between each layer, and in parts other than the electrode lead-out part, each layer is covered with a layer on the substrate side to prevent short-circuiting between the layers.
このことはPN構造のものと同様である。 This is similar to the PN structure.
上述の如く本願発明は、第二の型の薄膜半導体
の一部は、絶縁基板上に直接形成され、この直接
形成された薄膜半導体の部分上にのみメタル配線
と第二の薄膜半導体とが接続されて形成されたか
ら、メタル配線材料が第二の型の薄膜半導体をつ
き抜けることによつて、第一の型の薄膜半導体と
の短絡を生じることがなく、このような短絡欠陥
による歩留の低下を防ぎ、デバイスの信頼性を向
上することができる効果を有する。 As described above, in the present invention, a part of the second type thin film semiconductor is formed directly on the insulating substrate, and the metal wiring and the second thin film semiconductor are connected only on the directly formed part of the thin film semiconductor. Since the metal wiring material is formed using a thin film semiconductor of the second type, the metal wiring material does not penetrate through the thin film semiconductor of the second type and cause a short circuit with the thin film semiconductor of the first type. This has the effect of preventing deterioration and improving device reliability.
第1図は、従来の薄膜太陽電池の構造を示す断
面図である。第2図は、本発明による薄膜太陽電
池の構造を示す断面図である。第3図は、第2図
の拡大図である。第4図は、第2図の平面図であ
る。たゞし、基板及び絶縁膜は省略してある。第
1図から第4図まで各添字は共通になつている。
FIG. 1 is a sectional view showing the structure of a conventional thin film solar cell. FIG. 2 is a sectional view showing the structure of a thin film solar cell according to the present invention. FIG. 3 is an enlarged view of FIG. 2. FIG. 4 is a plan view of FIG. 2. However, the substrate and insulating film are omitted. Each subscript is common from FIG. 1 to FIG. 4.
Claims (1)
び電極上の一部に第一の型の薄膜半導体を有し、 前記第一の型の薄膜半導体上のすくなくとも一
部と重なる第二の型の薄膜半導体を有し、該第二
の型の薄膜半導体上の一部にメタル配線が形成さ
れてなる太陽電池において、該第二の型の薄膜半
導体の一部は、該絶縁基板上に直接形成されてな
り、該直接形成された薄膜半導体の部分上にのみ
該メタル配線と、該第二の薄膜半導体とが接続さ
れてなることを特徴とする薄膜太陽電池。[Scope of Claims] 1. An electrode is provided on an insulating substrate, a first type thin film semiconductor is provided on a portion of the insulating substrate and the electrode, and at least one portion of the first type thin film semiconductor is provided on the first type thin film semiconductor. In a solar cell having a second type of thin film semiconductor that overlaps with the second type of thin film semiconductor, and a metal wiring is formed on a part of the second type of thin film semiconductor, a part of the second type of thin film semiconductor overlaps with the second type of thin film semiconductor. A thin film solar cell, characterized in that it is formed directly on the insulating substrate, and the metal wiring and the second thin film semiconductor are connected only on the directly formed portion of the thin film semiconductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13806779A JPS5661175A (en) | 1979-10-25 | 1979-10-25 | Thin-film solar cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13806779A JPS5661175A (en) | 1979-10-25 | 1979-10-25 | Thin-film solar cell |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5661175A JPS5661175A (en) | 1981-05-26 |
JPS6141156B2 true JPS6141156B2 (en) | 1986-09-12 |
Family
ID=15213194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13806779A Granted JPS5661175A (en) | 1979-10-25 | 1979-10-25 | Thin-film solar cell |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5661175A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0485443U (en) * | 1990-11-30 | 1992-07-24 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5935491A (en) * | 1982-08-24 | 1984-02-27 | Sanyo Electric Co Ltd | Photo semiconductor device |
JPS6071151U (en) * | 1983-10-22 | 1985-05-20 | 太陽誘電株式会社 | solar cells |
JPH04116160U (en) * | 1991-03-29 | 1992-10-16 | 三洋電機株式会社 | photovoltaic device |
-
1979
- 1979-10-25 JP JP13806779A patent/JPS5661175A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0485443U (en) * | 1990-11-30 | 1992-07-24 |
Also Published As
Publication number | Publication date |
---|---|
JPS5661175A (en) | 1981-05-26 |
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