JPS6135011A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To reduce undesirable power consumption without increasing a control signal by resetting/setting a shift register circuit in response to the control of a selection circuit of a bypass line. CONSTITUTION:When selection 27-30 are all thrown to the bypass position by control signals 32-35, a signal impressed to an input terminal 21 bypasses shift register SR circuits 23-26 and is transmitted to an output terminal 22. Since the input signal is not fed to any SR circuit whose operation is not required, unnecessary power consumption is caused. When the circuits 27-30 select all the SR circuits, a total 15-bit delay is applied at the terminal 22. The number of delayed bits is changed from 0 to 15-bit by combining properly the signals 32- 35. The circuits 23-26 are reset/set corresponding to the selection of the circuits 27-30 and no power is consumed at reset.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a delay circuit with a variable number of bits used in digital signal processing, etc., and particularly to a delay circuit suitable for semiconductor integrated circuit implementation.

(Prior Art) FIG. 1 is a diagram of a conventional variable bit number delay circuit in which the number of delay bits can be changed for each bit from 0 to 15 bits. 8 bit, 4 bit.

2-bit and 1-bit shift register circuit 3°4.5
and 6 are arranged in series in this order, and any one of the input and output sides of these shift register circuits 3, 4, 5 and 6 is selected as a selection circuit in response to control signals 12, 13, 14 and 15. , 8.9 and 10, and are connected to the input side and output terminal 2 of the subsequent shift register circuit 4.5, respectively.

The input side of the shift register circuit 30 in the side stage is the input terminal 1, and is simultaneously controlled by the clock from the terminal 11 of each of the shift register circuits 3, 4, 5, and 6. For example, when the control signals 12, 13, 14, and 15 select all the shift register circuits 7 to 10 on the bypass side, that is, the input side, the signal applied to the input terminal 1 selects all the shift register circuits 3 to 6. Since the signal is bypassed and applied to the output terminal 2, the number of delay bits becomes zero. Furthermore, when the selection circuits 7 to 10 all select the input side of the shift register circuit, the 1η signal applied to the input terminal 1 passes through all the shift register circuits 3 to 6, so it is delayed by a total of 15 bits and output. Hail appears on terminal 2.

By appropriately combining the control signals 12, 13, 14.degree. 15, the circuit of FIG. 1 can change the number of delay bits from .theta. bits to 15 bits.

FIG. 2 shows another example of a variable delay circuit, in which 2 bits to 1
The number of delay bits can be changed for each bit up to 7 bits, and parts corresponding to those in FIG. 1 are given the same reference numerals. In this example, shift register circuits 3 and 4
．． 5 and 6, respectively, are provided with 0.5-bit shift register circuits 16, 17, 18 and 19, respectively, and are connected to the input sides ajF' of the corresponding shift register circuits. Selection circuits 7, 8.9 and 1
0 are shift register circuits 3, 16.4, 17.
Each output side of 5.18 and 6,19 is selected. Shift register circuits 16 to 19 are also controlled by the clock at terminal 11. Shift register circuit 3, 4, 5.6
are respectively 8.5 bits, 4.5 bits, 2.5 bits, and 1.5 bits.

The shift register circuits 3 and 16 and the selection circuit 7 constitute a basic configuration circuit, and at the same time, the shift register circuit 4゜17, the selection circuit 8, the shift register circuit 5゜18, the selection circuit 9,
Furthermore, the shift register circuit 6.degree. 19 and the selection circuit 10 are also basic component circuits, and these basic component circuits are connected in cascade.

Selection circuits 7, 8 according to control signals 12.13, 14.15
, 9.10' are shift register circuits 16 and 17, respectively.
, 18, 19, the signal applied to input terminal 1 is sent to shift register circuits 16, 17, 18, 19.
It passes through and is delivered to output terminal 2. The number of delay bits during this time is 0.5 x 4 = 2 bits. Further, delay circuits 7, 8, 9.10 are shift register circuits 3, 4, respectively.
, when the 5.6 side is selected, the number of delay bits from input terminal 1 to output terminal 2 is 8.5 + 4.5 + 2.5 +
1.5=17 bits. Therefore, the control signals 12, 13
By appropriately combining ゜14.15, the number of delay bits can be changed for each bit from 2 bits to 17 bits.

The two variable delay circuits mentioned above are shift registers 3.4,
Even if 5.6 is not selected, each shift register 3, 4, 5.6 is in an operating state.

For this reason, although there is no need for operation if it is not selected, there is a drawback that extra power is consumed.

(Object of the Invention) An object of the present invention is to provide a delay circuit that reduces undesired power consumption without increasing control signals.

(Description of an Embodiment) FIG. 3 is a circuit diagram of an embodiment of a variable bit number delay circuit that can change the number of delay bits for each bit from 0 to 15 bits according to the present invention.

8-bit, 4-bit, 2-bit, and 1-bit shift register circuits 23, 24, 25, and 26 are arranged in series in this order, and these shift register circuits 23, 24,
Either the input side or the output side of 25 and 26 is controlled by selection circuits 27, 28, 29 and 30 in response to control signals 32, 33, 34 and 35, respectively, and each subsequent shift register circuit 24 .25 input side and output terminal 2
2, respectively. First stage shift register circuit 2
The input side of 30 is an input terminal 21, and each shift register circuit 23, 24, 25, 26 is simultaneously controlled by a clock from a terminal 31.
24, 25, and 26, only the first stage of each shift register circuit has a reset function or a set function, and the reset or set input terminal of each shift register circuit is provided with a control signal 32, 33, and 3.
4.35 respectively to control the operation of each shift register circuit. The basic operation is the same as that in FIG. 1, but for example, the selection circuits 27 to 27 are
When all the shift register circuits 30 select the bypass side, that is, the input side, the signal applied to the input terminal 21 bypasses all the shift register circuits 23 to 26 and is applied to the output terminal 22, so the number of delay bits becomes zero. . At this time, the shift register circuit that does not take out the delayed output receives control signals 32 and 33.
, 34°35. Therefore, since input signals are not transmitted to shift register circuits that do not require operation, unnecessary power consumption can be reduced. Further, when all of the selection circuits 27 to 30 select the shift register circuit ti, the operation is exactly the same as that shown in FIG. 1, and the signal is output to the output terminal 22 with a total delay of 15 bits. By appropriately combining the control signals 32, 33 and 34, 35t, the circuit of FIG. 3 can change the number of delay bits from .theta. bits to 15 bits, similar to the circuit of FIG. 1. In addition, power consumption can be reduced because the input signal is not transmitted to the inside of the shift register circuit that is not selected by the control signals 32 to 35.

FIG. 4 shows another embodiment of the variable delay circuit according to the present invention with respect to FIG. Shown with the same reference numerals. In this example, shift register circuits 23, 24, 25 and 26 and 0.5 bit-shift register circuits [36
, 37, 38 and 39 are provided, respectively, and the input sides of the corresponding shift register circuits are connected to each other. Selection circuits 27, 28, 29 and 30 are shift register circuits 23, 36, 24, 37.25° 38 and 26, respectively.
．． 39 output sides are selected. Shift register circuits 36 to 39 are also controlled by the clock at terminal 31. The shift register circuits 23, 24, 25, and 26 are respectively 8, 5 bits, 4.5 bits, 2.5 bits, 1.
It is assumed to be 5 bits. Moreover, the shift register circuit 23,
Only the first stage of each circuit of 24°25.26 is provided with a reset or set function, and the reset or set input terminal of each shift register circuit is provided with a control signal 32, 33, 3.
4.35 respectively to control the operation of each shift register circuit.

The shift register circuits 23, 36 and the selection circuit 27 constitute a basic configuration circuit, and at the same time the shift register circuits 24, 37,
The selection circuit 28, the shift register circuit 25.3g, the selection circuit 29, the shift register circuits 26, 39, and the selection circuit 30 are each a basic configuration circuit, and these basic configuration circuits are connected in cascade. There is.

The basic operation is the same as in Fig. 2, but for example, the control signal 3
2, 33, 34. 35 selection circuit 27. 28, 29
．． 30 are shift register circuits 36, 37, 38 respectively
．． 39, the signal applied to the input terminal 21 is applied to the output terminal 22 through shift register circuits 36, 37, 38, and 39. The number of delay bits during this time is 0.5×4=2 bits. At this time, the shift register circuit that does not take out the delayed output receives the control signal 32°33.
34 and 35 are reset or set to prevent input signals from being transmitted to shift register circuits that do not require operation, thereby reducing unnecessary power consumption. Further, the selection circuits 27 to 30 all operate in the same manner as in Fig. 2, in which the shift register circuits are selected, and the number of delay bits from the input terminal 21 to the output terminal 22 is &5 + 4.5.
+2.5 +1.5 = 17 bits. Therefore, if the control signals 12, 13°, 14.15 are appropriately combined, 2
The number of delay bits can be changed for each bit from bit to 17 bits.

In Figures 3 and 4, the explanation was given using an example in which the maximum variable delay is relatively small, but a selection is made in which a delay circuit with a large maximum variable delay is used, and moreover, there are many unnecessary parts of the circuit corresponding to the shift register circuits 23 to 26. In this case, the present invention tends to have a very large effect and can reduce power consumption.

(Explanation of Effects) As explained above, the variable delay circuit according to the present invention can reduce power consumption without increasing control signals or complicating the circuit, and operates in exactly the same way as the conventional circuit. Is possible.

[Brief explanation of drawings]

1 and 2 are block diagrams showing a conventional variable delay circuit, and FIGS. 3 and 4 are block diagrams showing first and second embodiments of the variable delay circuit according to Jin's invention. 1.21: Signal input terminal, 2.22: Signal output terminal, 3, 4, 5, 6, 16, 17, 18, 19. -to23
・24・25・26・36・37・38・39 Rin: Shift register circuit as a delay circuit, 7,8°9.
10,27,28.2゛9,30: Selection circuit, 11.3
1: Clock input terminal, 12.13,14°15.
32, 33, 34, 35: selection circuit control signal

Claims (1)

[Claims] (1) One input side of the first delay circuit and one input side of the second delay circuit are commonly connected, and the output side of the first delay circuit is connected to one input side by a control signal. The output side of the second delay circuit is connected to the other input side of the selection circuit, and the control signal is connected to the other input side of the first delay circuit. A plurality of basic component circuits are connected in cascade, each having an inverted output of the control signal connected to the other input side of the second delay circuit, and the control signals of these basic component circuits to the selection circuit are changed. A variable delay circuit characterized by making the number of delay bits variable.