JPS6132446Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a form processing device that determines the column position where a mark, punch, number, or character is recorded in a form such as an IBM card.

When reading the card data of the IBM card in the above example, the conventional reading means reads the card at a sampling period of multiple times per column, stores this in the memory circuit, and at the same time calculates the number of sampling times for the entire length of the card. The number of column pitch samplings was calculated by dividing the number of column pitches by the total number of columns, and each column position was determined using the number of column pitch samplings as a period.

In this way, the total number of samplings of the total document length was used to determine the column position, so if the total document length is arbitrary, or if there is a perforation at the rear end of the document and an area other than column data is created, the total length of the document This method has disadvantages in that it is not possible to specify the total number of samplings, it is not possible to measure the total number of samplings, and it is not possible to accurately determine the column position.

Therefore, the object of this invention is to provide a form processing device that can accurately determine the column position even if the total length of the form is arbitrary or even if there is an area other than column data at the rear end of the form.

According to this invention, pulses are generated at a cycle in which multiple pulses are emitted to the column position of the form being conveyed, the number of pulses is counted while the form is conveyed over a predetermined distance, and this counted value is calculated. Since the number of pulses of the column position pitch is calculated and each column position is determined based on the period of this number of pulses, the column position can be determined accurately regardless of the length of the form and the number of columns.

An embodiment of this invention having such characteristics will be described in detail below based on the drawings.

The drawing shows a device for reading marks or punches placed in column positions on a card, such as an IBM card, and the card used in this device is constructed as shown in FIG.

In other words, the card 1 has a data area with 12 columns in the horizontal direction, which are divided at predetermined intervals in the vertical direction to form column positions 2, and these column positions 2 are marked with marks 3. The data is structured by the following.

Mark 3A in the figure is a separator code,
Indicates the separation of data items.

FIG. 2 shows a reading device for the above-mentioned card 1,
The transport rollers 4 are driven and controlled by a motor 5, and transport the card 1 in the direction of the arrow.

The first detector 6 is provided at the starting end of the conveyance path,
It is detected that the card 1 is supplied to the conveyance path.

The second detector 7 is provided at the data reading position of the card 1, and detects that the card 1 has been conveyed to the reading position.

The first and second detectors 6 and 7 described above are set at a predetermined interval Lo, and are constituted by well-known photoelectric sensors consisting of a light projector and a light receiver.

A reading head 8 is provided at the aforementioned reading position, and this head 8 covers 12 of the data areas of the card 1.
It is composed of a number of photoelectric sensors corresponding to the number of columns so as to read each column at once.

Note that 9 is a glass fiber that guides the reflected light from the projector to the receiver.

FIG. 3 shows a control circuit, and the CPU 10 controls each circuit device and also performs arithmetic processing.
The ROM 11 stores a program for this device, and operates according to this program. RAM
12 writes and reads data.

A transmission control circuit 13 performs data transmission between this device and the sensor. The motor control circuit 14 is connected to the motor 5
The drive control is performed. A read control circuit 15 performs read control of the read head 8.

Since the interrupt control circuit 16 performs card data reading processing by interrupt processing, it controls this interrupt.

The first detector 6 is inputted to the interrupt control circuit 16 via an integrating circuit 17 which differentiates and outputs the rising edge of the card detection signal, and the second detector 7 differentiates and outputs the rising edge of the card detection signal.
The signal is input to the interrupt control circuit 16 via.
Based on the detection signals from the first and second detectors 6 and 7, it is detected that the card is being conveyed through the section set by both the detectors 6 and 7.

Also, the second detector 7 via the above-mentioned differentiation circuit 18
The detection signal is used as a reading start signal,
Furthermore, it is inputted as the end of reading through an inverter 19 and a differentiation circuit 20 that differentiates and outputs the rising edge of the signal.

The clock pulse generation circuit 21 generates pulses at a period to be described later, and these pulses are input to the interrupt control circuit 16 via an AND gate 22 gate-controlled by the CPU 10.

The period of the clock pulse generated by the clock pulse generation circuit 21 mentioned above is as shown in FIG.
It is provided at a period in which two pulses are generated in one column while the card 1 is being transported.

Further, the length of each column 2 of the card 1 is set to _L1 , and the length from the leading edge of the card 1 to the first column position 2 is set to be _L2 .

FIG. 5 shows the memory area of the RAM 12, and area 23 is the distance between the first and second detectors 6 and 7.
Lo is stored, the area 24 stores the pitch L ₁ of column 2, and the area 25 stores the distance L ₂ from the tip of the card 1 to the first column position 2.

A flag 1 is set in the area 26, and this flag indicates that the second detector 7 detects the leading edge of the card 1. Flag 2 is set in area 27, and this flag indicates that the reading position of the first column position has been reached.

Area 28 stores the total number of pulses A between the detectors 6 and 7, and this total number of pulses A refers to the pulses generated by the clock pulse generator 21 while the leading edge of the card 1 is conveyed between the detectors 6 and 7. It is a number. Area 29 is located at the first column position 2 from the leading edge of card 1.
The number of pulses B between column pitches is stored in area 30, and the number of pulses C between column pitches is stored in area 30. In area 31, a pulse count value D obtained by counting pulses between column positions is stored.

A designated address E within the buffer is stored in the area 32, and this address E is the address of the buffer area 35 in which column data is stored. In the area 33, the start address of the buffer area 34 is stored. An end flag is set in area 34, and this flag points the rear end of the card to the second
It is set when the detector 7 detects it. The read data of each column position 2 . . . is stored in the buffer area 35 according to the address specification of the area 32.

The operation will be explained with reference to FIGS. 6 and 7.
In the main routine of Figure 6, this device
It operates according to the program in ROM11, and at the beginning
The flags in areas 26 and 27 of RAM 12 are reset, and the data in areas 28-32 are cleared. Thereafter, the start address of the buffer area 34 is moved from the area 33 and stored in the area 32.

Next, when card 1 is supplied to the conveyance path, the first
The detector 6 detects this, and based on this detection signal, the motor control circuit 14 drives the motor 5, the conveying rollers 4 are driven, and the card 1 is conveyed to the reading head 8 side.

Next, in the main routine, it is checked in area 34 of RAM 12 whether the end flag of the form is set.
The card data is read by an interrupt until this flag is set.

That is, in the interrupt routine shown in FIG. 7, when the first detector 6 detects the leading edge of the card 1, the signal is input to the interrupt control circuit 16, and an interrupt for the reading process is started.

In response to this interrupt, the CPU 10 outputs a gate signal to the AND gate 22, and the pulses from the clock pulse generation circuit 21 are inputted via the AND gate 22.

The CPU 10 counts the input pulses and stores them in the area 28 of the RAM 12.
is detected by the second detector 7, and the total number of pulses A is stored in the area 28.

When the second detector 7 detects the leading edge of the card 1, flag 1 is set based on the detection signal, and then the CPU 10 detects the area 23 of the RAM 12,
Based on the data of 25 and 28, that is, the distance Lo between the detectors 6 and 7, the distance L ₂ to the first column position 2, and the total number of pulses A between the detectors 6 and 7, L ₂ ×A/ Perform the calculation of L ₀ to calculate the number of pulses B to the first column position 2, and add this to the area 29 of RAM 12.
Store in.

Furthermore, using the data of areas 23, 24, and 28, that is, the distance L ₀ described above, the column pitch L ₁ , and the total number of pulses A described above, the calculation of L ₁ ×A/L ₀ is performed to calculate the distance between the column pitches. The number of pulses C
is calculated and stored in area 30 of RAM 12.

Next, the CPU 10 checks the flag 1 in the area 26 of the RAM 12, counts the pulses from the time when the second detector 7 detects the leading edge of the card 1, stores them in the area 30, and calculates the number of pulses D between columns. It is checked whether or not it matches the number B of pulses up to the first column position 2 stored in area 29.

When the pulse numbers D and B match, the detection position of the second detector 7 is then on the line of the first column position 2, and the reading head 8, which is co-linear with the second detector 7, is also on the line of the first column position 2. It is on position 2.

Therefore, the CPU 12 controls the read control circuit 15, the read head 8 reads the column data at that time, and transfers this first column data to the RAM 12.
Buatuhua area 35 designated in area 32 of
Store in.

Then, the designated address E in area 32 is incremented by +1 and stored, and the number of pulses D between columns in area 31 is cleared.

When the CPU 10 stores the data in the first column, it counts the pulses again from the point of storage.
It is stored in area 31 of RAM 12 and the number of pulses between the next columns is counted.

Since flag 2 is set in area 27 of RAM 12, the number of pulses C between column pitches in area 30 and the number D of pulses between columns mentioned above are set.
It is checked whether or not they match.

When the number of pulses D and C match, the positions of the second detector 7 and the reading head 8 are on the line of the second column position 2, so the CPU 10 controls the reading control circuit 15, and the reading head 8 The column data at that time is read and the data of this second column is stored in the buffer area 35 specified by the area 32 of the RAM 12.

Thereafter, the specified address E in area 32 is incremented by +1 as described above, and the number of pulses D between columns in area 31 is cleared.

This kind of reading process is repeated in sequence,
The data of each column 2 .

When the second detector 7 detects the trailing edge of the card 1, an end flag is set in the area 34 of the RAM 12, and the interrupt process for the reading process ends.

In the main routine shown in FIG. 6, when the end flag of the form is checked and this flag is found to be set, the motor control circuit 14 stops driving the motor 5, and the CPU 10 reads the column stored in the buffer area 35 of the RAM 12. The data is processed, necessary data is transmitted to the center via the transmission control circuit 13, and the main routine ends.

In the embodiment described above, the output of the reading head 8 can also be used as the second detector 7.
Further, the mark 3 on the card 1 may be a punch, a number, a letter, or the like. But that's fine.

[Brief explanation of the drawing]

The drawings show one embodiment of this invention, with Fig. 1 being a plan view of the card, Fig. 2 being a schematic side view of the card reading device, Fig. 3 being a block diagram of the control circuit, and Fig. 4 being an enlarged explanation of a portion of the card. 5 is an explanatory diagram of the RAM area, FIG. 6 is a flowchart of the main routine, and FIG. 7 is a flowchart of the interrupt routine. 1... Card, 2... Column position, 3... Mark, 6... First detector, 7... Second detector, 8...
...Read head, 10...CPU, 12...
RAM, 16...interrupt control circuit, 21...clock pulse generation circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] A pulse generating circuit that generates pulses at a cycle of emitting multiple pulses to the column position of a transported form, and a form detector that detects that a form is transported over a predetermined area. , while the form detector is detecting a form, the number of pulses emitted by the pulse generation circuit is counted, the number of pulses at the column position pitch is calculated from this counted value, and each column position is A form processing device equipped with a control circuit that determines.