JPS6132446A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6132446A JPS6132446A JP15288184A JP15288184A JPS6132446A JP S6132446 A JPS6132446 A JP S6132446A JP 15288184 A JP15288184 A JP 15288184A JP 15288184 A JP15288184 A JP 15288184A JP S6132446 A JPS6132446 A JP S6132446A
- Authority
- JP
- Japan
- Prior art keywords
- filler
- resin
- sealing material
- particle size
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分力′〕
本発明は半導体装置、特に、樹脂封止型の半導体装置に
適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Power'] The present invention relates to a technique that is effective when applied to semiconductor devices, particularly resin-sealed semiconductor devices.
半導体装置の樹脂封止に用いられる樹脂封止材料は樹脂
にフィラーを添加したものよりなるが、フィラーの粒径
によりその成形性や半導体装置の耐湿性等に差異が生じ
る。しかも、フィラーの粒径にばらつ鍍が生じると、粗
い粒子の含有率が高い場合、半導体装置の耐湿性等に対
して悪影響を及ぼす。The resin encapsulation material used for resin encapsulation of semiconductor devices is made of resin with filler added, but the moldability and moisture resistance of the semiconductor device vary depending on the particle size of the filler. Furthermore, if the particle size of the filler varies, if the content of coarse particles is high, it will have an adverse effect on the moisture resistance of the semiconductor device.
そこで、粗い素子の含有率を低くする為、フィラーを細
粒化することが考えられる。Therefore, in order to reduce the content of coarse elements, it is possible to make the filler grains finer.
ところが、粉砕時間の延長等によりフィラーの細粒化を
行なえば、粗い粒子含有率を低下させ、粗い粒子の及ぼ
す悪影響を低減出来るものの、細粒化に伴なう単位重量
当りの表面積増加に起因し２樹脂封止材料金体の溶融粘
度が増大するため、樹脂封止材料の流動性が低下し、成
形性が悪くなり、ワイヤの曲り等をひき起こす、という
問題を生じることが本発明者によって見い出された。However, if the filler is made finer by extending the grinding time, etc., the content of coarse particles can be lowered and the negative effects of coarse particles can be reduced. However, the present inventors have discovered that, as the melt viscosity of the resin sealing material increases, the fluidity of the resin sealing material decreases, resulting in poor moldability and bending of the wire. was discovered by.
なお、樹脂封止型半導体装置の樹脂材料については、株
式会社サイエンスフォーラム、昭和５８年１１月２８日
発行の「超ＬＳＩデバイスハンドブックＪ ｐ２２４に
説明されている。The resin materials for resin-sealed semiconductor devices are explained in "Very LSI Device Handbook J," published by Science Forum Co., Ltd. on November 28, 1980, p.224.
本発明の目的は、樹脂封止材料の溶融粘度を好適なもの
とし、成形性を良好にすることのできる技術を提供する
ことにある。An object of the present invention is to provide a technique that can improve the melt viscosity of a resin sealing material and improve its moldability.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、樹脂封止材料中に含有されるフィラーのうち
粒径２μｍ以下のものの累積含有率が３％以下であるよ
うな粒度分布でフィシ−を構成することにより、成形性
を向上させることができる・ ものである。That is, moldability can be improved by configuring the fissy with a particle size distribution such that the cumulative content of fillers with a particle size of 2 μm or less among the fillers contained in the resin sealing material is 3% or less.・It is something.
第１図は本発明による一実施例である樹脂封止ＪＪｊｌ
半専体装僅における封止材中のフィラーの粒径とその累
積含有率との関係を示す図（フィラーの累積粒度分布図
）、第２図はフィラーの粒径とＡｕ線曲り率との関係を
示す図、第３図は樹脂封止型半導体装置の一例を示す断
面図である。FIG. 1 shows a resin-sealed JJjl according to an embodiment of the present invention.
Figure 2 shows the relationship between filler particle size and its cumulative content in the encapsulant in semi-dedicated packaging (filler cumulative particle size distribution diagram). FIG. 3, a diagram showing the relationship, is a sectional view showing an example of a resin-sealed semiconductor device.
第３図に示すように、樹脂封止型半導体装置はリードフ
レームのタブ１上にベレット２をポンディンクシ、次ニ
該ヘレソト２のポンプイングツくソドとリードフレーム
のインナーリード３とを金（Ａｕ）またはアルミニウム
（Ａ、ｅ）等のワイヤ４でボンディングした後、ペレッ
ト２やワイヤ４等を封止材５でモールドして封止し、リ
ードフレームを切断成形してアウターリード６のみが封
止材５外に突出するようにしたものである。As shown in FIG. 3, in the resin-sealed semiconductor device, a pellet 2 is pumped onto the tab 1 of the lead frame, and then the pumping rod of the pellet 2 and the inner lead 3 of the lead frame are bonded with gold (Au or gold). After bonding with a wire 4 made of aluminum (A, e), etc., the pellet 2, wire 4, etc. are molded and sealed with a sealing material 5, and the lead frame is cut and molded so that only the outer leads 6 are covered with the sealing material 5. It is designed to protrude outward.
このような樹脂封止型の半導体装置において、封止パッ
ケージを構成する封止材５はたとえばエポキシ樹脂で構
成されるが、その中にはたとえば溶融シリカ粉あるいは
結晶シリカ等よりなるフィラー７が機械的強度や熱膨張
係数の改善等のために所定隼だけ含有されている。In such a resin-sealed semiconductor device, the sealing material 5 constituting the sealed package is made of, for example, epoxy resin, and a filler 7 made of, for example, fused silica powder or crystalline silica is machined therein. It is included in a predetermined amount in order to improve the mechanical strength and coefficient of thermal expansion.
本実施例では、このフィラー７０粒径を所定の粒径分布
のものにすることにより、封止材５の成形性を改善する
ものである。In this embodiment, the moldability of the sealing material 5 is improved by making the particle size of the filler 70 have a predetermined particle size distribution.
すなわち、フィラー７０粒径が大きすぎることによる悪
影響を除くためにその粒径な小さくしすぎると、逆に細
粒化に起因する封止材５の溶融粘度の増大を来たし、溶
融粘度があまり高くなり過ぎるとワイヤ流れやワイヤ曲
り等をひき起こすことを本発明者は見い出し、本発明を
なすに至ったものである。That is, if the particle size of the filler 70 is made too small in order to eliminate the negative effects caused by the particle size being too large, the melt viscosity of the sealing material 5 will increase due to the particle size reduction, and the melt viscosity will become too high. The inventor of the present invention has discovered that if the wire is too thick, it causes wire flow, wire bending, etc., and has led to the present invention.
言し・換えれば、本実施例では、封止材５の中のフィン
−７０粒径が、２μｍ以下のものを添加するに際し、そ
の２μｍ以下のフィラーの累積含有率を３％以下（含有
フィラー総重量は所定）とすることにより、封止材５の
溶融粘度が必要以上に大きくなって成形性の低下、ワイ
ヤ曲りを生じることを防止できたものである。In other words, in this example, when adding the fin-70 particle size of 2 μm or less in the sealing material 5, the cumulative content of the filler with a particle size of 2 μm or less is 3% or less (the filler contained By setting the total weight to a predetermined value, it is possible to prevent the melt viscosity of the sealing material 5 from becoming larger than necessary, thereby preventing deterioration in moldability and wire bending.
このことを図面に示したグラフについて説明すると、第
１図において、横軸はフィシ−０粒径〔μｍ〕、縦軸は
その粒径毎の含有率〔重量％〕を示し、曲線Ａ、Ｂ、Ｃ
，Ｄは供試封止材Ａ、Ｂ。To explain this with respect to the graphs shown in the drawings, in Fig. 1, the horizontal axis shows the Ficy-0 particle size [μm], the vertical axis shows the content rate [wt%] for each particle size, and curves A and B , C
, D are the test sealing materials A and B.
Ｃ，Ｄ中のフィラーの粒度分布を示している。また、第
２図において、横軸は前記供試封止材Ａ。The particle size distribution of fillers in C and D is shown. In addition, in FIG. 2, the horizontal axis represents the sample sealing material A.
Ｂ、Ｃ，Ｄにおいて粒径０〔μｍ〕から順に含有率を累
積して累積含有率が３重量％を超えるに致った粒径〔μ
ｍ〕、縦軸はＡｕ線曲り率〔％〕を示している。In B, C, and D, the particle size [μ
m], and the vertical axis indicates the Au wire curvature [%].
第１図および第２図から明らかなように、供試封止材Ｂ
、Ｃ，Ｄの場合にはフィラー粒径が２μｍ以下のものの
累積含有率が３％以下であり、また累積含有率が３％を
超える粒径が２μｍ以上であるＢ、Ｃ，Ｄの場合にはＡ
ｕ線曲り率が５％以下である。As is clear from FIGS. 1 and 2, the sample sealing material B
In the case of , C, and D, the cumulative content of the filler particle size is 2 μm or less is 3% or less, and in the case of B, C, and D, the cumulative content of particles whose cumulative content exceeds 3% is 2 μm or more. is A
The u-line curvature is 5% or less.
これに対し、サンプルＡの場合には、フィラー粒径２μ
ｍ以下の累積含有率が３重量％以上であり、Ａｕｉ曲り
率は１５％以上となり、成形性に問題を生じることがわ
かる。On the other hand, in the case of sample A, the filler particle size was 2μ
It can be seen that the cumulative content of m or less is 3% by weight or more, and the Au curvature is 15% or more, causing a problem in moldability.
（１）粒径２μｍ以下のフィラーの累積含有率が３％以
下であることにより、封止材の溶融粘度が増大しすぎて
成形性を低下させることを防止できる。(1) By setting the cumulative content of fillers with a particle size of 2 μm or less to 3% or less, it is possible to prevent the melt viscosity of the sealant from increasing too much and reducing moldability.
（２）前記（１）により、樹脂モールドによるワイヤ流
れやワイヤ曲り、それに起因するワイヤショート不良等
を防止できる。(2) According to the above (1), it is possible to prevent wire drift and bending due to the resin mold, and wire short defects caused by the wire bending.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で洋々変更可能
であることはいうまでもなＸ、論
たとえば、フィラーや樹脂の材料としては前記以外のも
のを用いることかできる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. For example, materials other than those mentioned above can be used as filler and resin materials.
図面のｆ？ｉ！ｉ ＊な説明
第１図は本発明による一実例である樹脂封止型半導体装
置における封止材中のフィラーの粒径とその含有率との
関係を示す図（フィラーの累積粒度分布図）、
第２図はフィラーの粒度分布とＡｕ線曲り率との関係を
示す図、
第３図は樹脂封止型半導体装置の一例を示す断面図であ
る。f in the drawing? i! i*Explanation FIG. 1 is a diagram showing the relationship between the particle size of filler in the encapsulating material and its content in a resin-encapsulated semiconductor device that is an example of the present invention (cumulative particle size distribution diagram of filler); FIG. 2 is a diagram showing the relationship between filler particle size distribution and Au wire curvature, and FIG. 3 is a cross-sectional view showing an example of a resin-sealed semiconductor device.
１・・・タブ、２・・・ベレット、３・・・インナーリ
ード、４・・・ワイヤ、５・・・封止材、６・・・アウ
ターリード、７・・・フィラー。DESCRIPTION OF SYMBOLS 1...Tab, 2...Bellet, 3...Inner lead, 4...Wire, 5...Sealing material, 6...Outer lead, 7...Filler.
第 １ 図 第 ２ 図Figure 1 Figure 2
Claims (1)
含有されるフィラーのうち、粒径２μｍ以下のフィラー
の累積含有率が３％以下である半導体装置。 ２、フィラーがシリカよりなることを特徴とする特許請
求の範囲第１項記載の半導体装置。[Scope of Claims] 1. A resin-sealed semiconductor device in which the cumulative content of filler with a particle size of 2 μm or less among the fillers contained in the resin encapsulation material is 3% or less. . 2. The semiconductor device according to claim 1, wherein the filler is made of silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15288184A JPS6132446A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15288184A JPS6132446A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6132446A true JPS6132446A (en) | 1986-02-15 |
Family
ID=15550156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15288184A Pending JPS6132446A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6132446A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2735283A1 (en) * | 1995-06-09 | 1996-12-13 | Solaic Sa | Heterogeneous resin packaging for IC |
| US5698904A (en) * | 1993-09-03 | 1997-12-16 | Rohm Co., Ltd. | Packaging material for electronic components |
| JPH1067883A (en) * | 1996-08-29 | 1998-03-10 | Mitsubishi Electric Corp | Inorganic filler, epoxy resin composition, and semiconductor device |
-
1984
- 1984-07-25 JP JP15288184A patent/JPS6132446A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5698904A (en) * | 1993-09-03 | 1997-12-16 | Rohm Co., Ltd. | Packaging material for electronic components |
| FR2735283A1 (en) * | 1995-06-09 | 1996-12-13 | Solaic Sa | Heterogeneous resin packaging for IC |
| JPH1067883A (en) * | 1996-08-29 | 1998-03-10 | Mitsubishi Electric Corp | Inorganic filler, epoxy resin composition, and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6297546B1 (en) | Underfill coating for LOC package | |
| US5773878A (en) | IC packaging lead frame for reducing chip stress and deformation | |
| US6661102B1 (en) | Semiconductor packaging apparatus for controlling die attach fillet height to reduce die shear stress | |
| JP2699517B2 (en) | Semiconductor device having round or tapered edges and corners | |
| JPS6132446A (en) | Semiconductor device | |
| JPH0547979A (en) | Resin-sealed semiconductor device | |
| JPH08264569A (en) | Method for manufacturing resin-sealed semiconductor device | |
| JPS61236130A (en) | semiconductor equipment | |
| JP2003031848A (en) | Solid-state light emitting lamp and its manufacturing method | |
| US8252631B1 (en) | Method and apparatus for integrated circuit packages using materials with low melting point | |
| JPS6164145A (en) | Resin sealed semiconductor device | |
| JP2873009B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS62261161A (en) | Resin sealed semiconductor device | |
| JPH01243531A (en) | Semiconductor device | |
| US4832996A (en) | Semiconductor die for plastic encapsulation having an adhesion promoter | |
| US6384333B1 (en) | Underfill coating for LOC package | |
| JP3384259B2 (en) | Resin encapsulated semiconductor device | |
| JPH0693469B2 (en) | Resin-sealed semiconductor device | |
| JPS63104455A (en) | Filler for filling sealing resin and its manufacture | |
| JPH04196471A (en) | Semiconductor device | |
| JPH0312467B2 (en) | ||
| KR200292411Y1 (en) | Leadframe for Small Die Pad Package | |
| JPS5827326A (en) | Resin sealing method of ic chips | |
| JPS6053060A (en) | Semiconductor device and its manufacturing method | |
| JPH03265161A (en) | Resin-sealed semiconductor device |