JPS6130357B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitor memory in which each memory cell is composed of a MOS transistor and a capacitor.

Liquid crystal image displays, which can display images including halftones, have a liquid crystal sandwiched between a glass plate and a circuit board on which capacitor memory is formed by interconnecting switching elements and memory capacitors. It is something. This liquid crystal image display stores an analog voltage corresponding to the density of the pixel in the capacitor of each memory cell of the capacitor memory, and the liquid crystal of the part corresponding to each memory cell is activated according to the strength of the electric field generated by this analog voltage. It attempts to display an image by driving the device.

FIG. 1 is a block diagram of a memory cell portion of the conventional capacitor memory described above. As shown in the figure, memory cells 11, 11, . That is, each memory cell 11 has a MOS transistor 12 and a MOS transistor 12.
A capacitor 1 connected between the drain of the MOS transistor 12 and a reference potential point (ground potential point)
It is composed of 3. In order to store an analog voltage corresponding to the concentration of the pixel in each memory cell 11, m data buses B ₁ , B ₂ , B ₃ , ………Analog voltage is applied to B _n-1 and Bm, and each memory cell 11 is
n connected to the gate of MOS transistor 12
This is done by sequentially giving row addresses to the book's address buses A ₁ , A ₂ , . . . An. In other words, the above one address bus Ai (1≦i≦n)
m selected by the row address given to
In the m memory cells, the MOS transistor 12 is turned on, and each of the m data buses B ₁ , B ₂ ,
The analog voltages applied to B ₃ , B _n-1 , and Bm are supplied to each capacitor 13, and each capacitor 13 then stores the analog voltage.

However, in each memory cell 11, if one or both of address bus A and data bus B is disconnected or comes into contact with other wiring, the capacitor memory becomes a defective product. The occurrence of such defects is mainly caused by defects in the production mask and the adhesion of dust during the manufacturing stage. Now, if we assume that the probability of such a defect occurring is, for example, 0.5%, the defect rate of the capacitor memory when 5×5=25 memory cells 11 are provided is 1−(1−
0.005) ¹⁰ =0.059, or 5.9%, which is extremely high, and increases as the number of memory cells 11 increases.

As described above, conventional capacitor memories have the drawbacks of high defect rates and low manufacturing yields.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to prevent a decrease in yield due to defects in the production mask or dust adhering during the manufacturing stage. The purpose is to provide capacitor memory.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows the structure of a capacitor memory according to the present invention, in which only the memory cell portion is shown. In this memory cell section, as in the conventional case, memory cells 21, 21, 21, . Two MOS transistors 22A, 22a
and a capacitor 23 connected between this common drain connection point and a reference potential point (ground potential point). Then, the m memory cells 21, 21, . . . arranged in each horizontal row are
In, one MOS transistor 22A, 2
The gates of MOS transistors 2A, 2A, . . . or the gates of the other MOS transistors 22a, 22a, .
The common connection points of the gates 2A, 22A, . _. . are connected sequentially from the top in FIG.
The gate common connection points _of 2a, . In addition, the n memory cells 21 arranged in each vertical column,
In 21, . . . , the sources of one MOS transistor 22A, 22A, . . . or the sources of the other MOS transistors 22a, 22a, . The common source connection points of ... are data buses B ₁ , B ₂ , ...Bm of one of the two data buses, sequentially from the left in Fig. 2.
The source common connection points of the other MOS transistors 22a, 22a, . . . are connected to the data buses b ₁ , b ₂ , . ...connected to each bm.

That is, in the above embodiment device, each memory cell 2
Two charging paths for the internal capacitor 23 are provided. With this configuration, each capacitor memory can now be
When operating the MOS transistor 22A to store an analog voltage in the capacitor 23, the address bus Aj (1≦j
≦n) or when data bus Bj is disconnected or comes into contact with other wiring, address bus A ₁ ~ An
are switched to the address buses a ₁ to an, and the data buses B ₁ , B ₂ , ...... Bm are switched to the data buses b ₁ , b ₂ ,
. . .bm, and the other MOS transistors 22a, 22a, . . . are operated. Therefore, in this case, this capacitor memory is not defective. Here address bus A ₁ ~
An, a ₁ ~ an or data bus B ₁ , B ₂ , ......
Bm, b ₁ , b ₂ , ...... Assuming that the probability of bm breaking or contacting other wiring is 0.5%, as in the past, and the number of memory cells 21 is 5 x 5 = 25. The failure rate of capacitor memory is 1-(1-
0.005 ² ) ¹⁰ = 0.00025 or 0.025%. In other words, in this example, the defective rate is 1/1 compared to the conventional method.
230, which significantly improves the yield.

By the way, a new problem here is that each memory cell 21 has two MOS transistors 22A, 2.
By providing 2a, the chip size becomes larger. However, capacitor 23
requires a relatively large capacitance value of 2 to 10 PF, so the area it occupies is more than 200 μm.
The MOS transistors 22A, 22a only need to be about 20 to 30μ in size, and even if two MOS transistors are provided, the chip size will hardly increase compared to the conventional one.

Note that the present invention is not limited to the one embodiment described above; for example, in the embodiment described above, each memory cell is provided with two MOS transistors; however, this is not limited to two MOS transistors;
Of course, there may be more than one.

As explained above, according to the present invention, a plurality of MOS transistors are provided in each methyl cell, and the output terminals of the MOS transistors are connected in parallel, and one of the MOS transistors is operated to store data in the capacitor. By doing so, it is possible to provide a capacitor memory that can prevent a decrease in yield due to defects in the production mask or dust adhering during the manufacturing stage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional capacitor memory, and FIG. 2 is a block diagram of an embodiment of the present invention. 21...Memory cell, 22A, 22a...
MOS transistor, 23...capacitor, A ₁ ~
An, a ₁ ~an……address bus, B ₁ , B ₂ ,……
Bm, b ₁ , b ₂ ,...bm...data bus.

Claims (1)

[Claims] 1. Multiple systems of address buses and data buses,
A capacitor whose one end is connected to a reference potential, whose one end is commonly connected to the other end of this capacitor, whose other end is connected to each data bus of the plurality of systems, and whose gate is connected to each address bus of the plurality of systems. and a memory cell composed of a plurality of MOS transistors connected to the memory cell, and selectively uses one of each of the plurality of address buses and data buses to charge and discharge the capacitance. A capacitor memory characterized by being configured as follows.