JPS6130306B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an access processing method in a data processing system, and in particular, when determining the priority of access requests, an access request that is once selected and becomes unprocessable for some reason during the processing process is used. The present invention relates to an access processing method in which access requests that have already been accessed are allowed to participate again from the determination of priorities, and at that time, a high priority is given to prevent access requests that require a long access processing time from occurring.

TECHNICAL BACKGROUND FIG. 1 shows an example of the configuration of a data processing system to which the present invention is applied. In the figure, 1 and 2 are two central processing units CPU ₀ and CPU ₁ , and 3 and 4 are four channel processing units CHP ₀ to
CHP ₃ is omitted. Also, 5 is a pipelined memory control unit MCU, and 6 is a memory device.
MSU, 7 is, for example, a set associative type buffer memory BS, 8 is its directory,
9 is a priority determining circuit.

The MCU accepts requests for access to the MSU from each of CPU ₀ , CPU ₁ , and CHP ₀ to _{CHP 3} at any time, and executes storage control using a buffer method using the directory and BS. Further, when a plurality of access requests are received at the same time, the priority order determining circuit selects one access request according to a certain priority order determining logic and executes it.

As a priority determination method for each access request, the priority between CHP and CPU is set higher for CHP, and the priority between CPU and CPU is determined by the priority determination logic determined by the device. The priority is determined according to the priority of the loopback. The outline and problems are explained below.

When the MCU receives access requests from multiple CHPs and multiple CPUs, it determines their priorities and sequentially processes the selected access requests in a pipeline, but the method for determining priorities in the MCU is , First, in response to access requests from multiple CHPs,
A first priority determination is made between CHPs to select one access request and then
A second priority is determined between CHP access requests, multiple CPU access requests, and loopback access requests for reusing the pipeline, and one access request is selected. The selected access requests are sequentially submitted to the pipeline and processed.

At this time, the selected
A CHP access request may have its acquired priority invalidated (NULLIFY) as follows:

(1) In the second priority determination process, when an access request from loopback collides with an access request from loopback, the access request from loopback must be given priority in order to use the pipeline again, and CHP access Since the priority is set higher than the request, CHP access cannot take priority, and the priority obtained in the first priority determination is invalidated.

(2) In the second priority order determination, if the bank of the buffer memory BS used by the CHP access is busy due to another access being processed by the MCU in advance, or if the bank is busy due to control reasons. , when a condition prohibiting CHP access occurs, the priority obtained in the first priority determination becomes invalid.

(3) Obtained priority in the second priority determination
After a CHP access is entered into the pipeline, there is no data to be accessed in the buffer memory BS (battle NOT
FOUND), and if the number of buffer NOT FOUND accesses processed by the MCU in advance is the same as the number of main memory access ports, and the main memory is being accessed, the main memory access port becomes busy. After the timing of the pipeline identified as busy, subsequent pipeline processing is disabled (NULLIFY), and the CHP access is restarted from the first priority determination.

(4) Set associative buffer memory
In the BS, when the set conflict detection function determines that the set address of the buffer memory BS used by the preceding access is the same set address as the CHP access, a set match occurs and the access to the same set, that is, the CHP access, is determined to be a set match. prohibited,
Disable further pipeline processing and
Regarding CHP access, the first priority determination is started again.

If the invalidated CHP access request as described above conflicts with another CHP access request when the first priority is determined again, it should have been processed first. It is possible that that CHP access request of a CHP access request is lost by a subsequent CHP access. Therefore,
The CHP access request that came after overtaking the MCU
Due to the effect of being processed first, a problem arises in that the access processing time for CHP access requests that should have originally been processed in advance becomes even longer.

In addition, as another method, instead of resetting the CHP access whose priority was invalidated in the second priority determination from the first priority determination,
There is a way to hold the priority until the priority is determined. In this case, hardware is required to hold the access request whose priority has been invalidated, and to allow other subsequent CHP access requests to participate in the second priority determination or wait in the second priority determination. Control circuit hardware is required to allow CHP access to participate.

Purpose and Structure of the Invention The purpose of the present invention is to
When a CHP access request participates in the first priority determination, the priority is raised, and in this priority determination process, the priority is raised so that it does not lose to other CHP access requests, and once the priority is invalidated.
The purpose is to shorten the access processing time for CHP access requests as much as possible.

The present invention has a configuration for this purpose, in which access requests from a plurality of access requesting devices are processed by determining priorities, and when a plurality of access requests from the plurality of access requesting devices are simultaneously received, determines the priority order of the access requests, selects one access request from among them, gives priority and starts processing, and if it becomes impossible to continue processing midway through, the priority of the access request is invalidated. In an access processing device that is equipped with a means to return the access request to a state in which it is accepted and then re-determine the priority order, when the access request whose priority right has been invalidated is allowed to participate in the determination of the next priority order, the priority order The feature is that the access request is processed by raising the access request to a higher value and competing with other access requests at the time.

EXAMPLES OF THE INVENTION The present invention will be described in detail below using examples.

FIG. 2 shows a memory control device to which the present invention is applied.
This figure shows an example configuration of an MCU. Note that the figure shows only the circuit portions related to the present invention for convenience.

In the figure, 11 is a CHP port, and CHP ₀ to
Accepts address and control signals from CHP ₃ . 12 is a CHP selector, which will be described later.
Controlled by a priority determination circuit. 13 is
This is a CHP priority determination circuit, which first selects one REQ among the access request signals REQ from CHP ₀ to CHP ₃ , and then transmits the REQ signal of the selected channel (expressed as SCH) to other access request devices. Output to determine priority between. 13a is a status display table provided for each CHP, which displays the processing status of access requests of each CHP, the busy status of ports, etc. Note that details will be described later.

14 is a CPU port, which receives address and control signals from CPU ₀ , CPU ₁ , a selected channel SCH, and a loopback control circuit LB (not shown). Reference numeral 15 denotes a CPU selector, which is controlled by a main priority determining circuit, which will be described later.

16 is a main priority order determining circuit, which determines the priority order of the REQ signal for input targets CPU ₀ , CPU ₁ , SCH, and LB of the CPU selector 15 . 16a is a flag that indicates the priority order among CPUs. The signal output from circuit 16 to circuit 13 indicates that SCH has not been selected.

17 is a pipeline, and only stages T ₁ , T ₂ and T ₃ are shown. T ₁ V, T ₂ V, and T ₃ V are the variable signals of each stage.

Reference numeral 18 denotes a circuit having the aforementioned set conflict detection function. Reference numeral 19 denotes an invalidation control circuit that detects and invalidates a condition that makes it impossible to process an access request that has started execution. Reference numeral 20 denotes a prohibition gate, which inverts the valid signal and outputs a disable signal when the circuits 18 and 19 instruct that processing cannot be continued (NULLIFY).

As the basic ranking determination logic of the CHP priority determination circuit 13, any suitable method can be used, such as port number order, prespecified order, cyclic change method, etc. On the other hand, a means is added for raising the priority level in re-priority determination of an access request that once acquired priority but became invalid. Further, the order determining logic of the main priority order determining circuit 16 is two: following the order of CPU<SCH<LB, and following the display of the flag 16a for CPUs.

Next, the present invention is characterized by:
Regarding the control method of priority determination processing for priority invalid access requests in the CHP priority determination circuit 13, based on the configuration diagram in FIG.
This will be explained in detail with reference to FIGS. 5 to 5.

FIG. 3 shows a configuration example of a status display table 13a provided for managing access requests of each CHP. The first bit displays "1" when an access request is issued (REQUEST). The second bit indicates that one access request has been accepted and priority determination processing and pipeline processing are in progress, and that the CHP port 11 is busy (PORT BUSY). The 3rd to 6th bits are status codes that indicate the control status during priority determination processing and pipeline processing at ports regarding accepted access requests (ACCEPTED 0, 1, 2,
3).

Figure 4 shows status display table 1 shown in Figure 3.
3a is a state transition diagram consisting of nine states in total.

First, it is in the reset state of [000000],
When access request REQ is accepted [100000]
Move to. Here, the first stage priority determination process is performed in the CHP priority determination circuit 13, and when the priority is acquired here, that is, when the access request is selected, the process moves to (P) [110110], and on the other hand, when the access request is not selected, At time(), it waits in the state of [110000] until it is selected.

The CHP access request selected in the CHP priority determination circuit 13 then participates in the second stage of priority determination processing in the main priority determination circuit 16, and when selected here (POK), the CHP access request is [110101] When it is executed (EXEC), it moves to [100100]. Next access request after execution ends
If the REQ is accepted, it returns to [100000], and on the other hand, if there is no next access request (), it returns to [000000].

However, if the CHP access request is not selected in the second stage of processing (),
Move to [111011], where it is given higher priority. Therefore, it is selected from the first stage (P
(High)), [111111] and undergoes the second stage processing again. If selected here (POK),
The program moves to [110101] and is executed. However, if it is not selected, return to (), [111011], restart from the selection operation in the first step, and repeat the operation (POK) until it is selected in the second step.

On the other hand, when entering execution (EXEC) from [110101], if the CHP access request becomes impossible to execute (), it moves to [111010] and is given a high priority (P (HIGH)) in the first stage. to select it and move on to the second step [111111]. The following is the same as the previous case.

Also, if access requests from three or more CHPs exist in the MCU at the same time, and each access request cannot continue processing (NULLIFY), the first
When a situation arises in which it is necessary to repeatedly determine the priorities of the stages, two access requests with high priorities (P (HIGH)) compete with each other, and one of them is not selected (
(HIGH)), but in the next cycle, the high priority given to the unselected access request remains (P(HIGH)), so it is selected (P(HISH)) and the second undergo stage treatment. The above state transitions are shown in Figure 3 when it is not selected from [111010] and moves to [111011] (()), and when it is not selected from [111011] and remains at [111011] (()). It can be done.

In this way, even if priority is lost after the second stage priority determination process, control can be performed so that the priority is immediately selected when returning to the first stage.

FIG. 5 is a timing diagram of an operation example showing logical conditions for generating the state transition of the state display table shown in FIG. 4 and control contents based on the generated state display.

In FIG. 5, a indicates the clock period, and E
-E is the CHP clock cycle. The clock period of the CPU and MCU is 1/2 between E and E.
It is becoming. b is port busy (PORT
BUSY) period, c is the port busy period inside the MCU, d is the existence period of the access request REQ, and e is the priority P or P given in the first stage.
(HIGH), f to g indicate status display codes. The solid line portion represents "1" and the blank portion represents "0".

Further, j indicates the processing result of the first stage CHP priority determination circuit 13, and SEL REQ indicates that REQ has been selected. k represents the processing result CPU-P of the second stage main priority order determining circuit 16. A dotted line indicates a negative result, and a solid line indicates a positive result. and l
indicates the presence or absence of the output signal POK, m
indicates the operating status of the pipeline according to the result. n exemplarily indicates the correspondence with FIG. 4.

The zero marks in the figure represent input logic conditions for activating control operations, and the control operations activated as a result of vertically connecting and combining these conditions are indicated by arrows. For example, REQ="1", P=
“1”, ACPTD 0 = “0”, ACPTD 1 = “0” input condition outputs [SEL REQ], and at the same time
This indicates that ACPTD1 and 2 are set to "1". Then, SEL REQ="1" and CPU
-P=“0”, that is, a signal is generated from non-selection in the second stage, and the status code [1011] is further generated from the status code [0110]. The following shows that it becomes unexecutable at the _T3 stage of the pipeline, generates a signal, and rewrites the status code to [1010].

Effects of the Invention As described above, according to the present invention, a CHP access request that once acquired priority but lost it midway through for some reason is given priority over other CHP access requests in re-prioritization. By providing suitable conditions, the chances of re-execution increase and processing can be made smoother.

[Brief explanation of the drawing]

Figure 1 is a typical configuration example of a data processing system, Figure 2 is a configuration diagram of a memory control device according to an embodiment, Figure 3 is an explanatory diagram of a status display table, and Figure 4 is an illustration of a status display table. FIG. 5 is a state transition diagram of CHP priority determination control and a timing diagram of an operation example. In the figure, 11 is a CHP port, 12 is a CHP selector, 13 is a CHP priority determination circuit, and 14 is a CPU
15 is a CPU selector, 16 is a main priority determining circuit, 16a is a flag indicating priority among CPUs, and 17 is a pipeline.

Claims (1)

[Claims] 1 Prioritize and process access requests from multiple access requesting devices, and when multiple access requests from the multiple access requesting devices are received at the same time, determine their priority and process them. If one access request is selected from among them, given priority, and processing is started, and it becomes impossible to continue the processing midway through, the priority of the access request is invalidated and the access request is returned to the state where the access request is accepted. Therefore, in an access processing device equipped with a means to re-determine the priority order, if the access request whose priority rights have been invalidated is to participate in the determination of the next priority order, the priority order is increased and the other access requests at that time are An access processing method characterized in that processing is performed in competition with access requests.