JPS61296420A - Electronic calculator - Google Patents

Abstract

PURPOSE:To prevent a key common signal from the reduction of voltage and to remove miskeying by generating key reading timing during the generation of a blanking time signal and generating display timing during the time of no generation. CONSTITUTION:At the display timing and key scanning timing, a CPU 1 outputs digit signals D1-Dn successively. A blanking time generating circuit 4 generates a blanking time signal A by output of the signal D1 to turn off a transistor (Tr) 6, generate a delay signal B from a delay circuit 7 and apply the delay signal B to a latch 8. Therefore, a fluorescent display tube 21 displays no picture during the period. The latch 8 latches a key output signal to be applied a line input terminal 31 and applies the latched signal to the CPU 1. The CPU 1 executes key processing at the existence of the key output, and when there is no key output, outputs signals VF1, VF2 from a DC/DC converter 9 and displays the outputted signals VF1, VF2 on the display tube 21 during the residual period (display period) of the signal D1. Thereafter, the signals D2-Dn are similarly and successively processed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a small electronic calculator that uses both a display digit signal for a display device using a fluorescent display tube and a key common signal for a key matrix circuit of a key input device. It is.

[Prior Art] Generally, in a small 1tf calculator equipped with a fluorescent display tube, the display digit signal (signal applied to the grid electrode plate) supplied to the fluorescent display tube and the key common signal are used together, and the PIN of the LSI is The number can now be reduced.

When using the above-mentioned display digit signal and key common signal together, in order to prevent double display between digits on the display, blanking time should be obtained between adjacent display digit signals by software processing. It will be done.

In other words, a blanking time is created using the display digit signal, and while the display is being displayed on the fluorescent display tube, the LSI
At this point, input key processing is performed.

In the display device as described above, a voltage is constantly applied to the cando electrode (filament), and when a display digit signal is applied to the grid electrode, a plurality of plates provided corresponding to the grid electrode Display is achieved by applying appropriate signals to the electrodes. In this case, the display digit signal is applied sequentially to the grid electrodes of the fluorescent display tube provided for each digit.

[Problems with the prior art] As mentioned above, key sampling is performed at the same timing as the display operation in the fluorescent display tube using a signal that uses both the display digit signal and the key common signal. Because a large current (about several mA to 10 A) flows through the terminal, the voltage of the key common signal decreases, and the key input signal falls below the reading level of the LSI, and the LSI may not be able to read the key input signal. . Furthermore, even when a display operation is not being performed, when the display digit signal (VGND) is applied to the grid electrode, the grid electrode and cando electrode (filament)
(-30V), a discharge occurs due to the potential difference between
The voltage of the key common signal may drop. Furthermore, if different types of common keys on the same key input line are pressed at the same time, the display digit current will double, the voltage of the key common signal will drop significantly, and even though key input has been made, the key In order to avoid chattering when it is determined that there is no input, when one key is released from being pressed at the same time and becomes a single key, it is considered a new input even if that single key is a continuous operation of the previously operated key. There have been times when I have been

In particular, the above-mentioned drawbacks occur when a large fluorescent display tube is used, and from the above, special LSI
There were also problems in that it became necessary to use a fluorescent display tube or to limit the size of the fluorescent display tube.

Furthermore, a method to compensate for the above-mentioned drawbacks by outputting the display digit signal and the key common signal from separate terminals may be considered.
In that case, there is a problem that the number of LSI bins increases.

[Purpose of the invention] When the key common signal and the display digit signal are used together, it is possible to prevent the voltage of the key common signal from dropping, thereby preventing key input errors, and it is possible to use a conventional ordinary LSI, and the fluorescent display It is an object of the present invention to provide a small-sized electronic calculator that does not impose any restrictions on the size of the tube and does not require any increase in the number of PINs of the LSI.

[Key Points of the Invention J] When the above key common signal and display digit signal are used together, a blanking time signal is generated that turns off the display operation for the selected digit while each digit for the above display method is selected by the above combination signal. The key point is that the key read timing for the key input device is determined while the blanking time signal is being generated, and the display timing for the display method is determined while the blanking time signal is being displayed.

[Example] Hereinafter, a small model according to the present invention will be described with reference to the drawings. ! ! An example of an electronic calculator will be described.

In FIG. 1, CPUI is a well-known circuit that controls all operations of a small electronic computer, and is composed of a microprocessor and the like. Then, the digit signals D1 to Dn are outputted and displayed on the fluorescent display tubes 21 to 21 of the corresponding display digits of the display device 2.
? It is applied as a display digit signal to the n grid electrodes and is also supplied as a common signal to the corresponding row input terminals 31 to 3n of the key matrix circuit of the key input device 3. Furthermore, the digit signal is also supplied to a blanking time generation circuit 4 and outputted for a predetermined period of time.
A blanking time signal A, which is an emission signal, is created.

In other words, as seen in the time chart of FIG. 2, the digit signals D1 to Dn are not provided with the conventional blanking time period, but have waveforms that are sequentially output.

Further, the CPUI supplies segment signals P1 to P1 to the plate electrodes of each fluorescent display tube of the display device 2 to display necessary information.

On the other hand, the blanking time signal A output from the blanking time signal generation circuit 4 is passed through the inverter 5 to the NP
In addition to being applied to the base of the N-type transistor 6, the signal B shown in FIG. 2, which is applied to the delay circuit 7 and delayed by a predetermined time, is outputted and supplied to the latch 8 as a latch signal. At this time, the latch 8 latches the key output @ sign (in the illustrated example, 4-bit parallel data) from the key input device 3, and supplies it to cptyi to perform key input processing.

A signal output from the DC1rJC converter 9 is input to the collector of the transistor 6, and the output of the emitter is input to the DC:/IIC converter 9 as a signal VS, and the signal output from the DC:/DC: converter 9 (AC Current) Controls the output status of VFI and VF2. That is, the signal VF1. VF2 is QND when the signal VS is "H level"
(“H” level), and when it is 'L' level -30 yen
(-is output at “L” level, and signals VFI, V
F2 is supplied to the cathode electrode of each fluorescent display tube.

Next, the operation will be explained with reference to FIGS. 2 and 3. C.P.
As shown in Figure 3, the UI uses digit signals D1 to D at display timing and key scan timing.
Output n sequentially and display it in response method 2 of display bag a12.
+"2++ and also to the corresponding 31 to 3n of the key input device 3. Then, at the start of this display timing and key scan timing, the CPU clears the Yl/ register (not shown) in step A, and then this A digit signal D1 is output for the O-th digit (first fold) (step A2, At).

Therefore, this digit signal DI is
The grid electrodes and digit input terminals 31 are applied to the blanking time generation circuit 4, respectively. As a result, the blanking time generation circuit 4 generates the blanking time signal A as a single signal that is output for a predetermined period of time, and applies it to the base of the transistor 60 via the inverter 5 to turn off the transistor 6 and also to the delay circuit. A blanking time signal A is also applied to the delay circuit 7 to generate a delay signal B from the delay circuit 7, and the delayed signal B is applied to the latch 8.

Therefore, during this off period of the transistor 6, the signal Vs+f"
The signals VF1 and VF2 are supplied to the DC/DC converter 9 from the DC/DC converter 9 at the G level.
It is output as ND (“H” level). Therefore, during this period, the fluorescent display tube 21 is in the display timing off state and nothing is displayed.

On the other hand, during the off period of this display timing, the latch 8 latches a 4-bit parallel key output signal to the row input terminal 31 (step A4) and supplies it to the CPU 1. Therefore, the CPU determines the presence or absence of an operation key from the key output signal (step As), and if the key is present, performs the key processing and returns to step A1 (step A6).
However, if the key is not present, the process proceeds to step A1, and after the blanking time signal A goes to the "L" level, the signal VS is set to the "L" level by the ON operation of the transistor 6, and therefore the output from the DC/DC converter 9 is Signal VFI
, output VF2 as -30■ (“L” level),
causing the fluorescent display tube 2I to perform a display operation during the remaining period of the digit signal Dl, that is, during the ON period of the display timing;
The deshift signal D1 is turned off and set to "L".

Next, in step A8, the Y register is increased by 1 to designate the second digit, and the digit signal D2 is output as "H". Further, in step A9, the CPU 1 determines whether the data in the Y register has become n, and since it is YES, step A? The process proceeds to key input processing for the row input terminal 32, and during that period, the display timing for the fluorescent display tube 22 is turned off, and then, when the key input processing is completed, the display timing for the fluorescent display tube 2z is turned on and the display is started. perform an action. That is, steps A2 to A9 described above are executed.

After that, step A2~ is performed similarly for the 3rd digit~nth digit.
Execute A9 and when the nth digit is completed, Y in step A9
Since the result is ES, the process returns to step A1, and the next key input process and display process for the first digit are executed.

[Effects of the Invention] As explained above, the present invention provides the following advantages: - When the key common signal and the display digit signal are used together, the display operation for the selection technique is performed while each digit on the display device is selected by the combination signal. This display method generates blanking time 0, which turns off the blanking time, and sets the key lead timing for the key input device during the blanking time, and sets the display timing during the blanking period, so the key common signal and the display digit signal When used together, it is possible to prevent the voltage of the key common signal from dropping, which also prevents key input errors.Also, conventional LSI can be used, and there is no restriction on the size of the fluorescent display tube.
Furthermore, there are advantages such as being able to provide a compact electronic meter that does not require any increase in the number of PINs on the LSI.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart, and FIG. 3 is a flow chart of display and -t-1 input processing. 1...CPU, 2...Display device, 21
~2. ...... Fluorescent display tube, 3... Key input device δ, 4... Blanking time generation circuit,
6...Transistor, 7...Delay circuit, 8...Latch, 9...DC/DC converter.

Claims (1)

[Claims] In a small electronic calculator that uses both a display digit signal for a display device using a fluorescent display tube and a key common signal for a key matrix circuit of a key input device, while each digit for the display device is selected by the combined signal. a blanking time generation circuit that generates a blanking time signal that turns off the display operation for the selected digit; and this blanking time generation circuit that controls the key read timing for the key input device while the blanking time signal is being generated. 1. A small electronic calculator characterized by comprising a means for generating.