JPS6129463A - Rotary head type recording and reproducing device - Google Patents

Abstract

PURPOSE:To ensure sufficient burst error correcting length and to cope with both channel independence and non-state by switching whether or not a channel is independently in use depending on the switching of a RAM address with a channel independent control signal. CONSTITUTION:A stereophonic audio signal fed to input terminals 11a, 11b is given to an A/D converter 13 alternately by a switch 12 and converted into a PCM signal of 1 word 16 bits. The signal is divided into high/low-order 2-symbol at each 8 bits at each revolution of a drum 31 via a switch 14 and written on RAMs 15, 16. The arrangement in the RAM written in this case is controlled by a circuit 23 and selector switches 25, 26 are switched alternately in synchronization with the switch 14. A half of the PCM signal fetched to the RAM16 is coded at the next period and the remaining half is coded at the period next to the next period, a required information symbol is read by a coding address control circuit 21 and fed to a coding circuit 19 via switches 17, 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a rotary head type recording and reproducing apparatus that records and reproduces digital signals on a recording medium using a rotary head.

[Prior art]

2. Description of the Related Art There is a device that converts an information signal such as a general audio signal into a PCM and records and reproduces it on a magnetic tape using a rotary head. In such a device, when recording, P
The commercialized audio signal is temporarily held in memory, error correction and detection codes are generated and added, and during playback, the data is stored in memory in the same arrangement as during recording, and then error correction is performed. Here, the two-channel audio signals of the L channel and the R channel sampled with a quantization bit number of 16 bits using a sampling frequency of 48.0 KHz are processed by two heads installed on a drum rotating at a rotation speed of 200 rpm. Let us consider the case of recording and reproducing information on magnetic tape.

FIG. 1 shows an example of a data arrangement when encoding and decoding is performed by such a device, and Lou in the figure
(LOIl) is the L channel, the subscript number is the sampling order, and U is the upper symbol (β is the lower symbol) when the 16-bit word is divided into upper and lower 8 bits. There is. Further, P and Q represent areas of the P check symbol and Q check symbol, respectively, and PO to P3 and QO-Qll represent the check symbols.

When the sampling frequency is 48.0 KHz, the samples generated per second are 2 channels and 96,000 words, and the trunk on the magnetic tape is (2,000 words per second).
x 2 ) /60=66.6...Since this is formed, one track has 96000/66.66...=
Information symbols of 1440 words, ie 2880 symbols (one word is divided into an upper symbol and a lower symbol) will be written. Here, 5760 information symbols corresponding to two tracks are sequentially stored in the memory in a data arrangement as shown in FIG. As a result, four AXCXK cubes of A=4 symbols, C=13 symbols, and 28 symbols are created. At this time, there is a surplus information symbol area for 16 symbols per cube, and a dummy symbol with a value of 0, for example, is inserted there.

The symbols belonging to these four cubes are the even-numbered and odd-numbered sample groups of the L channel, respectively.

It is in a state where it is divided into even-numbered and odd-numbered sample groups of the R channel.

For the information symbols arranged in this way, J (=4) check symbols are generated and added to the 28 information symbols in the y direction, and D is added to the 26 information symbols in the X direction. (=6) Symbol check symbol is generated.

B = 32 symbols, M = 32 symbols in total.
As a result, a cube of (BXMX2A) is completed.

When recording on a tape, the data of the (BXMXA) symbol is treated as one track's worth of data, and as shown in Figure 1', it is divided into an even sample group of the L channel and a group of odd samples of the R channel, with a group of Q check symbols in between. are recorded in one trunk in blocks, and in the adjacent track, the even number samples of the R channel and the odd number samples of the L channel are recorded in blocks, and the samples of the same channel are recorded in the tape width between the two trunks. Record in such a way that it moves away from you.

The advantage of recording in such a pattern is that even if one track's data is lost due to a clogged head, the average value can be corrected using the data of the other paired track. Even if data on half of the tracks (strictly speaking, half of the information symbols and all of the Q check symbols) is missing continuously, the average value can be corrected using the data on the other half of the tracks.

By the way, in the above-mentioned recording device, although the L channel and R channel PCM data recording areas are separated within the track on the tape, it is possible to record 20M data of only the L channel or only the R channel during after-recording, etc. Practical inconveniences arise when re-recording or the like. That is, since the Q check symbol is generated across the information signals of both the L channel and the R channel, the Q check symbol is newly generated from both the information signal of the channel that is not rewritten and the information 1 signal of the channel that is newly recorded. It is necessary to re-record the PCM, and if the new recording area is shifted in the track scanning direction, the PCM must be retained.
There is a possibility that new PCM data may be recorded on top of the data.

Therefore, a proposal as shown in FIG. 2 has been made.

FIG. 2 shows the trunk formation pattern on the tape. In the figure, 2 is the tape running direction, 3 is the track scanning direction, and 4 is generated from the L channel information 1 information signal and the L channel information signal, for example. The area 5 in which the check code is recorded is, for example, the information signal of the R channel and the R channel.
Area where check codes generated from channel information signals are recorded; 6 indicates P recorded in recording areas 4 and 5;
This is a guard space in which signals other than CM data are recorded.

In the configuration shown in Fig. 2, error correction encoding and decoding are completed within each channel. If it is ensured that the direction is greater than the deviation, it is easy to rewrite only the L channel or only the R channel. However, a drawback of such a configuration is that the error correction ability is low. That is, since the code is completed in a short area within the trunk, the burst error correction ability in the track scanning direction is inevitably low.

By the way, if you think about the usage of such recording and playback devices, it is generally not very common to use channels independently, such as when performing after-recording. In this case, it is inappropriate for the error correction ability to be in a low state as described above.

Therefore, there has been a demand for a device that can easily select between the L and R channels using a control signal indicating whether to use them independently, and that can also ensure sufficient correction capability.

[Summary of the invention]

The present invention has been made in view of the above, and provides a rotary head type recording/reproducing device for recording K, L channel, and R channel information signals separately with a guard space in between, for performing after-recording, etc. , the RAM during encoding and decoding is switched by a channel independent control signal to switch whether or not to use the channel independently.
To provide a rotary head type recording/reproducing device capable of dealing with both channel independent and non-channel independent cases with a simple device configuration by switching only addresses, and ensuring sufficient burst error correction length in each case. It is.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, an example of data arrangement when encoding and decoding is performed in the rotary head type recording/reproducing apparatus of the present invention is shown in FIG. We will explain how to do this.

First, when recording, 5760 tracks should be recorded on 2 tracks.
Symbol information symbols are loaded into the RAM for each channel in the order of the subscripts in the figure. In this example, E
= 26 symbols, to = 28 symbols.

N=2 symbols are arranged in four (26x28x2) symbol cubes.

Now, if we consider the case where the L channel and R channel are used independently (or in a normal state (no after-recording, etc.)), Q encoding is first performed in the X direction.

At this time, the error correction code is a Reed-Solomon code (RS) on a Galois field GF (28) with high correction ability.
C) is used. Here, n is the code length, k is the information length, and d
If is the minimum distance, then (n, k, d) = (60
, 52, 9) is used. For example, [LOu
t L4u, L8u, "'.

L48u, Rlu, R5u, R9u,
-, R49u ], check symbols [QO, Ql, Q2 . Q3
．． Q4. Q5. Q6°Q7 ] is generated to satisfy the following equation.

V= [LOu, L4u +...+ L48u
+QOI・l Q3. Rlu, R5u, -
.

R49u, Q4. -, Q7] -(1)...
(2) π1 ・vT−o ・
(3) Here, α is a root that satisfies f (X) −0 for the irreducible polynomial f (x) on CF (28). Further, T means a transposed matrix.

By the Q encoding described above, F=4 symbols (2Fx
Q check symbols of Kx2N) = (8X28x4) symbols are generated, and then (32, 28, 5
) P is encoded by R3C.

For example, check symbol [PO, Pl, P2゜P3]
is generated to satisfy the following equation.

U= [LOII, Lol, Ls2u+・+L
? 28u, L7281, PO.

PI, P2. P3 code...(4) π2 ・'ffT-0...(6) By such P encoding, as J-4 symbol (
GxJx2N) - (60x4x4) symbols of P check symbols are generated, totaling (GxMx 2N)
= A cube of (60x32.x 4) symbols is created.

Next, when considering encoding when each R channel is used independently in after recording, etc., first, 26 information symbols in the X direction and 26 information symbols adjacent to them in the two directions, a total of 5 information symbols, are used.
Eight Q-check symbols are generated for two information symbols. In other words, the generator matrix ``is (
Similar to equation 2), for example, the following equation (Q9, QIO, Qll) is generated for even samples of the R channel.

¥:= [LOu, L4u, +・+, L4B
u, QO.

Q3, L2u, L6u, ++.

L50u, QB, ..., Qll] - (7
1π1 ・YT−0...(8) For odd samples of the R channel, for example, 'i' = [Rlu, R5u, -, R49u, Q4
．． ....

Q7 + R3u+ R7u, -+ R51u *Q
12. ..., Q15] ... (9) Kl-VT=0
...Q check symbol [Q4. Q5, Q6, Q7
, Q12, Q13, Q14, Q15]. In this way, (8×28×4) symbols of Q check symbols are generated. Also, P encoding is described above &
This is done in the same way as when L and R are not independent.

When recording data encoded in this way, one frame consists of 32 information symbols and check symbols in the y direction, and a synchronization signal is placed at the beginning of each frame, regardless of whether L and R are independent or not. and the frame address signal, (x +2) becomes (0, O), (0,
1>, (1, 0), (1, 1), etc. transmit GXM×N data for each frame sequentially at addresses 1
form a book track, then (x, z) becomes (0,2)
, (0,3), (1°2), (1,3),
The remaining GXMXN data is transmitted at the address . . . to form another trunk. At this time, after recording the first half (E + F)XMXN data for each track, a guard space 6 as shown in Fig. 2 is formed.
Record the remaining data.

Next, during reproduction, the reproduced PCM signal is stored in the RAM with reference to the frame address signal, and the data is arranged as shown in FIG.

For decoding, P decoding is first performed in the y direction using the following procedure.

(1) Syndrome So, Sl, S2. S3 calculation Here, “゛” is the received data sequence, 100-(eo.

If el, .

""="+100= [LOu + eO+ LOj! + el +-
, P3 + e31] ... (12) (ii) Calculation of error position and error value (iii) @ correction and addition of error pointer If at least one of the syndromes is not O, there is an error in the received data Therefore, find the error position and its value from the syndrome. Although up to two errors can be corrected in Pfjj, the method is not the subject of the present invention and will not be discussed here.

Also, depending on the result of P decoding, an error pointer is stored in a separately provided register or RAM on a frame-by-frame basis. For example, if two or more entertainments are detected, move the pointer “
1” so that it can be used in the next stage of Q decoding.

Next, Q decoding is performed, but the procedure at this time is basically P
It is the same as decoding, and the syndrome is from SO to 8 up to S7.
The difference is that the pointer of the P decoding result can be used for correction.

In this case, the received data sequence when calculating the syndrome differs depending on whether L and R are used independently;
In other words, if R is not independent, for example, when performing after recording, etc.
For example, when the R channel is independent. Here, V' = V + 100... (15) x
−x+e (16). In Q decoding, there are many error correction algorithms, and although they will not be described in detail, it is possible to correct up to eight erasure errors (errors with pointers in P decoding) or four errors with unknown locations.

The information symbols subjected to error correction in P decoding and Q decoding in this manner are read out in the order of the subscripts in FIG. 3.

Note that although the above embodiment describes a method in which encoding is performed in a circuit separate from decoding, decoding can also be performed using a decoding circuit.

That is, when decoding, put a pseudo (pointer) at the position of the Q check symbol in the K, (υ equation), and decode as 8 erasure error corrections to obtain the required 8 check symbols.

As mentioned above, in the encoding and decoding method of the apparatus of the present invention, the generator matrix πl is common during Q encoding, but when the L and R channels are used independently, the Q code is used in each channel. If the L and R channels are not independent, the Q code is applied across both R channels, and coding is performed so that the data is completed within one track. By doing so, the maximum burst error correction length in the track scanning direction can always be ensured. In other words, if the channels are not independent, the PC shown in FIG.
Up to a burst error in the track scanning direction of approximately 1/8 of the M data recording areas 4 and 5, or in the track scanning direction of approximately 1/8 of the respective area length in each area 4 and 5 when channels are independent. Even burst errors can be corrected.

In this example, a code with simple error correction capability is used as the P code, but it may also be a code with only error detection capability, such as a CRCC (cyclic code). It also shows the data arrangement, code length, and number of check symbols, N, K, J,
The values of E, F, etc. are not fixed.

Next, the configuration and operation of a rotary head type recording/reproducing apparatus using the encoding and decoding methods described above will be explained.

FIG. 4 is a block diagram of a recording system of a rotary head type PCM audio magnetic recording and reproducing apparatus which is an embodiment of the present invention. In the figure, lla and 11b are L channel and R channel analog audio signal input terminals, 12 is a channel selection switch, and 13 is an analog audio signal input terminal.
A digital (A/D) converter 14 is a RAM selection switch for recording/writing signals;
Together with this, it constitutes symbol generation means. 15 and 1
6 is a first RAM and a second RAM, respectively; 17 is a RAM selection switch during encoding and reading; 18 is a switch for switching data flow during encoding and reading; 19 is an encoding circuit; 20 is a read RAM address control circuit; 21 2 is an encoded address control circuit (first and second memory addressing means); 22 is a channel independent control signal input terminal;
3 is a write address control circuit (symbol block creation means), 24 is a read RAM address and encoding address selection switch, and 25 and 26 are first RAMIs, respectively.
5. A selection switch for selecting a write RAM address and a read or encoded RAM address of the second RAM 16, 27 a frame address addition circuit, 28 a modulation circuit, 29 a recording amplifier, 30 a head selection switch,
31 is a rotating drum, 32a and 32b are heads, and 33 is a timing control circuit.

FIG. 7 shows a part of the specific configuration of the encoded address control circuit 21. In the figure, 71 is a frame clock input terminal, 72 is a symbol clock input terminal, 73 is a frame address counter, and 74 is a frame clock input terminal. Symbol address counter, 75 is ROM, 76 is mod 128
Adder for decoding, 77 is frame address output terminal, 78
is the symbol address output terminal.

Next, the operation will be explained with reference to the recording system timing diagram shown in FIG. Here, ta) and (bl in the same figure indicate the recording waveforms of the heads 32a and 32b, respectively, and (C1,
(d) is the second. This shows the operation of the first RAM 16.1'5. Further, in the figure, T indicates a period during which the head rotates 90 degrees.

The stereo audio signals supplied to the input terminals 11a and llb are alternately switched between m A /
The signal is applied to the D converter 13. A/D converter 13
So the sampling frequency per channel is 48.0K.
PCM of 16 words sampled at Hz
converted into a signal. This PCM signal is LO, RO, Ll
, R1, . . . sequentially through the switch 14 to the first RAM
15 or the second RAM 16. The switch 14 is switched by a 16°67) 1z signal synchronized with the rotation of the drum 31 from the timing control circuit 33, and the fifth
As shown in Figure (C1, (dl), the above-mentioned PRAM 15 and the second RAM 16 are alternately
A CM signal is supplied, and the PCM signal is divided into upper and lower two symbols of 8 bits each and sent to the first RAM 15 or the second R.
Written to AM16. At this time, the arrangement of the information symbols in the RAM to be written is controlled by the write address control circuit 23, and therefore the address selection switches 25 and 26 are alternately switched in synchronization with the switch 14.

A PC incorporated into one RAM, for example, the second RAM 16
As shown in FIG. 5(0), the M signal is encoded with K, half of which is encoded during the initial period K of the next T, and the remaining half of which is encoded during the next T period. At this time, the necessary information symbols in the RAM are read out by the encoding address control circuit 21 and supplied to the encoding circuit 19 via the switches 17 and 18. The check symbol generated by the encoding circuit 19 is again written to the second RAML6 via the switches 17 and 18.

Figure 6 shows a specific RAM that corresponds to the data array in Figure 3.
This figure shows only the RAM configuration corresponding to one track, so the first RAM 15 and the second RAM 16 each correspond to two RAMs shown in FIG.
It has twice the capacity. That is, FIG. 6 shows only the (GXMXN) part of the data array in FIG. 3, and this much information is encoded in the period T. Figure 5 (
Of the 5760 information symbols generated during the 4T data writing period in C), the 1440 information symbols of the even sample group of the L channel and the 1440 information symbols of the odd sample group of the R channel are the 6th information symbol.
It is located in the RAM shown in the figure. L143B, R1439
The subsequent O symbols are the aforementioned dummy symbols.

In the case of Q encoding in the encoding circuit 19, a frame clock of 60 clocks is input from the timing control circuit 33 to the terminal 71 of the encoding address control circuit 21, the counter 73 counts and amplifies this, and the output is sent to the ROM 75. is supplied to the lower six bits of the address and the adder 76, and the adder 76 adds this to the output of the ROM 75. A symbol clock of one clock is inputted to the terminal 72 from the timing control circuit 33 every 6° frame clock, and the counter 73 is reset and the counter 74 is counted and amplified. Of the output of the counter 74, only the least significant one bit is connected to the address of the ROM 75, and the most significant five bits are outputted from the terminal 78 as a symbol address. A channel independent control signal generated by a control signal generating means (not shown) is inputted from the terminal 22 to one bit of the most significant address of the ROM 75. As this channel independent control signal, "O" is input when the present recording apparatus is used as a channel independent control signal, and "1" is input otherwise. ROM75
The output of 1 is specified by the ROM content diagram shown in Figure 8.
．． The frame address output terminal 77 is provided by adding the 6 bits of the lower address of the counter 73 and the output bit of the ROM (
IIIOd128) The value is output.

For example, in the case of channel independent use, the frame address is 0.2, 4,..., 50.1, 3, 5°...
, 51, the required information symbols are read out and supplied to the encoding circuit 19, and the check symbols of the even-numbered sample group of the L channel generated thereby are assigned frame addresses 52, 53, . . . , 59. Then, the lowest value 1 of the output of the counter 74
When the bit becomes “1”, the frame address is 6.
0,62. .

64,..., 110.61.63. ..., 11
1, the required information symbol is read out and supplied to the encoding circuit 19, and the check symbol of the odd sample group of the R channel thus generated is assigned to the frame address 112.K. ..., written in 119.

Furthermore, when encoding is performed across 1, L, and R channels, that is, when the channel independent control signal is "1", the frame addresses are 0, 2, 4, . ....

50.60,62. . . 110, the required information symbols are successively outputted and supplied to the encoding circuit 19, and the check symbols generated thereby are assigned frame addresses 52, 54, . ..., 58°112, ...
, 118, and then receives the lowest one pin "1" of the output of the counter 7t, and the frame address becomes 1.3.5.
..., 51.61. ..., 11, and check symbols generated from this information symbol are frame addresses 53, 55, ..., 5! j, 113. ...,
119.

With such a circuit, it is possible to generate codes using K different information symbol sequences when the channels are independent and when they are not channel independent, as described above.

In this way, after a Q check symbol is generated and added in a period of T, and a P check symbol is further generated and added, in the next period of T, the information symbols and check symbols shown in the RAM of FIG. The read address control circuit 20 sets the frame address to 0.1, 2, . ...,
119 and are sequentially read out frame by frame, and the frame address addition circuit 27 adds a frame address signal that is the same as the frame address of the RAM to the beginning of the frame and supplies it to the modulation circuit 28. This frame-by-frame signal is added with a frame synchronization signal in the modulation circuit 28, and after being modified, is amplified in the recording amplifier 29, and sent via the switch 30 to the heads 32Ffi and 32b.
The data is recorded on the magnetic tape 1 at the same time. At this time, as shown in FIG. 2, after the information symbols and check symbols of the even number samples of the L channel with frame addresses 0 to 59 are recorded, a guard space for several frames is provided, and the R channel with frame addresses 60 to 119 is recorded. Information and check symbols of odd samples of the channel are recorded.

Furthermore, in the next T period, the remaining information symbols of the odd sample group of the L channel and the information symbols of the even sample group of the R channel are encoded in the same way, and are further recorded on the tape in the next T period.

Next, the configuration of the reproducing system of the recording/reproducing apparatus of this embodiment will be explained.

FIG. 9 shows a block diagram of the configuration of the reproduction system, and in the figure,
40 is a head selection switch, 41 is a reproduction amplifier, 42 is a demodulation circuit, 43 is a selection switch for reproduction writing and decoding, 4
4 is a RAM selection switch for playback writing and decoding, 45
．． 46 is a third RAM, a fourth RAM, 47 is a write address control circuit, 48 is a decode address control circuit, 4
9 is a channel independent control signal input terminal, 50 is a read address control circuit, 51 is a write address and decoded address selection switch, and 52 and 53 are the third RAM 4, respectively.
5. 54 is a decoding circuit; 55 is a pointer RAM; 56 is an address control circuit for the pointer RAM 55; 57 is a RAM selection switch for reproduction/reading;
8 is a correction circuit, 59 is a digital-analog (D/A)
converter, 60 is an output signal stereo selection switch,
61a and 61b are L channels respectively.

R channel analog audio signal output terminal, 62
is a timing control circuit.

Next, the operation of this reproduction system will be explained. Figure 10 shows a timing chart during playback.
) are the reproduced output waveforms of the heads 3a and 3b, respectively, and (C) and (d) of the figure are the reproduction output waveforms of the heads 3a and 3b, respectively. It shows the operation of the fourth RAM.

From the heads 32a and 32b, FIGS. 10(a) and (
As shown in b), reproduction outputs are obtained for periods K and T.

This playback head output is amplified by the playback amplifier 41 via the switch 4o, and then returned to the original digital signal train by the demodulation circuit 42, the frame address signal is sent to the write address control circuit 47, and the PCM data is sent to the switch. 43
．． 44 to the third RAM 45 or fourth RAM 46. The write address control circuit 47 generates a RAM address in response to the frame address signal, and
CM data is written to the RAM as shown in FIG.

The third RAM 45 and the fourth RAM 46 each have a capacity to write data for two tracks, but once one trunk's worth of PCM data is stored as shown in FIG. The decoding of the data is P decoding,
It is performed in the order of Q decoding.

That is, an address is designated by the decoding address control circuit 48, and information symbols and check symbols are supplied to the decoding circuit 54 via the switches 44 and 43. At this time, as mentioned above, the generation sequence of the Q check symbol is different when channel independent use is used and when it is not, so naturally the data to be read is different.
This can be realized by using the address generation circuit shown in the figure and changing the contents of the ROM 75 to the one shown in FIG.
7) Read each symbol in the order shown in equation (1))
.

The decryption method has been discussed previously, so I will not discuss it here. A pointer indicating a residual error that was not corrected by Q decoding is stored in the pointer RAM 55.

When the decoding of data for two tracks is completed, the information symbols are sent to the correction circuit 5 via the switch 57 during the next 4T period.
8. Switch 57 is recording switch 14
Similarly, it is switched at 16.67 Hz in synchronization with the rotation of the drum 31, and the third RAM 45 and fourth RAM 46 alternately perform reading, writing, and decoding. A pointer indicating whether or not there is an error in the symbol is supplied to the correction circuit 58 from the pointer RAM 55 at the same time as the information symbol.
If there is an error in either the upper symbol or the lower symbol, correction processing such as average value interpolation is performed on that word. The data is then restored to an analog signal by a D/A converter 59, separated into channels by a switch 60, and output from output terminals 61a and 61b, respectively.

In this embodiment, since the encoding and decoding RAM addresses are controlled to select the information symbol for code generation, it is possible to re-record the data of only one channel during after-recording. This can be easily done, and the burst error correction length in the track scanning direction can be maximized even when channels are not used independently. In addition, switching between channel independent use and non-independent use can be done by writing to RAM for both recording and playback systems.
This can be done with a very simple device configuration without changing the read address circuit or encoding/decoding circuit.

As mentioned above, in the case of encoding using a decoding circuit, the RAM at the time of encoding and the time of decoding are
Since the addresses are the same, the ROM contents shown in FIG. 8 are no longer necessary, and the ROM capacity can be reduced.

Furthermore, although the above embodiments have been described with respect to stereo PCM audio signals, the present invention is not limited to audio; for example, when two channels have no relation to each other, for example, the present invention is used as a memory of a computer. Even if the signal is used in such a case, the same effect as in the above embodiment can be obtained.

Further, it is not necessary to perform modulation and demodulation using the PCM method.

Furthermore, in the above embodiment, in the encoding and decoding address control circuit of FIG.
Although the M address is changed by changing the contents of the ROM 75, other methods may be used, for example, the corresponding frame address generation circuits may be selected by selectors. Further, the drum rotation speed, sampling frequency, quantization bit number, etc. used in the above embodiments are not fixed values.

〔Effect of the invention〕

As described above, according to the present invention, in a rotary head type recording and reproducing apparatus that separates information signals of two channels such as an L channel and an R channel across a guard space and records them on a magnetic tape, channel independent control is possible. Since the configuration is configured so that only the RAM address during encoding and decoding is switched by a signal to correspond to cases where channels are used independently or not, after-recording etc. can be easily performed, and track scanning can be performed even when channels are not used independently. The burst error correction length in the direction can be maximized, and it is encoded in both the recording and playback systems.

This has the advantage that it can be realized with a very simple device configuration without changing the writing and reading address circuits, encoding circuits, and decoding circuits in the RAM other than decoding.

[Brief explanation of the drawings] Fig. 1 is a data array diagram showing encoding and decoding in a conventional rotary head type recording/reproducing device, and Fig. 2 is a magnetic tape of a rotary head type recording/reproducing device capable of independent channel use. The above magnetization pattern diagram, FIG. 3 is a data array diagram showing encoding and decoding in a rotary head type recording/reproducing device according to an embodiment of the present invention, and FIG. 4 is a recording system of an embodiment of the device of the present invention. FIG. 5 is a timing diagram showing the operation of the recording system of the device, FIG. 6 is a RAM configuration diagram of the device, and FIG. 7 is the encoding and decoding RAM included in the device.
FIG. 8 is a block diagram showing the specific configuration of the address control circuit. FIG. 8 is a diagram of the contents of the ROM when encoding is performed in FIG. 7. FIG. FIG. 10 is a timing diagram showing the operation of the reproduction system of the apparatus, and FIG. 11 is a diagram of the contents of the ROM when decoding is performed in FIG. 7. 1... Magnetic tape, 15, 16, 45.46... RAM for storing data, 19... Encoding circuit, 21...
- Encoded address control circuit (first and second memory address designating means), 22.49... Channel independent control signal input terminal, 23... Write address control circuit (symbol block creation means), 54...・Decoding circuit, 48・
...Decoded address control circuit, 73...Frame address counter, 74...Symbol address counter, 7
5...ROM, 76...Adder. Note that the same reference numerals in the figures indicate the same or equivalent parts. Ward

Claims (5)

[Claims] (1) A rotary head type recording and reproducing device that records and reproduces digital information signals of first and second channels separately across an area other than the digital information signal recording area within a predetermined scanning period, symbol generating means for digitizing an input information signal to generate information symbols of a predetermined number of bits; a memory for storing the information symbols; and symbol block creation for storing the information symbols in the memory in the form of information symbol blocks. means for generating and adding at least one of an error correction code and an error detection code to the information symbol; and a substantially equal number of information symbols from either one of the two channels or both channels from the memory. a step of reading out the information symbols and supplying them as one code generation sequence to the encoding means, and writing into the memory at least one of an error correction code and an error detection code both generated by the encoding means. A rotation device comprising first and second memory addressing means, and control signal generating means for generating a control signal for selecting either one of the first and second memory addressing means. Head type recording/playback device. (2) The symbol block creation means converts the information symbols of the first and second channels into three each of (x, y, z).
E, K, N in the dimension direction (E, K≧1, N≧2 integers)
The first memory addressing means creates (E, K, N) symbol blocks for each channel by arranging E symbol blocks in the x direction and x adjacent to it in the z direction within each block. The second memory addressing means reads out a total of 2E information symbols including E information symbols in the x direction and the other information symbols in the x direction of the block of one channel. A second total of 2E information symbols including E information symbols in the x direction of the block of the channel are read out as one code generation sequence, and the encoding means reads out the information symbols with the first memory addressing means. 2 for the first 2E information symbols
Generate F (an integer of F≧1) first check symbols, add them to each of the first 2E information symbols in the x direction, and add each block as a whole. (E+F, K, N) symbol block, and the encoding means encodes 2F information symbols for the second 2E information symbols read out by the second memory addressing means. A second check symbol is generated and added to each of the second E information symbols of each of the blocks of the different channels, F times each in the x direction, so that each block is (E+F, K, N) as a whole. 2. A rotary head type recording/reproducing apparatus according to claim 1, wherein said symbol block is used as a symbol block. (3) The symbol block creating means generates information symbols for each of the first and second channels by 3 each of (x, y, 2).
E, K, N in the dimension direction (E, K≧1, N≧2 integers)
The first memory addressing means creates (E, K, N) symbol blocks for each channel by arranging E symbol blocks in the x direction and x adjacent to it in the z direction within each block. The second memory addressing means reads out a total of 2E information symbols including E information symbols in the x direction and the other information symbols in the x direction of the block of one channel. A second total of 2E information symbols including E information symbols in the x direction of the block of the channel are read out as one code generation sequence, and the encoding means reads out the information symbols with the first memory addressing means. 2 for the first 2E information symbols
Generate F (an integer of F≧1) first check symbols, add them to each of the first 2E information symbols in the x direction, and add each block as a whole. (E+F, K, N) symbol block, and the encoding means encodes 2F information symbols for the second 2E information symbols read out by the second memory addressing means. A second check symbol is generated and added to each of the second E information symbols of each of the blocks of the different channels, F times each in the x direction, so that each block is (E+F, K, N) as a whole. Further, the encoding means encodes the (E+F, K, N) symbol block with J check symbols (an integer of J≧1) for the K information symbols in the y direction. is generated and added to each block as a whole (E+F
, K+J, N) symbol block, and when recording information symbols and check symbols, y
Each frame consists of (K+J) symbols in the direction, and each symbol is read out in a predetermined order for each frame, a synchronization signal is added to the beginning of each frame, and (E+F, K+J, N) Symbol blocks are separated within one scanning period across an area in which signals other than digital information signals are recorded, and are recorded in block units. A rotating head type recording and reproducing device. (4) The symbol block creation means creates a total of four (E, K, N) symbol blocks for each even-numbered sample and odd-numbered sample of the information symbols of each of the first and second channels. The first memory addressing means supplies information symbols to the encoding means so that the encoding is completed within each block, and the second memory addressing means supplies information symbols to the encoding means so that the encoding is completed within each block. ,
Information symbols are supplied to the encoding means so that encoding is performed across two blocks, that is, an even sample block and an odd sample block of different channels, or two blocks of even sample blocks and odd sample blocks of different channels. A rotary head type recording/reproducing device according to claim 2 or 3, characterized in that the rotary head type recording/reproducing device is a rotary head type recording/reproducing device. (5) A patent characterized in that, among the four blocks, two blocks to which information symbols that are read out as one code generation sequence by the second memory addressing means belong are recorded within one scanning period. A rotary head type recording/reproducing device according to claim 4.