JPS61294566A - Communication control processor - Google Patents

Abstract

PURPOSE:To perform the sense/control operation with various transistors without using any special interface by performing the reading/writing operations of various registers set at circuit junction parts in an invalid mode where no request is given to the bit processing. CONSTITUTION:In a sense mode a sense/control indication, the sense and a register address are written to a desired circuit corresponding memory (ICW)10. A circuit junction part LiC sets the contents of the register indicated by a register address given from an out-bus to an in-bus. Then a circuit scan part CS writes the data to the ICW10. While in a control mode a sense/control indication, the control and the register address setting data to the desired ICW10. The part LiC receives a register address and data from the out-bus and sets this data to the register indicated by the register address.

Description

[Detailed Description of the Invention] [Summary] In a communication control processing device equipped with a line connection section, a line scanning section, and a display operation section, during invalid scanning when there is no bit processing request from the line connection section, the line scanning section , a configuration is shown in which each Yuzu register is read as instructed by the display operation unit or the control program, and if there is a write request, it is inserted at the timing of setting the transmission data.

[Industrial application field]

This book pertains to reading and writing methods for various registers in a line connection section in a communication control processing device.

[Problems that conventional technology and inventions attempt to solve] In recent years,
With the advancement of semiconductor technology (・Using large-scale JJK product circuits, small devices with multiple operating modes have been developed.
・Ru.

The communication control device has multiple line connections depending on the communication speed, etc. depending on the communication speed, etc., and the basic circuit is configured with one large-scale integrated circuit that is selected according to the purpose of use, and the initial settings etc. I decided to use the operating mode and became reluctant to use it.

In the conventional line connection section, most of the operating modes (one package and fixed) did not require reading or writing the operating mode, but it would be very useful if other control registers could be sensed and controlled during maintenance. It's convenient.

To achieve this, it was necessary to provide a special interface for sense/control.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is designed to solve the above problem by solving the following problems:
Taking advantage of the fact that multiple scans are performed during one bit reception/transmission, and invalid scans occur, when there is no bit processing request, the display operation unit or control program It reads the various registers specified by , and if there is a write request, it is read in and out at the timing of setting the transmission data.

[Effect]

According to the present invention, bit processing is required! The system senses/controls each stock register at the line connection part, such as inputting setting data and protruding data, during undesired invalid scans, and makes effective use of the registers during invalid scans. It is possible to sense/control each dim register in the line connection section without providing an interface.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The first figure is a block diagram of a communication control processing device according to an embodiment to which the present invention is applied, the second figure is a block diagram of a line scanning section and the line connection section according to an embodiment of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 4 shows a scanning time chart.

In FIG. 1, 1 is a central processing Vc, 2 is a channel,
3 is Shinshu TBL+ control processing device, 4 is line connection section, 5 is central control section, 6 is channel adapter, 7 is display operation section,
8 is a memory, and 9 is a line scanning section.

In FIG. 2, 10 is a line compatible memory, which holds the address of one of the multiple registers in the line connection section.
a means for controlling the sense/control operation, a means for holding sense/control data, and a means for holding control data for controlling the sense/control operation. 11 is one of multiple registers provided in the line connection section.
12 is a means for selecting one of a plurality of registers, 13 is a means for selecting the state of the line when there is a bit processing request from the line, and 12 is selected when there is no bit processing request. This is a means for selecting the contents of a register.

First, the collection operation will be explained. The SAR in Figure 2 is configured to hold the line address, step by step, and the S&R
The contents of the line-compatible memory are written to the SWR by the address shown in
At the same time, the line connection section (hereinafter abbreviated as LIC) for that address is selected.

This is the address indicated by CLIC&DR8&iSnR in FIG. 4, indicating that LICO is selected.

In the case of a conventional line connection unit, when LICO is selected, it sends the line status such as modem status and received data, and whether or not a bit processing request is required to a line scanning unit (hereinafter abbreviated as C3). This bit processing request requests one bit of next transmission data in the transmitting state, and indicates that one bit of data from the line has been received in the receiving state.

Normally, in order to prevent bit omissions from occurring, the system is designed to perform multiple scans within one bit time, so there are times when there is no bit processing request.
In the present invention, during scanning without this bit processing request, K sends the contents of a register selected by means for holding the address of one of a plurality of registers in the line connection section to C8.

When the C8 receives the above data from the LIC, if there is a bit processing request and it is in the sending state, it takes out the sending bit from the SWR loaded from the line compatible memory (hereinafter abbreviated as ICW) and processes it as shown in Figure 4. C0NT, B
LICK with REG? I. C0NT and B REG are B REGs that hold transmission data, modem control signals, etc.
One B REG is held per line. In the receiving state, the received data transferred together with the bit processing request is taken into the ICW.

The transmission/reception data holding section of the ICW is a two-character buffer for performing serial-to-parallel conversion of transmission/reception data.
F: Parallel DataField)
, a field for disassembling transmitted data and assembling received data (S DF: a@real Data Fl-
・ld), and when transmitting, it is shifted to the data ' of SDF every 1 bit transmitted, and when one character transmission is completed, the data of Hata DF is transferred to SDF, interrupts the control program, and the data transferred to SDF is transferred during transmission. Request to set one character in YPDF to be sent next. At the time of reception, data from the line is assembled bit by bit using SDF, and when a photon is assembled into a single letter, the data is saved in PDF, and the control program is interrupted, and the subsequent received data is converted into 3DF.
While assembling the data, the control program requests that the PDF data be processed by the control program.

If there is no bit processing request, the contents of the SWR are written to the ICW again without being changed.

If it is in the transmitting state, BRE is set by C0NT, B BEG.
Since GIC transmission data and modem control signals are stored, LICO sends transmission data to the line.

In addition, LICADR8 and C0NT.

The operation instruction of B REG is given by the Data Control signal.

This series of processing is a scan of one line, and then the S input RY step is performed to perform services on other lines in the same way.

Next, the case where the line is controlled from the control program or the display operation section will be explained.

PAR shown in FIG. 2 is a register for setting the address of the ICW from the program, and PWR is a register for loading the contents of the ICW indicated by the PAR, or for modifying and storing the data in the ICW. Therefore, the control program etc. can set the address of the line to be controlled in PAR and read and write the ICW of the selected line. It goes without saying that the line is controlled by writing to the ICW.

In the explanation of the general operation, we explained the write operation to B REG, but as a register similar to B REG, input REG, L
There are registers for controlling the IC's operating mode, such as MODEREG and low transmit/receive timing, etc., but the registers that can be controlled from C8 for general operation are A and B REG.
Sense/control for MODEBEG etc. is performed as follows.

In the case of sense, the sense/control instruction, sense, and register address are written into the ICW of the target line from the control program or display operation unit. C8 is C0NT in FIG. 4 if there is no bit processing request when scanning the relevant line.
, B REG timing to set the register address. In other words, SET the DataControl signal
)LEG 8DR3 and set the OUT BUSK register address.

LIC decodes the Data Control signal and returns 0
Set UTBUS data to register address holding means,
to C8 is the ICW address set completion bit.
”.

When the LIC is scanned again, it sets the contents of the register indicated by the register address 1ftINEUS instead of the line status if there is no bit processing request.

If there is no bit processing request, C8 saves the current data to 5
It is written to the sense/control data holding means of the ICW as ENSE DATA, and the sense/control instruction bit and address completion bit are set to 00#.

The control program or display operation section
When the control instruction bit becomes the 0° trap, the data in the sense/control data holding means is read and the operation is completed.

In the case of control, the sense/control instruction, control, register address, and data to be set are written into the target ICW from the control program or display operation section. If there is no bit processing request when scanning the relevant line, C8 sets the register address at the timing of C0NT and B REG shown in Fig. 4◇In other words, Da
Set the t&Control signal to SET REG A-RI and set it in the OUT BUS register address holding means. C8 sets the address set completion bit of the engineering CW to "1"
”.

When the LIC is scanned again, it sets INBUs to the contents of the register indicated by the register address instead of the line status if there is no bit processing request. C8 is a Data Control signal if there is no bit processing request.
0NT @REG and set the data in the ICW sense/control data holding means to 0UTBUS. At this time, the 5ENSED input from the LIC becomes invalid.

L I Ck'! , decodes the Data Control signal, and if it is C0NT REG, sets the OUT BUS data in the register indicated by the register address holding means.

C8 has a sense/control instruction bit, control, and address completion bit of 10m.

The control program or the display operation section confirms that the sense/control instruction bit has become "0" K, and the operation ends.

FIG. 5 is an expanded example of the anti-deception memory of the present invention.
A constant monitoring bit is provided in the control data holding means of W,
If there is no bit processing request during sensing operation, the sense data holding means is always changed. In other words, when this bit is °1', the normal 5ENSE
This is to suppress the operation of setting the sense/control instruction bit to "O" upon completion of inputting DATA to the ICW. This embodiment is also effective in cases where the operation of the LIC is constantly monitored.

〔Effect of the invention〕

As explained above, according to the present invention, by utilizing the fact that scanning is performed multiple times within the time of one bit of transmitted/received value data, the various registers of the line connection section are successively read and written during invalid scanning, so special This is useful because there is no need to provide an interface and it can be done even during operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication control processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of a circuit edge scanning section and a line connection section according to an embodiment of the present invention, and FIG. 3 is an implementation example. 4(a) to 4(f) are diagrams showing scanning time charts of the embodiment, and FIG. 5 is a diagram showing an example of expansion of the line-compatible memory.

Claims (1)

[Scope of Claims] A line connection unit that generates a bit processing request each time one bit of data is received from the line or transmitted to the line, and a plurality of lines are sequentially scanned to monitor the bit processing requests. At the same time, when the bit processing request is detected, if it is in the receiving state, the received bits are taken into the line compatible memory and characters are assembled, and if in the transmitting state, the characters in the line compatible memory are disassembled and the next transmission bit is passed to the line connecting unit, character by character. In a communication control processing device equipped with a line scanning section that generates a character processing request interrupt to a control program, and a display operation section that displays the status of each section, the line connection section includes one of a plurality of registers included in the line connection section. means (11) for holding one address; and means (12) for selecting one of a plurality of registers by the address holding means (11);
Means (1) for switching whether to transfer the contents of the selected register or the state of the line according to the bit processing request;
3), wherein the line scanning section has means for holding an address of one of a plurality of registers included in the line connection section in a line corresponding memory;
A sense/control data holding means for the line connection section and a control data holding means for controlling the sense/control operation are provided, and the sense/control data holding means for the register of any line can be stored from the display operation section or control program into the line corresponding memory. A communication control processing device that instructs control, and senses/controls a register of the line connection unit if a bit processing request is not generated when the line scanning unit scans the arbitrary line.