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JPS61285740A - High-density mounting type ceramic ic package - Google Patents

High-density mounting type ceramic ic package

Info

Publication number
JPS61285740A
JPS61285740A JP60126309A JP12630985A JPS61285740A JP S61285740 A JPS61285740 A JP S61285740A JP 60126309 A JP60126309 A JP 60126309A JP 12630985 A JP12630985 A JP 12630985A JP S61285740 A JPS61285740 A JP S61285740A
Authority
JP
Japan
Prior art keywords
package
cage
ceramic
shape
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60126309A
Other languages
Japanese (ja)
Inventor
Soichi Imamura
今村　宗一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP60126309A priority Critical patent/JPS61285740A/en
Publication of JPS61285740A publication Critical patent/JPS61285740A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は高密度実装回路を実現するため、ＩＣチップを
上下２段に搭載可能としたセラミックＩＣＡＩクケージ
に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a ceramic ICAI cage in which IC chips can be mounted in two stages, upper and lower, in order to realize high-density packaging circuits.

〈従来の技術〉 従来のＩ（：ｐ４ツケージは、第４図に示すように、）
々ツケージ本体工の片面にのみＩＣチップ１０を搭載す
るという２次元的な実装構造であつ九、その九め多くの
場合は、１つのＩＣ−９ツケージＫＦｉ１つのＩＣチッ
プだけしか搭載されていない。<Prior art> Conventional I (:p4 cage, as shown in Fig. 4)
It is a two-dimensional mounting structure in which the IC chip 10 is mounted only on one side of the cage body, and in most cases, only one IC chip is mounted on one IC-9 cage KFi.

第４図はチップキャリヤ形態のセラミックｌ　Ｃａ譬ツ
ケージの従来例を゛示し、セラミック製ノ々ツケージ本
体１の上面の略中夫にＩＣチップ搭載部分としてキャビ
ティ２が１つ形成されておシ、キャビティ２周囲のノ譬
ノケージ本体ｌ上面にワイヤがンデイング用・臂ツド３
が形成され、更にノタツケージ本体１の側面から下面に
かけてＩ＃ラッドに接続する外部電極４が形成されてい
る。ＩＣチップ１０はキャビティ２内にダイがンデイン
グ５によって固定され、次いでＩＣチップ１０の電極と
ノ４ツケージ本体１のパッド３とが？ンデイングワイヤ
６で電気的に接続される。ＩＣチップ１０が搭載される
と、１４ツケ一ジ本体１の上面周囲にセラミック製スペ
ーサ７を封止固定し、さらにその上にメタル製あるいは
セラくクク製リッド８が封止固定することによシ、チッ
プキャリヤ形態のセラミックＡＩツケージＩＣができ上
る。９は封止材料、１１は印刷配線基板、１２は配線ノ
臂ターン、１３はハンダ付けである。FIG. 4 shows a conventional example of a ceramic lCa cage in the form of a chip carrier, in which one cavity 2 is formed approximately in the center of the upper surface of the ceramic notch cage main body 1 as an IC chip mounting portion. Wires are attached to the upper surface of the cage body around cavity 2, and armpit 3
is formed, and an external electrode 4 connected to the I# rad is further formed from the side surface to the bottom surface of the cage body 1. The IC chip 10 is fixed in the cavity 2 by die mounting 5, and then the electrodes of the IC chip 10 and the pads 3 of the cage body 1 are connected. They are electrically connected by a connecting wire 6. When the IC chip 10 is mounted, a ceramic spacer 7 is sealed and fixed around the upper surface of the 14-pack main body 1, and a metal or ceramic lid 8 is further sealed and fixed on top of the ceramic spacer 7. Then, a ceramic AI cage IC in the form of a chip carrier is completed. 9 is a sealing material, 11 is a printed wiring board, 12 is a wiring arm turn, and 13 is soldering.

〈発明が解決しようとする問題点〉 従来の工Ｃノ９ツケージは上述の如＜ＩＣチップ１０を
パッケージ本体１０片面に１つしか搭載しないため、実
装密度があまシ高くない。そこでＩＣチップを複数個搭
載することも考えられているが、パッケージ本体の片面
に並べるという２次元実装から脱却していない。そのた
め、さほど高密度化せず、また・臂ツケージ形状が平面
的に大きい特殊なものＫなって後工程での印刷配線基板
への実装が困難である。<Problems to be Solved by the Invention> As described above, in the conventional C9 cage, only one IC chip 10 is mounted on one side of the package body 10, so the packaging density is not very high. Therefore, mounting multiple IC chips is being considered, but this has not moved away from the two-dimensional mounting method of arranging them on one side of the package body. Therefore, the density is not so high, and the shape of the arm cage is large in plan, making it difficult to mount it on a printed wiring board in a subsequent process.

本発明は上記従来技術に鑑み、外形が標準パッケージと
殆んど変わらず、２つのＩＣチップを搭載することがで
きるセラミックＩＣ・４クケージを提供することを目、
的とする。In view of the above-mentioned prior art, the present invention aims to provide a ceramic IC four-pack cage that has an outer shape that is almost the same as a standard package and that can mount two IC chips.
target

く問題点を解決するための手段〉 本発明によるセラミックエＣ／譬りケージは、ＩＣチッ
プ搭載用キャビティをノ９ツケージ本体の上下両面に有
し、且つ各キャビティに搭載されるＩＣチップに対する
がンディンダＩクツド及び外部電極を有し、外形が標準
ＩＣ−４クケージに近似した形状のものである。Means for Solving the Problems> The ceramic cage according to the present invention has cavities for mounting IC chips on both upper and lower surfaces of the cage body, and It has an internal IC-4 cage and an external electrode, and has an external shape similar to that of a standard IC-4 cage.

く作用〉 Ａ？クケージ本体の上下両面にキャビティが存在するの
で、１つの工Ｃノ４ツケージに２つのＩＣチップを搭載
することができる。この場合、ＩＣ−＃ツケージは厚み
が少し大きくな・るが、３次元実装のため平面的な大き
さは殆ど大きくならず、実質上極めて高密度化する。Effect〉 A? Since there are cavities on both the upper and lower sides of the cage body, two IC chips can be mounted on one C4 cage. In this case, the IC-# cage becomes slightly thicker, but because of three-dimensional mounting, the planar size hardly increases, and the density is substantially increased.

そのため、従来から存在するチップキャリヤ形態、デュ
アルインライン／９ツケージ形態、ピングリッドアレイ
形態などの標準■Ｃノ臂クツケージ殆んど変わらない外
形にすることができ、これによｊ）　ＩＣＩ’？ツケー
ジの実装の自動化が簡単になる。特に、外部電極の数が
増えるが、その形状を従来の標準工Ｃ／？ツケージにお
ける外部電極の形状と近い形状とすれば、自動実装も一
層簡単になる。Therefore, it is possible to make the external shape almost the same as the conventional chip carrier form, dual in-line/9-cage form, pin grid array form, etc. It becomes easier to automate the implementation of the package. In particular, the number of external electrodes increases, but the shape is different from that of the conventional standard C/? If the shape is similar to the shape of the external electrode in the package, automatic mounting will be easier.

〈実施例〉 本発明の一実施例に係るセラミックＩＣ−やツケージを
第１図によシ説明する。第１図において、ノクツケージ
本体１はセラミック製であシ、上下両面にそれぞれキャ
ビティ２ａ。<Example> A ceramic IC and a package according to an example of the present invention will be explained with reference to FIG. In Fig. 1, the cage main body 1 is made of ceramic, and has cavities 2a on both the upper and lower surfaces.

２ｂを有する。また・母ツケージ本体１の上下両面には
それぞれ各キャビティ２ａ、２ｂの周囲にワイヤデンデ
ィング用／４′ツド３ａ　、　３ｂが形成され、更に各
・母ツド３ａ、３ｂに接続して外部電極４ａ、４ｂが形
成されている。It has 2b. In addition, /4' sockets 3a and 3b for wire ending are formed around the cavities 2a and 2b on the upper and lower surfaces of the main cage body 1, respectively, and external electrodes 4a are connected to the respective main sockets 3a and 3b. , 4b are formed.

このようなＡＩツケージ本体工の各キャビティ２ａ、２
ｂＫ：ＩＣチツゾ１０ａ、１０ｂがそれぞれ搭載され、
／９ノド３ａ、３ｂとの間で所定のワイヤ？ンディソグ
を施したのち、メタルまたはセラミック製すクド８ａ、
８ｂで上下が塞がれる。５ａ、５ｂはグイ？ンデインダ
、６ａ、６ｂｔｉ＆ンディングワイヤ、７ａ、７ｂはセ
ラミック製スペーサ、９ａ。Each cavity 2a, 2 of such AI cage main body construction
bK: IC Chitsuzo 10a and 10b are installed respectively,
/9 A predetermined wire between the nodes 3a and 3b? After applying the sanding, metal or ceramic Kudo 8a,
The top and bottom are blocked by 8b. Are 5a and 5b good? Ending wires, 7a, 7b are ceramic spacers, 9a.

９ｂは封止材料である。9b is a sealing material.

第１図よシ判るように、下側のＩＣチッグＪｏｂを収容
する分だけノ４ノヶ−ジの厚さが少し厚くなるが、２つ
のＩＣチップが上下２段になるので、平面的な大きさは
従来から存在する標準工（：　）Ｊ？ツケージの大きさ
と略等しい。As you can see from Figure 1, the thickness of the No. 4 nozzle is a little thicker to accommodate the lower IC chip job, but since the two IC chips are in two layers, one above the other, the flat surface is The size is the standard construction (: ) J? approximately equal to the size of the cage.

第２図と第３図に・ぐツヶージ形態についての２つの実
施例を示す。第２図に示すものはチップキャリヤ形態の
ものであシ、下側のスベーナ７ｂｆ：！ｊクド８ｂよシ
下に突出する形状トシ、各Ｉ　Ｃｆｙｆｌｏａ　、１０
ｂ用Ｏ外部電極４ａ、４ｂｔ−下面まで延長させである
。FIGS. 2 and 3 show two embodiments of the gutsage configuration. The one shown in FIG. 2 is in the form of a chip carrier, and the lower subena 7bf:! J Kudo 8b, shape toshi protruding below, each I Cfyfloa, 10
The O external electrodes 4a and 4b for b are extended to the lower surface.

これによシ、ノ々ツケージ形状及び外部電極形状が従来
の標準的なチップキャリヤと略同じになっている。チッ
プキャリヤの場合はテーピングすることによシ、自動実
装を行うことができる。第３図に示すものはＰＧＡ（ピ
ングリッドアレイ）形態のものであシ、ノぞツケージ本
体１の両側部を若干張り出し、各ＩＣノぐツケージ１０
ａ、１０ｂ用の外部電極４ａ。As a result, the shape of the notch cage and the shape of the external electrodes are substantially the same as those of a conventional standard chip carrier. In the case of a chip carrier, automatic mounting can be performed by taping. The one shown in FIG. 3 is a PGA (pin grid array) type, in which both sides of the slot cage main body 1 are slightly protruded, and each IC slot cage 10 is
External electrode 4a for a, 10b.

４ｂとしてビン１４ａ、１４ｂを立てである。4b, the bottles 14a and 14b are placed vertically.

この場合も、ノＲツケージ形状及び外部電極形状が従来
の標準的なＰＧＡと略同じであるうまた、図示はしない
がＤＩＰ（デュアルインラインノぐツケージ）形態の場
合も従来の標準的ＤＩＰとパックー・り形状、外部電極
形状が略同じである。これによシ従来と同様にノぞツケ
ー・りの自動実装が可能になる。なお、パッケージ内の
２つのＩＣチップ１０ａ、１０ｂ間の結線を必要に応じ
てパッケージ本体１に配線、？ターンを形成して行って
も良い。In this case as well, the shape of the R-shaped cage and the shape of the external electrodes are almost the same as those of the conventional standard PGA.・The shape of the outer electrode and the shape of the external electrode are almost the same. This makes it possible to automatically implement the process in the same way as in the past. Note that the wiring between the two IC chips 10a and 10b in the package is connected to the package body 1 as necessary. You may also form a turn.

〈発明の効果〉 本発明によればパッケージ本体の上下両面にそれぞれキ
ャビティが存在するため、１つのＡ’ツケージに２つの
ＩＣチップを搭載することができる。この場合、ＩＣチ
ップが上下２段の三次元実装となるので、標準ＩＣ／４
′ノケージと殆んど変らないパッケージ形状となシ、高
密度実装が達成された。またキャビティを／４４ツケー
ジ体の上下両面に形成すれば良いので製造工程が従来と
殆ど変らず、パッケージ製造が簡単である。更にパッケ
ージ形状が標準ＩＣバクケージに近い次め、バクケージ
の自動実装が可能である。<Effects of the Invention> According to the present invention, since cavities are present on both the upper and lower surfaces of the package body, two IC chips can be mounted on one A' cage. In this case, the IC chips are three-dimensionally mounted in two stages, upper and lower, so the standard IC/4
The package shape is almost the same as that of the conventional cage, and high-density packaging has been achieved. Furthermore, since the cavities need only be formed on both the upper and lower surfaces of the /44 cage body, the manufacturing process is hardly different from the conventional one, and the package manufacturing is simple. Furthermore, since the package shape is similar to a standard IC back cage, automatic mounting of the back cage is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例に係るセラミックＩＣ／４ツ
ケージの要部縦断面図、第２図はチップキャリア形態と
したセラミックＩＣバクケージの断面図、第３図はピン
グリッドアレイ形態としたセラミックＩＣ／４ツケージ
の断面図、第４図は従来のセラミックＩＣパッケージの
断面図である。 図　面　中、 １はパッケージ本体、２ｍと２ｂはキャビティｖ３ａと
３ｂはワイヤデンディング／４ツド、４ａと４ｂは外部
電極、６ａと６ｂはデンディングワイヤ、１０ｍと１０
ｂはＩＦチッグ、１４ａと１４ｂはビンである。Fig. 1 is a longitudinal cross-sectional view of the main parts of a ceramic IC/4 cage according to an embodiment of the present invention, Fig. 2 is a cross-sectional view of a ceramic IC back cage in the form of a chip carrier, and Fig. 3 is a cross-sectional view of the ceramic IC back cage in the form of a pin grid array. A cross-sectional view of a ceramic IC/4 package. FIG. 4 is a cross-sectional view of a conventional ceramic IC package. In the drawing, 1 is the package body, 2m and 2b are cavities, v3a and 3b are wire endings/four ends, 4a and 4b are external electrodes, 6a and 6b are ending wires, 10m and 10
b is an IF tick, and 14a and 14b are bottles.

Claims (3)

【特許請求の範囲】[Claims] （１）ＩＣチップ搭載用キャビティをパッケージ本体の
上下両面に有し、且つ各キャビティに搭載されるＩＣチ
ップに対するボンデイングパッド及び外部電極を有し、
外形が標準ＩＣパッケージに近似した形状のセラミック
ＩＣパッケージ。(1) Having cavities for mounting IC chips on both the upper and lower surfaces of the package body, and having bonding pads and external electrodes for the IC chips mounted in each cavity,
A ceramic IC package whose external shape is similar to a standard IC package. （２）特許請求の範囲第１項において、外部電極の形状
が標準ＩＣパッケージの外部電極の形状に近似している
セラミックＩＣパッケージ。(2) A ceramic IC package according to claim 1, wherein the shape of the external electrode is similar to the shape of the external electrode of a standard IC package. （３）特許請求の範囲第１項または第２項において、パ
ッケージ形態がチップキャリヤ形態、デュアルインライ
ンパッケージ形態及びピングリッドアレイ形態のうちの
いずれかであるセラミックＩＣパッケージ。(3) A ceramic IC package according to claim 1 or 2, wherein the package form is any one of a chip carrier form, a dual in-line package form, and a pin grid array form.
JP60126309A 1985-06-12 1985-06-12 High-density mounting type ceramic ic package Pending JPS61285740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60126309A JPS61285740A (en) 1985-06-12 1985-06-12 High-density mounting type ceramic ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60126309A JPS61285740A (en) 1985-06-12 1985-06-12 High-density mounting type ceramic ic package

Publications (1)

Publication Number Publication Date
JPS61285740A true JPS61285740A (en) 1986-12-16

Family

ID=14931994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60126309A Pending JPS61285740A (en) 1985-06-12 1985-06-12 High-density mounting type ceramic ic package

Country Status (1)

Country Link
JP (1) JPS61285740A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246852A (en) * 1987-04-02 1988-10-13 Ibiden Co Ltd Semiconductor mounting substrate and manufacture thereof
JPH01253942A (en) * 1988-04-04 1989-10-11 Hitachi Ltd Semiconductor package and computer using it
DE19720275B4 (en) * 1996-05-17 2008-06-26 LG Semicon Co., Ltd., Cheongju Substrate for a semiconductor device, manufacturing method for the same and a stackable semiconductor device using the substrate
CN104677400A (en) * 2015-02-15 2015-06-03 深圳市康通科技有限公司 Ultrasonic sensor and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246852A (en) * 1987-04-02 1988-10-13 Ibiden Co Ltd Semiconductor mounting substrate and manufacture thereof
JPH01253942A (en) * 1988-04-04 1989-10-11 Hitachi Ltd Semiconductor package and computer using it
DE19720275B4 (en) * 1996-05-17 2008-06-26 LG Semicon Co., Ltd., Cheongju Substrate for a semiconductor device, manufacturing method for the same and a stackable semiconductor device using the substrate
CN104677400A (en) * 2015-02-15 2015-06-03 深圳市康通科技有限公司 Ultrasonic sensor and manufacturing method thereof

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