JPS61282891A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a display device, and more particularly to a cursor display.

2. Description of the Related Art In general, various information processing apparatuses such as office computers, personal computers, word processors, image editing processing systems, workstations, and CAD/CAMs are equipped with display devices such as bit map displays.

Bit map displays are equipped with a cursor pattern memory that stores cursor pattern data from the host side, and can selectively use multiple types of cursors by directly rewriting the data in the cursor pattern memory from the host side. I am trying to display it in

In this case, if the host rewrites the cursor pattern data during the display period, a flash will occur in the display, so rewriting the cursor pattern data during the non-display period, and since the horizontal blanking period is short in bitmap display, it is usually vertical. This is done within the blanking period.

By the way, some information processing apparatuses are equipped with pointing devices such as mice, and in this case, the cursor pattern often changes frequently.

Therefore, the host side must detect the vertical granking period and rewrite the pattern every time the cursor pattern changes, which reduces system throughput and increases the response time for changing the cursor pattern. It has the disadvantage of being long.

Purpose This invention has been made in view of the above points, and an object thereof is to shorten the display response time when changing a cursor pattern.

1-1 In order to achieve the above object, the present invention is provided with a FIFO memory for storing cursor pattern data from the host side.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is an external perspective view showing an example of an image editing processing device as an information processing device embodying the present invention.

This information processing device uses character information as an input device.

A keyboard 1 for inputting various information such as control information.

It includes a mouse 2, which is a pointing device, and an image scanner 3, which reads original images and the like.

It also includes a CRT display 4 that displays various information as an output device, and a laser printer 5 that prints out various information.

Furthermore, the main body 6 is provided with a floppy disk device (FDD) and a hard disk device (HOD) as storage devices.

FIG. 2 is a block diagram showing the control section of this information processing device.

This control section 10 controls the entire processing device by a microcomputer system consisting of a microprocessor (MPU) 11 consisting of, for example, a 16-bit microprocessor and a main memory 12.

The main memory 12 is a system area (resident area) that stores resident programs such as an operating system loaded from the floppy disk device 7 or hard disk device 8 at the time of startup.

It consists of a non-resident area that stores non-resident programs, a data area, and a RAM that constitutes a working area.

The control unit 10 also includes a keyboard interface (1/F) 13 for inputting information from the keyboard 1.
, a mouse interface 14 that detects the direction of movement, amount of movement, and speed of movement based on the X pulse and Y pulse from the mouse 2 as a pointing device, and a scanner interface 15 for inputting read data from the image scanner 3. It is equipped with ·moreover,
This control unit 10 controls a CRT display 4.
An RT interface 16, a printer interface 17 that controls the printer 5, and a floppy disk device (F
The floppy disk controller (F
DC) 1B and hard disk device! (HDD) 13
Hard disk controller (HDC) 19 that controls
It is equipped with

The CRT interface 16 and CRT display 4 constitute a bit map display as a display device, and the microprocessor (MPU) 11
is the host for this bitmap display.

Furthermore, the control surface 10 also includes a communication control unit (CCU) 20 that controls the transmission and reception of information with other communication terminal devices.

FIG. 3 is a block diagram showing an example of the CRT interface 16.

A CRT controller (CRTC) 21 is a circuit that controls the entire CRT interface 16.
A cursor display timing signal C that outputs a horizontal synchronization signal H8YNC and a vertical synchronization signal VSYNC to the T display 4, and also indicates the timing to display a cursor.
DISP, control signal CMOV for pattern writing
E. A display period signal DISP for controlling the output period of the video signal VIDEO is output to each section.

The frame buffer 22 is a bit map memory, which is allocated as part of the memory access space of the MPU (microprocessor) 11 as a host in FIG. , the display data is sequentially read out in response to display timing signals from the CRTC 21.

The FIFO (first-in, first-out) memory 23 serves as a host for the MPU (FIG. 2).
A control signal allocated as part of the memory access space of the microprocessor (microprocessor) 11, into which cursor pattern data to be displayed on the CRT display 4 is written by the MPUI 1, and output from the CRTC 21 during the horizontal non-display period (horizontal blanking period). Read by CMOVE.

The cursor pattern data read from the FIFO memory 23 is written into the cursor pattern memory 24 in response to the control signal CMOVE from the CRTC 21, and the cursor pattern data is sequentially read out in response to the cursor display timing signal CD15P.

In this way, the cursor pattern memory 24 and the host (
A FIFO memory 23 is interposed between the MPU 11) and the MPU 11).

The shift register 25 converts the display data read from the frame buffer 22 from parallel to direct and outputs it, and the shift register 2 converts the cursor pattern data read from the cursor pattern memory 24 from parallel to direct. and output it.

The gate circuit 27 is an exclusive OR circuit or an OR circuit.
It consists of circuits, etc., and the display period signal DI from the CRTC21.
Each shift register 25,
A video signal VIDEO, which is a combination of serial display data and cursor pattern data from 2Ei, is output to the CRT display 4.

Next, the operation of this embodiment configured as described above will be explained with reference to FIGS. 4 to 6.

When displaying data on the CRT display 4, the MPUI 1 writes one display data to the frame buffer 22. Note that writing to the frame buffer 22 is performed during the vertical non-display period (vertical blanking period) TVH, for example, as shown in FIG. 4, since the amount of data is large during bit map display control.

Furthermore, the MPU 1j writes required cursor pattern data to the FIFO memory 23 each time the cursor pattern changes, regardless of the display timing.

On the other hand, when one display period begins, the CRTC 21 outputs a display timing signal for reading display data to the frame buffer 22, and also outputs a display period signal DISP to the gate circuit 27 to open the gate.

As a result, the display data read out from the frame buffer 22 is converted into serial data by the shift register 25, and then sent to the video signal VIDEO via the gate circuit 27.
The image is transferred to the CRT display 4 and displayed.

Further, as shown in FIG.
A control signal CMOV100 is outputted to the FIFO memory 23 to transfer the cursor pattern data stored in the FIFO memory 23 to the cursor pattern memory 24.

1. For example, when the cursor display timing to display the cursor CA is reached as shown in FIG. 6, the cursor display timing signal C is stored in the cursor pattern memory 24.
D15P is output to cause the cursor pattern data stored in the cursor pattern memory 24 to be output.

Note that in FIG. 6, the area surrounded by diagonal lines is the image display period.

As a result, the cursor pattern data read from the cursor pattern memory 24 is converted into serial data by the shift register 26, combined with the display data from the frenime buffer 22 by the gate circuit 27, and sent to the CRT display 4 as a video signal VIDEO. sent and displayed.

In this way, it is equipped with a FIFO memory that stores cursor patterns from the MPU on the host side.

The cursor pattern stored in the FIFO memory is transferred to the cursor pattern memory at a predetermined timing.

Therefore, the host side (MPU) can write the cursor pattern to the FIFO memory of the display device regardless of the display timing, which suppresses the decline in system throughput and reduces the display response time when changing the cursor pattern. be shortened.

It goes without saying that the display device according to the present invention can also be used in information processing devices other than the information processing device in the above embodiment.

As explained above, according to the present invention, display responsiveness when changing a cursor pattern is improved.

[Brief explanation of the drawing]

FIG. 1 is an external perspective view showing an example of an information processing device equipped with a display device embodying the present invention. FIG. 2 is a block diagram showing the control section. FIG. 3 is a block diagram showing an example of the CRT interface, and FIGS. 4, 5, and 6 are timing diagrams for explaining the display control. 4...CRT display 10...Control unit 1
6...CRT interface 21...CRT controller 22...Frame buffer 23...FIFO memory 24...Cursor pattern memory Figure 4 Figure 5 Figure 6 Horizontal scan direction

Claims (1)

[Claims] 1. In a display device equipped with a cursor pattern memory that stores cursor pattern data from the host side,
An FI between the host side and the cursor pattern memory
A display device characterized by interposing an FO memory.