JPS6128253A - Data transmission system - Google Patents

Abstract

PURPOSE:To attain high-speed data transmission while selection processing of a terminal device is executed in parallel by adding a terminal address (DTA) to a transmission frame, fetching the DTA at the reception side and writing reception data on a reception buffer at a designated terminal device for transfer. CONSTITUTION:A data station 12 is connected to terminal devices 131-13n by a ring transmission line 14 and a destination terminal address DTA is added to the transmission frame. A transmission control section 18 of a transmission station converts transmission data added to the said frame into a serial data by a communication control section 17, a transceiver section 15 converts the data into a transmission signal, which is transmitted. A reception station makes the received transmission station address DSA coincident with the own station address. After the detection of coincidence, the address DTA is used, S/P conversion is executed to a terminal device to be transferred and the data is transferred. Thus, the communication control section 17 is provided with a circuit for data DMA (Direct Memory Access) between a transmission/reception buffer and a converting circuit of IF sections 191-19n in addition to the S/P, P/S conversion circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a 7'-event transmission system for a data way system in which a plurality of terminal devices are connected to one data station.

(Prior art) The Cheetah Way system connects a large number of terminal devices (including computers) with data stations and transmission lines using data ways configured in the form of links, buses, or point-to-point. It enables data exchange between terminal devices. FIG. 2 shows a ring-shaped dataway system, in which terminal equipment 1. ~14 are connected to data stations 2~24, respectively, and a transmission line 3 is connected between each station.
1 to 34 are connected in a ring shape. Then, each data station 2. ~24 is based on the station address. n1 Data transfer from the terminal device f (source) on the sending side of data to the terminal device t (destination) on the receiving side is the transmission f-IK source station address and reception. A destination station address is added and the data is transferred from the source station to the ring-shaped transmission path, and when the destination address attached to the received data matches its own address, the receiving station takes in the data and connects it to the station. The received data is transferred to the terminal device.

Such a data way system is network ff1
Only one terminal device can be connected to one data station. In addition, the point-to-point multiplexing device has a pair of data stations '+-- as shown in Figure 3.
4trlJll'e transmission line 5, and both stations 41+41 have a plurality of terminal devices 6I to 6n, 7. ~7n
However, data transmission between terminal devices is fixed on a one-to-one basis between the source side and the destination side.

For such a system, there are two data stations 21 to 2, as shown in FIG. multiple terminal devices 81 to 8n
,9. A data way system that connects up to 9 ns to, , to, llk can effectively utilize the transmission path and improve system functionality. Data transmission in this system includes the source station address,
In addition to attaching the destination station address, at least a terminal address indicating to which terminal device of the station address the data is to be transmitted is attached, and the destination station is provided with a common thread for each terminal device, After identifying the destination terminal device tt of the received data from the terminal address, the data is transferred to the terminal device.

(Problem to be Solved by the Invention) In a data way system in which a plurality of terminal devices are connected to each station, the receiving station determines whether the station addresses match and then transmits data to which terminal device. A two-step identification process is required, in which the terminal device is identified by its terminal address and then the data is transferred to the terminal device in question.

For this reason, there is a problem in that the data transfer efficiency is poor, making high-speed transmission difficult.

The present invention enables efficient and high-speed data transmission in block units between multiple terminal devices within a local station connected to one data station, and between arbitrary terminal devices connected to both the local station and other stations, respectively. The goal is to provide all possible data transmission methods.

(Means and effects for solving all problems) In addition to the destination station address, a terminal address is attached to the frame transmitted from the sending side, and the receiving side data station has a terminal address in addition to the address bus, data bus, and control bus. ff on the address bus, a means for writing the terminal address into the register after detecting a match between the station addresses, and a means to output the memory address of the transfer destination to the address bus every time received data is transferred to the reception buffer, and the contents of the terminal address register at the same time. A means for outputting the data to the terminal address bus is provided with a communication control unit, and when the address data on the terminal address bus matches the address of the connected terminal device, the data is written to the memory area of the receive buffer specified by the address bus. The terminal interface section ke is used to specify the transfer destination terminal device in parallel with the transfer.

(Embodiment) FIG. 1 tAI shows a block diagram of a data station showing an embodiment of the present invention, and FIG. 1 IBI shows the receiving circuit configuration of a terminal interface section and a communication control section.

FIG. 1 (In Al, one data station 12
171mff number of terminal devices 13. ~13r] is connected
'L.

A ring-shaped data way system is constructed in which the ring-shaped transmission path 14 connects to data stations of other stations, and furthermore, from these stations to terminal equipment. The frame format of transmission data exchanged between the data station 12 and the transmission line 14 is as follows.

That is, in addition to the information field (2) to be transmitted, the transmission data includes exchange information consisting of the destination data station address D8A, the destination terminal address DTA, the control field C1, the source data station address S8A, and the source terminal address 8TA. Information indicating the contents of the frame, a frame check sequence FC8 for data checking, and a 7-lag sequence F for frame synchronization are attached.

The data station 12 has a transceiver ff that mutually converts signals on the transmission path 14 and electrical signals within the station.
B15, and) a communication control unit 17 that mutually converts the serial input/output signals of the runshiper unit 15 and the parallel signals on the internal bus 16.
, a transmission control s18 that performs protocol processing, etc. for exchanging information with the terminal devices ft131 to ft13rU and executing transmission procedures, and a buffer for data transmission and reception.The data transfer rate specified by the transmission rate and the data of the terminal device. 1 communication control unit 17, which includes a terminal interface @ 19, ~ 19T3, which has a function of absorbing differences in transfer speeds;
and the transmission control section 18 and the interface sections 191 to 19n.
There was no exchange of information between them due to the internal bus 16.
In this configuration, the source station for data transmission is the transmission control unit 1 that has received the transmission request from the terminal device.
8 is the transmission data 111 from the terminal device, as well as the destination station address D8A, the destination terminal address DTA, and the source addresses 88A and 8TAj.
A control field C, etc. is added, and the data in the above format is converted into serial data by the communication control section 17, converted into a transmission signal by the transceiver section 15, and placed on the transmission path 14.

The destination data station that receives this data performs serial/parallel (s/p) conversion on the received frame, checks whether the DsA and its own address match, and if they do not match, stops the data capture, and If it is, serial/parallel switching is performed until the end of the frame and data is taken in. These D
8A and the own address match, the frame is captured in the same way as in conventional reception processing. After this K710, the destination data station detects a match between the DEIA and its own address, and then sends the terminal address DTA, 'ii
Serial/parallel conversion and data transfer are performed simultaneously to the terminal device to be transferred using the serial/parallel conversion. Therefore, the communication control unit 17 has S/
In addition to the p conversion circuit, parallel/series (p/8) '11 conversion circuit, there is also an interface section 19. DMA of data between ~19n transmit/receive buffer and p/s, s/p conversion circuit
(Direct, Memory Access) Provides a (b) path for transfer.

The receiving circuit of the data station is constructed as shown in FIG. 1 (IB). The internal bus 16 includes a first (li') internal bus 16. which is composed of an address bus, a data bus, and a control bus. In addition to the terminal address /(x
Holds 162k. Terminal address bus 1 ((,
DTA multiple terminal devices connected to the internal bus
Or used to distinguish from 8TA.

After sending several addresses, the communication control unit 17 stores the received data from the DTA data i8/P conversion circuit 20 into the DTA register 21, and at the same time requests the transmission control unit 18 for the right to use the internal bus 160 using a signal engineer. After receiving the permission signal J from the transmission control section 18, the DMA control circuit 22'f is driven. The DMA control circuit 22 causes the data bus buffer 23 to take in the data from the S/P conversion circuit 20 (via the delay buffer 20At during high-speed transmission), and also causes the interface section 19. The address data set of the address bus buffer 25 and the contents of the DTA register 21 for addressing the reception data memory area of the reception backup memory 24 of 23, 25, .
The contents of 28 are outputted to the address bus, data bus and terminal bus by setting the contents of control bus 7a 27 to the address bus, data bus and terminal bus. This control is performed every time received data is transferred, and the memory address and terminal address are updated.

The interface units 191 to 19n are connected to the bus 16. , 16. A data bus buffer 2B, an address bus buffer 29, a terminal address bus buffer 30, and a control bus buffer 31t are connected to the communication control unit 171111 to take in data from the communication control unit 171111. Interface section 19. A terminal address match detection circuit 32 is provided at 19° to 19°, and when a match with the terminal address DTA from the buffer 30 is detected, data is written into the memory area of the memory 24 specified by the address data from the buffer 29. For this address specification, a memory select signal for the pack memory 24 is obtained by the output of the reception buffer selector 33 which takes in the address data of the buffer 29 and the output of the coincidence detection circuit 32. The data written in the reception buffer memory 24 is taken into the terminal devices 13° to 13T3 after the writing is completed.

By receiving data in this way, even if multiple terminal devices are connected to one data station, data can be transferred to the desired terminal device, and the destination terminal device can be specified in parallel with the data transfer. The station and terminal equipment are l
It is possible to obtain a transmission speed equivalent to that of a 2-pair transmission system.

Note that when transmitting data, the terminal address of the transmitter is not recognized by the transmitter, so the terminal address and memory address of the interface section where the transmit data is stored can be easily accessed by the DMA control circuit without using the DTA register. All you have to do is write it to the address register. In addition, for data transfer between terminal devices within the own station, the bus 16**16t is valved under the processing of the transmission control section 18 to perform data transfer between reception buffer memories.

In addition, although a ring-shaped data way system is shown in the embodiment, it goes without saying that the present invention can also be applied to a bus-shaped data way system and a point-to-point multiplexing device.

(Effects of the Invention) According to the present invention, a terminal address is attached to a frame to be transmitted in addition to the destination station address,
A terminal address bus is added as an internal bus of the data station, and the receiving data station reads the terminal address data while detecting a match between the data station addresses, and transfers the received data to the terminal device specified by the terminal address. My friend who wrote to the receive buffer of the interface part,
? To enable high-speed data transmission by performing one-choice processing for J number of terminal devices in parallel.

[Brief explanation of the drawing]

Fig. 1 IA) is a data station configuration diagram showing an embodiment of the present invention, Fig. 1 na+ is a receiving circuit configuration diagram in Fig. Fig. 3 is a block diagram of a point-to-point multiplexing device, and Fig. 4 is a block diagram of a data way system in the method of the present invention.1., t4... terminal device, 2., 24... data station, 3. ., '4'' Transmission line, 8.1
8. ．． 9.69n#IJ*101sll...Terminal device t, 12...Data station, 131.13n.
...Terminal device, 14...Transmission path, 15...Transceiver unit, 16...Internal bus, 17...Communication control unit,
18...transmission control unit, 19. ．． 19ゎ...Terminal interface section, 20...8/P conversion circuit, 21...
- DTA register, 22...DMA control circuit, 23.
28...Data bus buffer, 24...Receive buffer memo! J, 25.29... Address bus buffer 7.
26.30...Terminal address bus buffer, 2
7.31...Control bus buffer, 32...
Terminal address - several output circuits, 33...receive buffer selector. Wa1O NC to N to- 〇 〇

Claims (1)

[Claims] In a dataway system in which each data station is connected by a transmission path, multiple terminal devices are connected to each data station, and data is transmitted between each terminal device, the source terminal device sends the destination station address in the transmitted frame. The data station has an internal bus consisting of an address bus, a data bus, and a control bus as well as a terminal address bus, and the receiving data station receives the data after detecting a match between the station addresses. Means for writing the terminal address of the received frame into the terminal address register at the same time as starting capture, and means for outputting the memory address of the transfer destination to the address bus every time the received data is transferred to the receiving buffer memory, and at the same time writing the contents of the terminal address register. a communication control unit including means for outputting data to the terminal address bus; and a communication control unit that outputs data to a memory area of a reception buffer specified by the address bus when address data on the terminal address bus matches the address of a terminal device to be coupled. A data transmission method characterized by comprising a terminal interface section for writing.