JPS6128231B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and particularly a source having a fine structure and adjacent to a channel region.
This relates to a method for manufacturing insulated gate integrated circuit devices in which the drain region is formed shallowly.

In recent years, demands for higher speed and higher density semiconductor integrated circuits having insulated gate field effect transistors have increased, and along with this, the development of fine pattern processing methods has also become important. As the pattern becomes finer, the size of the connection hole formed in the insulating film between the gate electrode or the impurity diffusion layer in the substrate and the metal wiring becomes smaller, ranging from 8 μm to 1 μm.
In particular, it is difficult to form a connection hole between an impurity diffusion layer in a substrate and a metal wiring using conventional photolithography.

On the other hand, there has been no effective method for forming the electrode lead-out portions of the source and drain regions deep and the portion adjacent to the channel region shallow.

Therefore, an object of the present invention is to easily open a connection hole for connecting impurity diffusion in a substrate and metal wiring;
Another object of the present invention is to provide an effective method for manufacturing source and drain regions having the above-mentioned shapes easily and at a high yield.

A feature of the present invention is that in a method for manufacturing an insulating film gate field effect transistor in an active region of a semiconductor substrate of one conductivity type, dilute silicon dioxide is used in a first portion of the source and drain regions adjacent to the channel region. a polycrystalline silicon film is deposited on a second portion of the first partially inactive region, and impurities of opposite conductivity type are introduced through the thin silicon dioxide film and the polycrystalline silicon film by thermal diffusion. By introducing it into the source and drain forming regions and performing thermal oxidation,
A shallow PN junction is formed in the first part, a deep PN junction is formed in the second part, and both constitute a source and drain region, and a thermally oxidized layer is formed on the polycrystalline silicon film. A method of manufacturing a semiconductor device includes forming a silicon dioxide layer according to the present invention, forming a connection hole in the silicon dioxide layer, and forming a metal wiring that contacts the polycrystalline silicon film through the connection hole.

The present invention is based on the principle that the photoresist film can be coated almost uniformly in thickness without creating a concave shape on the opposite conductivity type region. Therefore, even minute connection holes can be uniformly formed, and high-density integration with high yield can be achieved. A circuit device is obtained. Also, deep source and drain regions
The process is simplified because the PN junction part and the shallow PN junction part can be formed at the same time, and according to the above method, it is possible to automatically suppress the spread of the PN junction in the substrate area under the gate insulating film. Facilitates formation of channel type transistors.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of the main steps of the first embodiment of the present invention. First, as shown in FIG. 1A, an active region and an inactive region are formed on a P-type silicon crystal substrate 101 by a known selective oxidation method using a silicon nitride film, and a P ⁺ diffusion layer is formed in the inactive region. 103
and a thick silicon dioxide film 102 in the active region.
A silicon dioxide film 104 of 0A is selectively formed.
Thereafter, as shown in FIG. 1B, the polycrystalline silicon film 105 is
The silicon dioxide film 106 is formed to have a thickness of approximately 5,000 Å, the silicon dioxide film 106 to a thickness of approximately 1,000 Å, and the silicon dioxide film 107 to a thickness of approximately 200 Å. The silicon dioxide film 107 is selectively etched away using a hydrofluoric acid aqueous solution by photolithography. Next, as shown in FIG. 1C, the silicon nitride film 106 is removed by etching in hot phosphoric acid to selectively expose the polycrystalline silicon film 105.
After performing phosphorus diffusion thereon, the polycrystalline silicon film 10
5 is removed by etching with a mixture of nitric acid, hydrofluoric acid, and glacial acetic acid. Polycrystalline silicon containing phosphorus has an etching rate several tens of times faster than polycrystalline silicon that does not contain impurities, so transistors can be uniformly removed regardless of non-uniformity in the thickness of the polycrystalline silicon film. Then Figure 1D
As shown in FIG. 3, the silicon dioxide film 107 is removed by etching in a hydrofluoric acid aqueous solution and the silicon nitride film 106 is sequentially etched away in hot phosphoric acid. The partially exposed silicon dioxide film 104 at this time has a thickness of about 500 Å, so even if the silicon dioxide film 107 is removed by etching, about 800 Å remains. Thereafter, phosphorus is simultaneously thermally diffused through the remaining silicon dioxide film and polycrystalline silicon film to perform thermal oxidation, and the source region 108 and drain region 10
9 and a silicon dioxide film 110 are formed. At this time, since the diffusion coefficient of the silicon dioxide film is smaller than that of polycrystalline silicon, the PN junction depth is shallow under the aforementioned remaining silicon dioxide film, and deeper under the polycrystalline silicon film. The thickness of the remaining silicon dioxide film can also be controlled to a desired thickness by performing oxidation using the silicon nitride film 106 in the previous step as a mask for thermal oxidation. Next, as shown in FIG. 1E, polycrystalline silicon 105
Connection holes with metal wiring are formed on the top, and aluminum wirings 111 and 112 are formed. In the photolithography process for drilling the connection hole, the source region 108
Since polycrystalline silicon 105 is formed on top,
Compared to the conventional technology, the surface is almost uniform, so the problems with photoresist films as mentioned above can be solved, and even minute connection holes can be reliably formed. The effect obtained by the first embodiment is that even minute connection holes can be easily formed. That is, the polycrystalline silicon on the source and drain regions eliminates the concave shape and creates a structure that is substantially flat with other regions, so that the above-mentioned problems of photoresists can be solved. In addition, the spread of the PN junction in the source and drain regions below the gate insulating film is automatically suppressed, making it easier to form short channel transistors, and also reducing the high resistance caused by the shallow depth of the PN junction. can be lowered by the polycrystalline silicon film, and aluminum can penetrate through the diffusion layer.
A polycrystalline silicon film can also prevent PN junction failure. Furthermore, since the surface is almost flat, defects such as disconnections and shorts in the aluminum wiring can be prevented.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention. First, as shown in FIG. 2A, active regions and inactive regions are formed on a P-type silicon single crystal substrate 201 by selective oxidation using a silicon nitride film.
P ⁺ diffusion layer 202 and thick silicon dioxide film 2203
In the active region, a silicon dioxide film 204 of about 500 Å is selectively formed. Thereafter, as shown in FIG. 2B, a polycrystalline silicon film 205 with a thickness of about 5000 Å is formed, followed by selectively covering silicon nitride films 206, 207, and 208 with a thickness of about 000 Å. After diffusing phosphorus into the polycrystalline silicon 205 using the silicon nitride films 206, 207, and 208 as a mask,
Oxidized at 1000℃, silicon nitride films 206, 207,
The polycrystalline silicon in the uncovered region 208 is changed to a silicon dioxide film 209. Since polycrystalline silicon containing phosphorus has a faster oxidation rate than a polycrystalline silicon film that does not contain impurities, it is possible to suppress lateral spread due to oxidation and non-uniformity in the thickness of the polycrystalline silicon film. After that, as shown in FIG. 2D, the polycrystalline silicon film 2 is
The silicon dioxide film 209 formed by oxidizing 05 is etched with a hydrofluoric acid aqueous solution so that a desired thickness remains. In this example, a silicon dioxide film of approximately 300 Å was left. Thereafter, the silicon nitride films 206, 207, and 208 were removed by etching in hot phosphoric acid, and then phosphorus was simultaneously diffused by thermal diffusion through the polycrystalline silicon 205 and the remaining silicon dioxide film 209, as in the first embodiment. perform oxidation,
A source region 210 and a drain region 211 are formed, and a silicon dioxide film 212 is also formed therewith. Thereafter, as shown in FIG. 2E, holes are made in the silicon dioxide film 212 on the polycrystalline silicon, and aluminum interconnections 213 and 214 are formed to complete the process. Second
It is clear that the effects obtained with the embodiments are exactly the same as those obtained with the embodiments of the first part.

In the first and second embodiments, the polycrystalline silicon film is coated with a silicon nitride film, but a silicon dioxide film may be used as needed.

Similar effects can also be obtained by using plasma or sputter etching in various types of etching.

[Brief explanation of the drawing]

1A to 1E and FIGS. 2A to 2E are cross-sectional views showing the manufacturing process of a first embodiment and a second embodiment of the present invention, respectively. In the figure, 101, 201 are silicon substrates, 102, 104, 107, 110, 203,
204, 209 are silicon dioxide films, 103, 202
is P ⁺ diffusion layer, 108, 109, 210, 211
is an n ^- diffusion layer, 105, 205 is a polycrystalline silicon film,
107, 206, 207, 208 are silicon nitride films,
111, 112, 213, and 214 are aluminum wirings.

Claims (1)

[Claims] 1. In a method for manufacturing an insulated gate field effect transistor in an active region of a semiconductor substrate of one conductivity type, a thin silicon dioxide film is deposited on a first portion of the source/drain forming region adjacent to the channel region. , a polycrystalline silicon film is deposited on a second part between the first part and the inactive region, and an impurity of the opposite conductivity type is sourced through the thin silicon dioxide film and the polycrystalline silicon film by thermal diffusion; By introducing it into the drain type region and performing thermal oxidation,
A shallow PN junction is formed in the second part, and a deep PN junction is formed in the second part, and both constitute the source and drain regions. 1. A method of manufacturing a semiconductor device, comprising forming a silicon layer, forming a connection hole in the silicon dioxide layer, and forming a metal wiring that contacts the polycrystalline silicon film through the connection hole.