JPS61281623A - Oscillation frequency adjusting device - Google Patents
Oscillation frequency adjusting deviceInfo
- Publication number
- JPS61281623A JPS61281623A JP60098239A JP9823985A JPS61281623A JP S61281623 A JPS61281623 A JP S61281623A JP 60098239 A JP60098239 A JP 60098239A JP 9823985 A JP9823985 A JP 9823985A JP S61281623 A JPS61281623 A JP S61281623A
- Authority
- JP
- Japan
- Prior art keywords
- vco
- frequency
- signal
- reference signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
印 産業上の利用分野
本発明は、VCO(電圧制御発振器)のフIJ −ラン
周波数を自動的に調整することが出来る発振周波数調整
装置に関するもので、特にIC(集積回路)化に適した
発振周波数調整装置を提供せんとするものである。Detailed Description of the Invention Field of the Invention The present invention relates to an oscillation frequency adjustment device that can automatically adjust the IJ-run frequency of a VCO (Voltage Controlled Oscillator), and particularly relates to an oscillation frequency adjustment device that can automatically adjust the IJ-run frequency of a VCO (Voltage Controlled Oscillator). The present invention aims to provide an oscillation frequency adjustment device suitable for circuit implementation.
(ロ)従来の技術
VTR(ビデオテープレコーダ)の色信号処理回路にお
いては、記録時に色副搬送波を低域変換色信号に変換す
る第1周波数変換回路、及び再生時に低域変換色信号を
色副搬送波に変換する第2周波数変換回路(第1周波数
変換回路と共用される場合もある)を備えている。、そ
れらは、昭和56年11月10日付で日本放送出版協会
から発行されたrNHKホームビデオ技術」第94頁及
び第95頁の図7−22乃至図7−24に記載されてい
るが、例えば記録時の周波数変換回路は、第2図に示す
如き構成となる。第2図において、入力端子(1)に印
加される3、 58 MHzの色副搬送波は、主周波数
変換回路(2)で側周波数変換回路(3)からの4.2
MHzの信号と混合され、出力端子(4)に629KH
zの低域変換色信号が得られる。また、入力端子(5)
には水平同期信号が印加され、該水平同期信号は波形整
形回路(6)で波形整形された後位相比較回路(7)で
VCO(81の出力信号を分局する分局器(9)の出力
信号と位相比較される。前記V CO(81は160f
II (約2.5 MHz )の発振周波数を有fるの
出力端に1f、Iの信号が得られる。前記位相比較器(
7)の出力信号は、誤差信号として前記V CO(81
に印加されるので、前記V CO(8)の発振周波数は
正確に16 Of、 になる。更に前記V CO(81
の16 OfHの出力信号は、分周器(11で1/4に
分周され、移相回路(11)を介して副周波数変換回路
(3)に印加される。この信号は、40f* (62
9Kllz)の周波数となり、カラーバースト信号に応
じて発振器(12+から発生される3、 58 MHz
の信号と混合されるので、副周波数変換回路(3)の出
力端には、4゜2MHzの信号が得られる。(b) Conventional technology In the color signal processing circuit of a VTR (video tape recorder), a first frequency conversion circuit converts a color subcarrier into a low-band converted color signal during recording, and a first frequency conversion circuit converts the low-band converted color signal into a low-band converted color signal during playback. A second frequency conversion circuit (which may be shared with the first frequency conversion circuit) for converting into a subcarrier is provided. , they are described in Figures 7-22 to 7-24 on pages 94 and 95 of ``rNHK Home Video Technology'' published by the Japan Broadcasting Publishing Association on November 10, 1981, for example. The frequency conversion circuit during recording has a configuration as shown in FIG. In FIG. 2, the 3.58 MHz color subcarrier applied to the input terminal (1) is transmitted from the main frequency conversion circuit (2) to the 4.2 MHz color subcarrier from the side frequency conversion circuit (3).
Mixed with MHz signal and output 629KH to output terminal (4)
A low frequency converted color signal of z is obtained. In addition, input terminal (5)
A horizontal synchronizing signal is applied to the horizontal synchronizing signal, and the horizontal synchronizing signal is waveform-shaped by a waveform shaping circuit (6).Then, the horizontal synchronizing signal is waveform-shaped by a waveform shaping circuit (6), and then outputted by a phase comparator circuit (7). The phase is compared with the V CO (81 is 160f
A signal of 1f, I is obtained at the output end of the oscillator having an oscillation frequency of II (approximately 2.5 MHz). The phase comparator (
The output signal of 7) is applied as an error signal to the V CO (81
Therefore, the oscillation frequency of the VCO (8) is exactly 16 Of. Further, the V CO (81
The output signal of 16 OfH is divided into 1/4 by the frequency divider (11) and applied to the sub frequency conversion circuit (3) via the phase shift circuit (11). This signal is 40f* ( 62
The frequency is 3,58 MHz generated from the oscillator (12+) in response to the color burst signal.
As a result, a 4°2 MHz signal is obtained at the output terminal of the sub frequency conversion circuit (3).
し→ 発明が解決しようとする問題点
上述の如く、第2図の回路を用いれば、3.58MHz
の色副搬送波を629KHzの低域変換色信号に周波数
変換することが出来るが、IC化に際してVCO(81
の発振周波数を決定する為の抵抗やコンデンサをIC内
に作成すると、前記抵抗やコシデンサの値のバラツキに
応じて前記V CO(81のフリーラン周波数が変化し
、低域変換色信号の周波数も変化するという欠点があっ
た。その為IC化に際しては、ICの外付ピンを追加し
、該外付ピンに可変抵抗を外付けし、該可変抵抗の値を
調整することにより前記抵抗やコンデンサの値のバラツ
キを吸収しているが、ICにおける外付ピンや外付部品
の増加は好ましいものではなく、何らかの改善が望まれ
ていた。→ Problems to be solved by the invention As mentioned above, if the circuit shown in Fig. 2 is used, 3.58MHz
It is possible to convert the frequency of the color subcarrier of
When a resistor and a capacitor are created in the IC to determine the oscillation frequency of the VCO (81), the free-run frequency of the VCO (81) changes depending on the variation in the values of the resistor and cosidenser, and the frequency of the low-frequency conversion color signal also changes. Therefore, when converting to an IC, it is necessary to add an external pin to the IC, attach a variable resistor to the external pin, and adjust the value of the variable resistor. However, the increase in the number of external pins and external parts in the IC is not desirable, and some kind of improvement has been desired.
−問題点を解決するための手段
本発明は上述の点に鑑み成されたもので、制御信号によ
り発振周波数が制御される第1VCOと、該第1VCO
と略同一の入出力特性を有する第2VCOと、所定周波
数の基準信号を発生する基準信号発生回路と、前記第2
VCOの出力信号と前記基準信号との位相を比較し誤差
信号を発生する比較回路と、前記誤差信号を前記第1及
び第2VCOに共通に供給して前記第1vcoのフリー
ラン周波数の調整を行う手段とを備える点を特徴とする
。- Means for Solving the Problems The present invention has been made in view of the above points, and includes a first VCO whose oscillation frequency is controlled by a control signal, and a first VCO whose oscillation frequency is controlled by a control signal.
a second VCO having substantially the same input/output characteristics as the second VCO; a reference signal generating circuit that generates a reference signal of a predetermined frequency;
a comparison circuit that compares the phase of the output signal of the VCO and the reference signal to generate an error signal; and a comparison circuit that commonly supplies the error signal to the first and second VCOs to adjust the free run frequency of the first VCO. It is characterized by comprising a means.
(ホ)作用
本発明に依れば、比較回路からの誤差信号が第1VCO
に供給されるので、前記第1vcoのフリーラン周波数
が基準信号周波数に応じて正確に設定されるとともに、
前記第1VCOの出力信号の周波数を制御信号に応じた
値にすることが出来る。(E) Effect According to the present invention, the error signal from the comparison circuit is output to the first VCO.
Since the free run frequency of the first VCO is accurately set according to the reference signal frequency,
The frequency of the output signal of the first VCO can be set to a value according to the control signal.
(へ)実施例
第1図は、本発明の一実施例を示す回路図で、0は制御
信号を発生する制御信号発生回路、(141は前記制御
信号が印加される第1VCO1(151は該第1VCO
α4)の出力信号が印加される被駆動回路、(161は
前記第1VCO141と略同一の入出力特性を有する第
zvco、αηは該第2VCO(161の出力信号を分
周する第1分周器、aεは基準信号を発生する基準信号
発生回路、(19は前記基準信号を分周する第2分周器
、■は前記第2VCO(161の出力信号と前記基準信
号との位相を比較し位相差に応じた誤差信号を発生する
位相比較回路、CIIは前記誤差信号を通過させるロー
パスフィルタ、のは該ローパスフィルタのを通過した誤
差信号を前記第1及び第2VCOα滲及びαeに供給す
る信号ラインであり、これらすべて単一のIC基板上に
集積化されている。前記基準信号発生回路aSは、例え
ば3.58MHzの周波数を有する信号を発生させるも
ので、第の信号が位相比較器■に供給される。また、第
1及び第2 V C0(141及ヒ(16)ハ、320
fN、(略5MHz )の信号を発生させるもので、第
1分周器αDで位相比較器■に供給される。従って、前
記位相比較器■の出力端に得られる誤差信号がローパス
フィルタ(211を介して第1及び第2VCOC141
及び(16)に供給゛され、該第1及び第2VCOα4
及び(161の発振、周波数が略5.4MHzにロック
され、前記第1及び第2VCOa滲及び(leのフリー
ラン周波数が5.4MHzになる。更に、第1VCOC
141には、第2図の場合と同様、水平同期信号と前記
第1VCOの出力が制御信号として印加されるので、前
記第1VC’0(141の出力信号は正確に320 f
i になる。(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, where 0 is a control signal generation circuit that generates a control signal, (141 is a first VCO 1 to which the control signal is applied, and 151 is a first VCO 1 to which the control signal is applied). 1st VCO
A driven circuit to which the output signal of α4) is applied, (161 is a ZVCO having substantially the same input/output characteristics as the first VCO 141, and αη is a first frequency divider that divides the output signal of the second VCO (161) , aε is a reference signal generation circuit that generates a reference signal, (19 is a second frequency divider that divides the frequency of the reference signal, and () is the second VCO that compares the phase of the output signal of 161 and the reference signal. A phase comparison circuit that generates an error signal according to the phase difference, CII is a low-pass filter that passes the error signal, and CII is a signal line that supplies the error signal that has passed through the low-pass filter to the first and second VCOs α and αe. All of these are integrated on a single IC board.The reference signal generating circuit aS generates a signal having a frequency of, for example, 3.58 MHz, and the first signal is sent to the phase comparator (2). Also, the first and second V C0 (141 and H (16) C, 320
It generates a signal of fN (approximately 5 MHz), which is supplied to the phase comparator (2) by the first frequency divider αD. Therefore, the error signal obtained at the output terminal of the phase comparator
and (16), and the first and second VCO α4
The oscillation frequency of (161 and
141, the horizontal synchronizing signal and the output of the first VCO are applied as control signals, as in the case of FIG.
Becomes i.
しかして、前記第2VCO(1110のフリーラン周波
数は、前記vcoueがPLL(フェーズψロックド・
ループ)内に配置される為、基準信号発生回路0秒から
の基準信号に正確に対応したものとなり、前記第2VC
O(161のフリーラン周波数を定める為の抵抗−?コ
ンデンサのバラツキは吸収される。そt、−C1前記第
1 V C0(141ハ、前記第2VCO(16iと略
同一の入出力特性を有し、当然抵抗やコンデンサのバラ
ツキ具合も同一となるので、前記第1VCo(141の
フリーラン周波数も前記基準信号に正確に対応したもの
となり、フリーラン周波数の手動調整の必要が全く無い
。また、水平同期信号に対し、基準信号の周波数を十分
大にとっであるので、第1VCO(14)の発振周波数
は、安定な基準信号に応じて支配的に決まり、それに水
平同期信号に応じた制御信号が重畳される形になり、前
記第1vCo(141の発振周波数を所望の値にするこ
とが容易である。Therefore, the free run frequency of the second VCO (1110) is determined by the fact that the vcoue is PLL (phase ψ locked).
Since the reference signal generation circuit is placed in the loop), it accurately corresponds to the reference signal from 0 seconds of the reference signal generation circuit, and the second VC
O (Resistor for determining the free run frequency of 161 -? Variations in the capacitor are absorbed. So, -C1 The first V However, since the degree of variation in the resistance and capacitor is naturally the same, the free run frequency of the first VCo (141) also corresponds accurately to the reference signal, and there is no need to manually adjust the free run frequency. Since the frequency of the reference signal is set sufficiently higher than the horizontal synchronization signal, the oscillation frequency of the first VCO (14) is determined predominantly by the stable reference signal, and the control signal corresponding to the horizontal synchronization signal is determined predominantly by the stable reference signal. are superimposed, making it easy to set the oscillation frequency of the first vCo (141) to a desired value.
第3図は、本発明の具体回路例を示すもので、儲は第1
入力端子−に第1図のローパスフィルタQIJを通過し
た誤差信号が印加される誤差信号供給回路、りは該供給
回路■の第1出力トランジスタ■のコレクタに得られる
出力信号が供給される第2VCO,C2?)は第2入力
端子弼に供給される第1図の制御信号発生回路Uの出力
制御信号と、前記供給回路@の第2出力トランジスタ翰
のコレクタに得られる出力信号とを加算して加算信号を
発生する加算回路、勢は前記加算信号が供給される第1
vcoである。Figure 3 shows a specific circuit example of the present invention.
An error signal supply circuit to which the error signal passed through the low-pass filter QIJ shown in FIG. ,C2? ) is a sum signal obtained by adding the output control signal of the control signal generation circuit U shown in FIG. The adder circuit that generates the addition signal is connected to the first
It is VCO.
入力端子@に誤差信号が印加されると、入力トランジス
タGυに前記誤差信号に応じた電流が流れ電流反転回路
曽で反転された後第1出力トランジスタ内のコレクタか
ら第2 V CO轡の電流源トランジスタ(ハ)及び(
財)のペースに供給される。その為、第2 v C0(
25+の発振周波数は、前記誤差信号に応じたものとな
ろうまた、前記入カドランジスタロυに流れる前記誤差
信号に応じた電流は、前記電流反転回路饅で反転された
後第2出力トランジスタ(至)のコレクタから黒人に供
給され、前記黒人で入力端子(ハ)に印加され差動増幅
回路響で増幅された制御信号と加算されて第1VCOC
30に供給される。When an error signal is applied to the input terminal @, a current corresponding to the error signal flows through the input transistor Gυ, is inverted by the current inverting circuit, and is then transferred from the collector of the first output transistor to the current source of the second VCO. Transistor (c) and (
goods) are supplied at the pace of supply. Therefore, the second v C0(
The oscillation frequency of 25+ will be in accordance with the error signal.Furthermore, the current in accordance with the error signal flowing through the input quadrant transistor υ is inverted in the current inverting circuit and then transferred to the second output transistor ( The control signal is supplied from the collector of the first VCOC to the first VCOC, and is added to the control signal applied to the input terminal (c) of the first VCOC and amplified by the differential amplifier circuit.
30.
その為、第1VCO■の発振周波数は、前記誤差信号と
制御信号との加算信号に応じたものとなる。Therefore, the oscillation frequency of the first VCO 2 corresponds to the addition signal of the error signal and the control signal.
第2VCOに)の出力端子(至)に得られる出力信号は
、第1図の第1分周器αので分周された後位相比較器■
に供給さn、第1VcOfiの出力端子6?)に得られ
る出力信号は、第1図の被駆動回路f151に供給され
る。尚、第1VCOiは第2 V C0(251と同一
の回路構成に付、第2図においては具体回路を省略する
。また、実施例においては、VTRの色信号処理回路に
用いられるVCOについて説明したが、本発明はこれに
限定されるものではなく、IC化される様々なVCOに
適用可能である。The output signal obtained at the output terminal (to) of the second VCO is divided by the first frequency divider α in Figure 1, and then the phase comparator ■
n, the output terminal 6 of the first VcOfi? ) is supplied to the driven circuit f151 in FIG. Note that the first VCOi has the same circuit configuration as the second VCO (251), and the specific circuit is omitted in FIG. However, the present invention is not limited to this, and is applicable to various VCOs that are integrated.
(ト1 発明の効果
以上述べた如く、本発明に依れば、見損回路として使用
される第1VCOと略同一の入出力特性を有する第2V
COを配置し、該第2VCOの発振周波数を基準信号に
より正確に短め、それによって得られる誤差信号を前記
givcoに印加して該′igI VCOのフリーラン
周波数を自動調整しているので、IC化に際しての素子
のバラツキを吸収することが出来、第1VCOのフリー
ラン周波数を所定値に設定することが出来る。特に、第
1vcoの発振周波数を制御信号と誤差信号とによって
定める場合、基準信号の周波数を制御信号の周波数より
も高く設定すれば、前記第1VCOの発振周波数tより
安定にすることが出来る。(G1) Effects of the Invention As described above, according to the present invention, the second VCO which has substantially the same input/output characteristics as the first VCO used as an oversight circuit
The oscillation frequency of the second VCO is accurately shortened by the reference signal, and the resulting error signal is applied to the givco to automatically adjust the free run frequency of the 'igI VCO. It is possible to absorb variations in the elements during the process, and it is possible to set the free run frequency of the first VCO to a predetermined value. In particular, when the oscillation frequency of the first VCO is determined by the control signal and the error signal, if the frequency of the reference signal is set higher than the frequency of the control signal, it can be made more stable than the oscillation frequency t of the first VCO.
第1図は、本発明の一実施例を示す回路図、第2図は従
来のVTRにおける周波数変換回路の一例を示す回路図
、及び第3図は第1図の具体回路例を示す回路図である
。
主な図番の説明
(141−@ I V CO、ttti・a 2 V
COl (181−・・基準信号発生回路、 l・・・
位相比較器、 C!z・・・信号ライン。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a frequency conversion circuit in a conventional VTR, and FIG. 3 is a circuit diagram showing a specific example of the circuit shown in FIG. It is. Explanation of main drawing numbers (141-@ IV CO, ttti・a 2 V
COl (181--Reference signal generation circuit, l...
Phase comparator, C! z...Signal line.
Claims (1)
O、該第1VCOと略同一の入出力特性を有する第2V
CO、所定周波数の基準信号を発生する基準信号発生回
路、前記第2VCOの出力信号と前記基準信号との位相
を比較し誤差信号を発生する比較回路、及び前記誤差信
号を前記第1及び第2VCOに共通に供給する手段を備
え、前記誤差信号により前記第1VCOのフリーラン周
波数の調整を行うことを特徴とする発振周波数調整装置
。(1) First VC whose oscillation frequency is controlled by a control signal
O, a second VCO having substantially the same input/output characteristics as the first VCO;
CO, a reference signal generation circuit that generates a reference signal of a predetermined frequency, a comparison circuit that compares the phase of the output signal of the second VCO and the reference signal and generates an error signal, and a comparison circuit that generates an error signal by comparing the phase of the output signal of the second VCO with the reference signal, and a comparison circuit that generates an error signal. An oscillation frequency adjustment device comprising means for commonly supplying the error signal to adjust the free run frequency of the first VCO using the error signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60098239A JPS61281623A (en) | 1985-05-09 | 1985-05-09 | Oscillation frequency adjusting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60098239A JPS61281623A (en) | 1985-05-09 | 1985-05-09 | Oscillation frequency adjusting device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61281623A true JPS61281623A (en) | 1986-12-12 |
Family
ID=14214406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60098239A Pending JPS61281623A (en) | 1985-05-09 | 1985-05-09 | Oscillation frequency adjusting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61281623A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0282719A (en) * | 1988-09-19 | 1990-03-23 | Sanyo Electric Co Ltd | Oscillating circuit |
US6150887A (en) * | 1996-09-10 | 2000-11-21 | Nec Corporation | PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57181232A (en) * | 1981-04-30 | 1982-11-08 | Fujitsu Ltd | Voltage-controlled oscillator circuit |
-
1985
- 1985-05-09 JP JP60098239A patent/JPS61281623A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57181232A (en) * | 1981-04-30 | 1982-11-08 | Fujitsu Ltd | Voltage-controlled oscillator circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0282719A (en) * | 1988-09-19 | 1990-03-23 | Sanyo Electric Co Ltd | Oscillating circuit |
US6150887A (en) * | 1996-09-10 | 2000-11-21 | Nec Corporation | PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal |
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