JPS6127761B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to machine controls and specifically to low cost machine controls designed to use programmable machine function controllers.

Traditionally, machine function controllers are used to control general machine operations such as power source and motor control, spindle, start/stop, tool change functions, and axial overtravel.

In many cases, input/output devices, such as lights, pushbuttons, readouts, etc., are often mounted on a panel far from the controller. This panel can be located at the main machine control station or at an auxiliary control station (i.e. corresponds to an auxiliary panel). In prior art control systems, these input/output devices are connected directly to the appropriate machine control circuitry by electrical wires. However, such direct wiring substantially increases the cost of the mechanical structure.

The purpose of the present invention is to be able to control a mechanical device using a simple processor, to realize data exchange between the operator panel and the control device with a small number of signal lines, to be low in cost, and to be easily adapted to conventional manually controlled machines. The objective is to provide a machine control device that can SUMMARY OF THE INVENTION It is an object of the present invention to provide a logic processor circuit for controlling a mechanical device by sequentially scanning a sequence of instructions associated with a single bit input state and output state, and for operating on multi-bit data in response to an output state signal. It is an object of the present invention to provide a machine control device having a concurrent data processing circuit for controlling the drive of a mechanical slide by executing arithmetic functions of a stored program. Another object of the invention is to provide a concurrent logic processor circuit that monitors and controls device status signals on a connection bus, a data processing circuit that monitors and controls data signals on a data bus, and a system that monitors and controls device status signals on a connection bus. A machine controller comprising a speed control circuit that modifies speed data in response to a bit signal and an excursion control circuit that modifies the transfer of the speed signal to a mechanical drive in response to multiple bit signals on a data bus. It is to provide. Yet another object of the present invention is to provide a system for controlling a mechanical slide by connecting the previously described simultaneous logic processor circuit and data processor circuit to a remote motion control device and data bus connected to the data processing circuit through an asynchronous motion signal transceiver. An object of the present invention is to provide a machine control device including an interface circuit for transmitting and receiving associated input and output signals.

The apparatus disclosed herein provides a serial data link connecting a remote machine control panel and a controller. Therefore, what used to require hundreds of electric wires now only requires a pair of two cables. Additionally, in the preferred embodiment, a serial data ring is used to serially multiplex the signals provided to the readout device, so that information from the controller can be read in real time without the use of storage elements in conjunction with the readout device. can be displayed.

The apparatus disclosed herein includes circuitry coupled to the controller to generate signals to control operation of the mechanical slide. The preferred embodiment includes elements to increase and decrease the programmed speed and re-record it for use during the next run of the machine cycle.

According to a preferred embodiment of the invention, there is provided an apparatus for controlling a machine having a first device responsive to a first output status signal commanding machine operation. The machine further has a second device for generating input status signals in response to machine operation, and the machine further includes a remotely located input/output device for receiving output data signals and generating input data signals. The machine also includes a movable element that is connected to a drive mechanism. A device according to an embodiment of the invention comprises a controller device including a connection bus for transferring input and output status signals and a data bus for transferring input and output data signals. The controller device further includes a logic processor that executes a stored set of logic instructions in response to input state signals to generate output states. The controller is also connected between the connection bus and the data bus, and executes a set of stored arithmetic instructions in response to one of the input data signal and output data signal asynchronously with the logic processor. Accordingly, a data processor is provided which generates an output data signal and another input status signal. Furthermore, the device of the embodiment has a connection bus and a first and second
An interface device is provided that is connected between the devices and controls the transfer of input and output data signals therebetween. The example apparatus also includes a device connected to the input/output device to serially transfer input data signals and output data signals between the input/output device and the controller device. The apparatus of the embodiment also includes a device responsive to the controller device and connected to the drive mechanism for controlling the operation of the drive mechanism in accordance with logic and arithmetic instructions contained within the controller device.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram showing the basic components of the control system. Machine 10 has at least one
includes two movable elements 12. Element 12 is electric motor 14
The electric motor 14 is responsive to a motor drive circuit 16. The functional operation of machine 10 is controlled by a programmable machine function controller which has as its main components a logic processor 18 and a data processor 20. These elements are the connection bus 2
2 are interconnected. The connection bus 22 is
There is an address bus 32, a single data bit line 46 that specifies the state of the output signals, a single data bit line 38 that specifies the state of the input signals, and a timing control line 44.

The functional operation of the machine is illustrated by a ladder circuit or relay diagram. This figure is programmed into the program device 24.
When used in conjunction with a machine, a logical program is created that determines machine operation. Each step in a typical program includes a device address and associated logic function. A combination of these two pieces of information is defined as a memory word. In a preferred embodiment, device address blocks are assigned depending on the device used, such as external coils, external connection inputs, timers, data processing functions, and other control device related functions. Therefore, the program device 24
By using , the program one selects a starting storage location and works through the ladder diagram in series along each line. Each memory word contains the element's determination, if applicable, e.g. inactive, output, input, device address in the allocation block associated with this element, and any other necessary information related to the state of the addressed device. It also includes functional information, such as the state of the contacts, such as normally open or normally closed. After the program is completed, program device 24 can be used to transfer the program to storage 26 within logic processor 18 via program buffer 28. Timing circuit 30 continuously scans memory 26.

As each memory word is read, a device address is transmitted via address bus 32 to connection bus 22. If the device address indicates an input element,
Input interface device 34 is address bus 3
2 energizes a circuit therein connected to receive the state of a corresponding input device 36 located in the machine in response to the device address. The status of the addressed input device is transmitted via connection status line 38 and connection bus 22 to logic circuitry 40 in logic processor 18. Logic circuit 40 determines whether the actual connection state matches the programmed connection state. As long as the programmed state and the actual state match, logic circuit 40 remains set. If there is a mismatch between the programmed state and the actual state, logic circuit 40 is reset. When scanning a memory word having a device address corresponding to an output coil, output interface circuit 42 decodes the device address.
Additionally, each time logic processor 18 decodes an output element, an output strobe signal is generated on output strobe line 44, which signal is transmitted to output interface circuit 42. logic circuit 4 when the memory word containing the output element is being decoded.
When a zero detects a continuous correspondence between the programmed and actual states of input device 36, logic circuit 40 generates a set state output signal on output state line 46. Output interface circuit 42 stores the state of the output signal on output status line 46 in response to the output strobe signal on line 44. The output signal is output to machine 10 corresponding to the device address decoded by output interface circuit 42.
energizes one output device 48 of. This device remains energized until storage device 26 is next scanned;
Logic circuit 40 determines that the state of the input device associated with this output device does not match the programmed state and generates a reset state output signal on output state line 46. The output devices of the machine 10 are thus controlled as a function of the desired state of the input devices of the machine.

Note that logic processor 18 is only capable of making simple logic decisions. It is optional whether the data processor 20 is connected to the connection bus 22 if the output devices of the machine are to be controlled according to arithmetic functions. A typical data processor includes a program storage device 50, a computing device 52, and a data storage device 54. Program storage 50 contains a number of programs, each having a sequence of microinstructions to perform a desired computational function. As mentioned above, device address blocks are assigned to the data processor to select programs stored therein. The data processor is connected to address bus 32, output strobe signal line 44 and output status signal line 46. When a memory word containing a device address corresponding to one of the stored programs is scanned and the machine is in a state requiring the arithmetic function specified by that program, the logic circuit outputs an output status line. 46. This signal is stored in the data processor in response to the output strobe signal on line 36, and the addressed program begins its execution. If the program requires other data for its execution, this data is stored on the data bus 56.
Obtained from elements connected to. Although not specifically shown, data bus 56 includes address lines, multi-bit data lines, and timing control lines. When an arithmetic function is performed, the data processor has a device address indicating the input device associated with the execution of the arithmetic function. Upon receiving this address, the data processor generates an input signal on line 38 indicating the result of the arithmetic function performed and returns this signal to logic circuit 40.
Note that data processor 20 and logic processor 18 operate asynchronously to each other.

In short, the logic processor 18 is a logic-controlled fixed sequence processor that continuously determines whether or not the desired state of the machine indicated by the memory word matches the actual state of the machine indicated by the input signal from the machine. It is something to monitor. When there is a match, the output device specified by the program is activated. When there is no match, the output device is not energized. As an independent device, logic processor 18 controls many relatively simple mechanical operations. However, a logic processor can only make logical decisions and cannot perform arithmetic operations. A connection bus is connected between a logic processor and a machine and provides for the transmission of only single data bit connection information. When an arithmetic operation is required, the logic processor generates an output signal that is decoded by the data processor and operates to select a stored program of arithmetic instructions in the data processor. A data bus connects the data processor to the machine's data signaling equipment and provides for the transfer of multiple data bits of information therebetween. While the data processor is executing arithmetic instructions, the logic processor continues to perform continuous cycle operations asynchronously. At the time specified by the memory program,
The data processor generates input signals and returns them to the connection bus. These signals are received by the logic processor at some point in its operating cycle when their corresponding device address is generated on the connection bus. The details of the programmable machine function controller are described in Application No. 677712, assigned to the present assignee, and entitled ``Asynchronous Dual Function Multiprocessor Machine Control''
"Function multiprocessor machine control)"
as described in a pending U.S. patent application entitled .
Similar machine controllers are also available in Cincinnati.
Commercially available from Cincinnati milacron Inc.

As mentioned above, the machine includes a movable element 12 coupled to an electric motor 14 that is responsive to a motor drive circuit 16. The motor drive circuit receives a speed signal from the motor control circuit 58 and
8 is responsive to a digital feed rate control circuit 60. The digital feed rate control circuit is responsive to separately assigned address blocks on the address bus 32 and defines the basic functions involved in determining the velocity of the movable element 12. For example, the speed can be increased or decreased. It is also possible to command a fixed speed. Digital feed rate control circuit 60 is also responsive to signals on the data bus and receives data signals indicating the desired magnitude of velocity. This data signal is modified by the input signal received from the connection bus and is returned in its modified state to the data processor. Digital feed rate control circuit 60 applies an analog speed signal to motor control circuit 58 that directly indicates the desired speed of the moving element in response to the data signal indicative of the speed. A motor control circuit 58 is connected to the connection bus and receives an output signal therefrom indicating the direction of movement of the movable element. The measuring device performs some operations when the operation is started and finished. Additionally, motor control circuit 58 receives signals from the data bus indicating the desired displacement of the movable element. The motor control circuit applies appropriate signals to the motor drive circuit 16 in response to the speed signal from the digital feed rate control circuit and the command signal from the connecting bus to effect the desired movement of the movable element. The displacement of the movable element is also controlled by the motor control circuit, and the motor control circuit 58 is operative to stop the movement of the movable element 12 after the desired displacement is achieved.

The machine is also coupled with an input/output panel,
This panel is located remote from the basic machine controller. The input/output panel can be placed anywhere near the machine to provide maximum operator convenience. The input/output panel can contain any number of devices depending on the type of machine and the general purpose of the panel. Only those necessary for explaining the present invention are shown here, and only input/output devices for communicating data information from or to the controller are shown in the figure. The input/output device includes a pushbutton 66, a light 66, and a readout device 68.

Pressing pushbutton 66 generates an alpha, numeric, or function input data signal that is passed through pushbutton interface circuit 84 and external data bus 86 to external data interface circuit 8.
Added to 8. Here, the input data signal is converted to a serial data signal and transferred via line 92 to internal data interface circuit 90. These signals are then transferred to data processor 20 via data bus 56. Similarly, the data processor generates an output data signal which is sent over data bus 56 to internal data interface circuitry 90 where it is converted to a serial data signal. The serial data signals are transferred over line 94 to external data interface circuit 88 which transfers these signals onto external data bus 8.
6 to the read interface circuit 96 and the read device 68, and also to the write interface circuit 71 and the write 65.

Figures 2a and 2b detail the elements necessary to transfer input and output data signals from the data bus to the input/output devices of panel 62 by coupling along connection lines. FIG. 2a shows the internal data interface circuit 90, and FIG. 2b shows the external data interface circuit 8.
8. External data bus 86, specific input/output devices,
and other circuits related to the interface circuit.

Data signals are transmitted between data interface devices by two universal asynchronous receiver/transmitters (UARTs) 102 and 104. These devices are commercially available and operate asynchronously with each other and with other elements in the control system, between which serial data signals are periodically and continuously transmitted. Second
In Figure a, RAM 106 is divided into transmitted signal storage 108 and received signal storage 110. RAM 106 participates in all three cycles of internal data interface circuit operation. First, data signals are transferred from the data processor to RAM 106 via data bus 56. Second, transmit signal storage 108 in RAM 106
A signal is transferred from the UART 102 to the UART 104, and this signal is further transferred to the UART 104. moreover
UART102 receives a signal from UART104,
These signals are transferred to received signal storage 110. Finally, the signal is returned from the received signal storage via data bus 56 to the data processor.

Suppose a data processor wishes to transfer or receive a data signal. In this case, an address is transmitted over the data bus, and the address is decoded by bus address latch circuit 112.
Additionally, the data processor generates a clock signal on data bus 56 which is further input to bus cycle controller 114. The bus cycle controller generates a bus cycle signal on line 116. The bus cycle signal is connected to the data bus 56.
Other control mode operations of the internal data interface circuit are inhibited until information is transferred between RAMs 106. The bus cycle signal is also transferred to the multiplex control circuit of bus address multiplexer 118. The input end of bus address multiplexer 118 is connected to a bus address latch circuit. bus address multiplexer
It is connected to the address input of RAM 106 to select a particular storage location within the RAM corresponding to the address signal generated from the data processor. When the data processor wishes to transfer data to RAM, this data is received on bus line 120. Bus line 120 is connected to data input multiplexer 122. The bus cycle controller generates an input signal on line 124, generates a control signal multiplexed with the bus cycle signal on line 116, and sends this signal to data input multiplexer 122. Additionally, the bus cycle control circuit generates a bus clock signal on line 126 which is connected to gate 128. This gate 128 is connected to the write input of RAM 106. Therefore, depending on the bus clock signal, data is transferred to bus address multiplexer 118.
is transferred to the storage location selected by. The address multiplexer 118 is connected to the received signal storage device 11.
If you select a storage location within 0, RAM10
The output terminal of 6 is connected to the input terminal of data output multiplexer 130. The data output multiplexer has multiple control circuits that transfer data signals from received signal storage 110 to data bus 56 and then to data processor 20 in response to signals generated by bus cycle control circuits. control.

The other mode of operation is the transmit cycle mode.
The output of the delay counter 132 is in an appropriate state,
When a clock 2 pulse is generated from cycle counter 300 on line 134, transmit cycle control circuit 136 generates a transmit cycle signal on line 138. This signal is sent to the sending address counter 14.
0 clock signal. The transmit address counter generates two address signals on lines 142 and 144. The meaning and details of this will be explained later. For our purposes, it is sufficient that the address signals on address lines 142 and 144 indicate unique locations in transmit signal storage 108. These address lines are connected to the inputs of a transmit address multiplexer 150, which has a multiplex control circuit to which the transmit cycle signal is applied. Transmit cycle control circuit 136 also generates a transmit clock signal on line 154, which becomes the clock signal for latch circuit 156, which stores the data signal just selected by transmit address multiplexer 150. where the transmit address counter increments its count value to a value corresponding to the next storage location, the transmit cycle control circuit generates a transmit data strobe signal on line 152;
The UART 102 receives the output of the latch circuit 156 and the currently addressed output of the transmit signal storage 108. In this way the UART
102 is loaded because the data signal is in the form of binary coded decimal (BCD) words. Therefore,
Each byte representing the BCD digits of each data word has a length of 4 bits. UART 102 has the capacity to receive 8 bits for one input strobe. Therefore, two 4-bit BCD digits are loaded each time an input strobe signal is received.

If the internal data interface circuit is not in bus cycle mode and not in transmit cycle mode, UART 102 generates a data available signal on line 157. This signal enables receive cycle controller 158. Control device 1
58 is also responsive to the clock 1 signal on line 160. The receive cycle controller generates a receive cycle signal on line 162 which serves as the clock signal for the receive address counter 164 and is provided to the multiplex control circuitry of the receive address multiplexer 166. The receive address counter generates address signals on lines 168 and 170 which are connected to the inputs of the receive address multiplexer. These signals specify unique storage locations within received signal storage 110. Additionally, the receive cycle controller generates a receive clock 1 signal on line 172. Line 172 is receive data multiplexer 1
74 multiplex control input terminal.
This multiplexer receives four binary bits or BCD digits from the receive output of UART 102. The generation of the clock 3 signal on line 176 from cycle counter 130 causes the BCD digits stored in receive address multiplexer 174 to be written to the storage location in receive signal storage 110 addressed by receive address buffer 166. be included. The received address counter then increments its count value to the value corresponding to the next address, addressing the next storage location in the received signal storage. Here, the receive cycle controller generates a receive clock 2 signal on line 178 which is connected to the multiplex control circuit of receive data multiplexer 180. Data multiplexer 180 operates according to other BCD digits or
Holds the four binary bits in the byte received by UART 102. When the next clock 3 signal is generated on line 176, multiplexer 1
80 transfers this second BCD digit to the storage location in received signal storage 110 currently addressed by receive address multiplexer 166. At the end of the receive cycle, receive cycle control circuit 158 generates a reset data available signal on line 182 connected to UART 102.

Although UARTs 102 and 104 operate asynchronously with respect to each other, the receive address counter and transmit address counter associated with one UART operate synchronously with the operation of the other UART. for example,
When the transmit cycle is completely completed, the transmit cycle signal disappears. A transmit address counter generates a final signal. This signal is UART102
The delay counter 132 is enabled when the generation of the character signal being generated on line 188 is completed. This changes the state of the output of the delay counter provided on line 190, disabling transmit cycle control circuit 136. The delay counter is timed by a baud clock pulse provided on line 192 from cycle control circuit 130. At the end of the first predetermined period, the delayed signal changes its state again, enabling the transmit cycle control circuit 136. When the interface circuit is not in a bus or receive cycle (its operation is then inhibited via gate 194), the transmit cycle control circuit again begins generating the transmit cycle signal and sends this signal to line 138. give. Therefore, UART1
02 continuously and periodically transmits data signals to the UART 104 in accordance with the baud clock signal.
UART 104 has a similar transmit cycle control mechanism and periodically transmits data signals to UART 102. Thus, after the data available signal is generated, this signal disappears from the first predetermined period due to the delayed signal inhibiting the UART 104 transmit cycle. As a result, the reset input of synchronization counter 196 is no longer asserted by the receive cycle on line 162, and synchronization counter 196 is ticked on a second predetermined period after the synchronization signal is generated on line 198. This synchronization signal resets the received address counter 164. After the end of this period, the receive cycle controller 158 operates in response to the next data available signal unless inhibited by the bus cycle signal or the transmit cycle signal via gate 200.

As mentioned above, multiple UARTs transmit data signals serially between them. In FIG. 2b, the external data interface circuit is indicated at 88. When UART 102 begins a transmit cycle, UART 104 generates a data available signal on line 200. clock circuit 202
When a baud clock signal is generated from , flip-flop 204 generates an output signal to AND gate 206 . When UART 104 is not in a transmit cycle, UART 104 generates a transmit buffer empty signal on line 208. clock circuit 20
With the next baud clock signal generated from 2,
Flip-flop 210 generates a reset data available on line 212. This signal is combined with other pokelock signals to the AND gate 21.
6 to generate a data strobe signal on line 214. At this point, address counter 218
generates address signals on lines 220 and 222, and these signals are connected to the flip-flop memory device 2.
24 or latch circuit 226,2
Specify one of 28 and 230. When a data strobe signal is generated on line 214,
The addressed element latches the data signal provided from UART 104 to input bus 232. The reset data enable signal also increments the address counter and provides the new address on address lines 220 and 222. This addressing state continues until the next data available signal is generated.

The data available signal resets the synchronization counter 234. For example, if the data available signal is not generated, the delay counter 132 (FIG. 2a)
prohibits the transceiver 102 from performing a transmitting operation during the first predetermined period, the line 2
No delay signal is generated at 00. Accordingly, synchronization counter 234 maintains the count value during the second predetermined period and generates a synchronization signal on line 236, thereby resetting address counter 218.

Note also that address lines 220 and 222 are connected to the inputs of transmit address multiplexer 240. Therefore, each time the address of address counter 218 changes, the output data signal from pushbutton interface circuit 70 is multiplexed and provided to the transmitting input of UART 104 and further transmitted to UART 102. Since the data available signal on line 200 inhibits counter 132 from performing delay operations, and because the data available signal on line 200 is required to increment the count value of address counter 218, UART 104 Each transmission cycle is delayed from the first predetermined period.

The input data signal is generated by pressing pushbutton 64. The outputs of these pushbuttons are connected to a priority encoder 242, which encoder 242
The first signal as well as the address input is generated at the multiplex control input of pushbutton address multiplexer 244. The pushbutton address multiplexer receives the addresses of activated pushbuttons from the priority encoder 242, multiplexes them, and transmits them to the input of the transmit address multiplexer 240. As discussed above, this device multiplexes these signals and provides them to UART 104.

The write interface circuit 71 includes an address decoder 246, a flip-flop storage device 224,
and optical isolator and its driving circuit 248
It is equipped with When a data strobe signal is generated on line 214, the address decoder decodes the address currently being generated by address counter 218. This address makes a particular storage location in flip-flop storage 224 available. The other end of the data strobe signal causes the input data signal on bus 232 indicating the desired state of the write to be stored in the addressed flip-flop. Each flip-flop in storage device 224 is connected to one of lights 65 by an optical isolator and drive circuit 226.

The read storage device is indicated at 96 in the figure.
Address latch circuit 230 latches the address currently output from address counter 218 in response to data strobe signal 214. This address is decoded by the common line decoder and becomes a signal that energizes a particular common line driver in the common line drive circuit 252 and is used as a signal for energizing a specific common line driver in the common line drive circuit 252.
One of the common lines in 8 is energized. Similarly, 10
Decimal point decoder and latch circuit 218 latches the data output signal on bus 232 and the current address of address counter 218 in response to the data strobe signal. The output of decoder and latch circuit 228 is the input to comparator 254, which compares the new decimal point position relative to the current decimal point position. As a result, after the read time elapses,
The position of the decimal point moves by 1 bit. The output of the comparator is provided to a decimal point driver 256 which outputs an LED readout device 68.
The decimal point display inside is driven. BCD―
Seven segment decoder and latch circuit 226 is responsive to addresses from address counter 218. Data output signal on bus 232 and line 214
The data strobe signal decodes and latches the signals representing the seven segments of the LED to display numerical digits corresponding to the data output signal. LED driver 258 is responsive to decoder and latch circuit 256 to drive the individual numeric displays of LED readout device 68.

Here, the specific address of each pushbutton, light, or readout device is not generated directly by the data output signal output from the data processor, but by the data interface shown in FIGS. 2a and 2b. Note that it is generated by the address counter in the Ace circuit.
In the preferred embodiment, the pushbuttons, lights, and readouts are located at arbitrary row and column locations in a matrix with each location 4 bits deep, so that each location in the matrix has an LED.
Sufficient information may be included to define the numerical value of one digit of the readout device 68. Additionally, each matrix position can define the states of four lights or four pushbuttons. In the preferred embodiment, pushbuttons, lights, and readout devices are assigned to fixed positions in this matrix. Furthermore, the address counter 14
The outputs of 0,164 (FIG. 2a) and 218 (FIG. 2b) contain address signals that individually specify the row and column locations of each matrix location.
Therefore, in FIG. 2a, address line 17
0 and 144 indicate the column address bus, line 16
8 and 142 indicate row address buses. Similarly, in FIG. 2b, address line 220 represents the column address bus and address line 222 represents the row address bus. Furthermore, the address counter 21
At the end of each cycle of 8, each matrix location is addressed and the state of the input/output device associated with all matrix locations is updated.

As is clear from the above explanation, the two
UARTs 102 and 104 operate to periodically transmit information therebetween. The data characters transferred in a particular cycle are determined by the design features of the particular UART involved. However, the number of characters that are transferred is determined by the circuit designer. The data signal discussed here is in binary coded decimal notation, so
In the preferred embodiment, a 64 position BCD matrix is provided. Each information byte is determined by a column number and two consecutive row numbers, so that when specifying each subsequent byte, a pair of consecutive rows are addressed and successive columns are addressed. For numeric readouts, each column of the matrix indicates the decimal magnitude and each row of the matrix indicates the number of reads. The effect of such an addressing scheme is that all the least significant digits of the digit read can be scanned and the digits can be successively moved to the most significant digit. Therefore, on each cycle, the UART multiplexes and transmits new information to the reading device.

The UARTs are driven at a clock speed that allows them to scan the readout device with newly updated information. New information appears dynamically, but the human eye sees old, unchanged information. Multiplexing the readout using multiple UARTs has the advantage of not requiring buffer stages at distant input/output panels. A disadvantage of buffer storage is that incorrect information stored due to noise or other problems may be displayed until the buffer storage is updated. Conversely, if the UART is used for read multiplexing, incorrect information will only be displayed in one UART cycle and will not be visible.

FIG. 3 shows one embodiment of an apparatus for generating an analog signal indicative of a desired velocity of a movable element. Bus interface circuit 260 is connected to data bus 56 and controls data transfer from the data bus to data latch circuit 262. This data is
It is a digital signal that is loaded into a BCD reversible counter 264 and is indicative of the desired velocity magnitude of a moving element of the machine. Under normal circumstances, the counter 264 will hold a constant digital speed signal, or in some conditions the speed will change one or more times during a machine cycle. Using these controls, the logic processor generates address signals on connection bus 22.

Board address decoder 266 generates interrupt enable signals in response to address signals, address decoder 268 decodes these signals into address signals,
The results obtained are transferred to storage, typically flip-flop storage 270. This address enables one flip-flop of the storage device, the input of which will depend on the state of the signal on output status line 46. When an output strobe signal is generated on line 44, the output state is input to the flip-flop selected by the above address. Multiplexing circuit 272 is responsive to the increment signal on line 274 and the reset signal on line 279, and includes a multiplexing control circuit responsive to board address decoder 266. Multiplexer 272 returns the output state of the selected flip-flop of storage device 270 to connection bus 22 via connection status return line 38. Clock gate circuit 278, flip-flop storage 270, and feed rate override clock circuit 28
0 to generate an increment/decrement clock signal on line 282.

Counter 264 increments or decrements the digital value of the desired speed signal in response to the clock signal on line 282 and the increment signal on line 274. When the machine operator energizes the increment or decrement control, the digital counter increments or decrements the count until the movable element reaches the operator's desired speed. multiplexer 288
is connected to the output terminal of the counter 264, multiplexes the digital values of the counter, and provides the multiplexed digital values to the storage device in the data processor via the data bus.
When the machine operator changes the programmed speed, the new speed is sent back to the data processor.
Replaced with original programmed speed. Thus, once the operator has set the speed to optimum values during one cycle of machine operation, these optimum values will operate effectively during subsequent machine cycles of operation.

Digital-to-analog converter 290 generates a DC signal in response to the digital speed signal from counter 264 and transmits this signal to acceleration/deceleration control circuit 2.
Give to 92. A voltage controlled oscillator generates a pulse train representing a motor clock signal on line 304 in response to the DC signal. Acceleration/deceleration control device 292
is connected to acceleration/deceleration logic circuit 294.
The purpose of these two circuits is to control the change from one DC level to another in response to programmed speed changes.

As will be apparent to those skilled in the art, the use of voltage controlled oscillators in conjunction with acceleration/deceleration circuits to obtain speed signals is well known. The details of the oscillator and acceleration/deceleration control circuit are determined by the function of the machine to be controlled and the desired operation. here,
A detailed explanation of the voltage controlled oscillator and the acceleration/deceleration control circuit will be omitted.

The maximum speed counter 296 is connected to the output terminal of the oscillator 295 and operates so that no output is generated from the oscillator when the oscillator output frequency exceeds a predetermined value. Time counter 298 is responsive to clock circuit 300 and provides a load signal to speed counter 296. This load signal is sent to the speed counter 29
6 is loaded with a predetermined number indicating the maximum desired frequency (speed) of oscillator 295. Under normal conditions, the maximum speed counter 296 is
Counter 296 reloads the maximum number into it in response to the load signal before it reaches zero as soon as possible to count the output of . However, if for some reason the output of oscillator 295 suddenly has to take on a large value that exceeds the desired maximum value, the count value of the maximum speed counter will be becomes zero due to the output of In such a situation, the maximum speed counter provides an inhibit signal to gate 302 and line 304 inhibits the motor clock signal from being generated. The maximum speed counter is then reset by a reset signal generated by the operator, and the count value is transmitted via connection bus 22 to flip-flop storage 270.

FIG. 4 is a detailed block diagram showing the elements necessary to control the displacement of the movable elements of machine 10. Commands relating to the general operation of the movable elements are converted into single bit digital signals and transmitted via connection bus 22 to board decoder 306. The board decoder decodes the address on line 32 and provides an interrupt enable signal to address decode 308 and a multiplex control signal to multiplexer 310. A flip-flop storage device, more preferably storage element 312, is connected to address decoder 308;
Enable one of the flip-flops in the storage device. The input to this flip-flop is controlled by the output on line 46 and is pulsed to the flip-flop by an output strobe signal on output strobe line 44. multiplexer 310
transmits the clocked flip-flop output state via connection status return line 38 to the connection bus. Storage device 312 generates a forward/reverse signal on line 314, an inch/meter signal on line 316, and a start/stop signal on line 3.
Occurs on the 18th.

AND gate 320 is responsive to a start/stop signal on line 318, a motor clock signal on line 304, and an in-position signal on line 322. This gate controls the transmission of the motor clock signal to the motor drive circuit and the displacement control circuit described above.
Address decode and counter circuit 326 is connected to the data bus and generates a first signal that controls the loading of BCD counter 324 along with a data signal indicative of the desired displacement of the movable element. Address decoding and counter circuit 326 is multiplexer 3
28 provides another input to the multiplex control circuit 28 and returns the contents of the BCD counter to the data processor via data bus 56.

Resolution control circuit 330 is responsive to the inch/meter signal on line 316 and the motor clock signal from gate 320 to modify the motor clock signal to be a preselected function of resolution. B.C.D.
The clock input of counter 324 is connected to the output of resolution control circuit 330 to reduce the count value by the number contained therein under the action of the motor clock signal. A zero decoder 332 is connected to the output of the BCD counter 324 and generates an in-position signal when the counter value decreases to zero. The inposition signal generated on line 332 is connected to an inhibit circuit of counter 324, which in turn is connected to gate 320 to inhibit the motor clock signal from being transmitted to the motor drive circuit.

The motor clock signal is a pulse train whose frequency represents the desired speed and each pulse represents an increase in displacement. Therefore, by counting pulses,
BCD counter 324 can measure the commanded displacement of the movable element. The above pulse is BCD
Before being clocked into counter 324, resolution control circuit 330 modifies the frequency of this pulse train and changes the scale that BCD counter 324 uses to measure commanded displacement. Although shown for inch/meter resolution only, resolution control circuit 330 can also be used to modify the frequency of the motor clock signal to obtain typical resolutions.

In the preferred embodiment, electric motor 14 is a step motor. Therefore, the motor clock signal output from the oscillator is a pulse train. Additionally, step motors of the type used here require a four-phase divider 334;
Divider 334 connects the motor clock signal to line 3.
14 forward/reverse signals. Optical isolator 3
36 connects the four-phase divider 334 to the motor drive device 16
used for electrical isolation from Those skilled in the art will appreciate that various other modifications to the position and speed controls may be made depending on the type of motor used to drive the moving element. The stepper motor and its associated speed and displacement circuit shown here are merely examples, and the invention is not limited to this type of motor, its displacement control circuit, and speed control circuit.

Returning to FIG. 1, the last circuit will be explained. In some applications, logic processor 18
may be required to send and receive data signals. To this end, intercommunication circuit 64 communicates data signals between data bus 56 and connection bus 22 by converting single bit data signals to multiple bit data or vice versa. Specifically, this is accomplished by interconnecting two bus interface circuits. In FIG. 3, the data bus interface circuit is the bus interface circuit 26.
0, a data latch circuit 262, and a multiplexer 288. The connection bus interface circuit includes a board address decoder 266;
It includes an address decoder 268, a flip-flop storage 270, and a multiplexer 272. Intercommunication circuit 64 also includes the elements described above, but these elements are similar to data latch circuit 2.
62 is connected to the input of multiplexer 272, and the output of flip-flop storage 270 is connected to the input of the multiplexer.

The effects of the present invention will be described below. (1) Whereas hundreds of wires were traditionally used to exchange data between a remote operator panel and control equipment, the use of asynchronous data transceivers allows data to be exchanged using a much smaller number of signals. (2) a serial data link is used to sequentially multiplex the signals applied to the readout device, so that the control can be realized at low cost; (3) The machine control device of the present invention includes a programmable logic processor for controlling all cycles of operation and for controlling the drive of the mechanical slide. (4) The program executed by the processor can be implemented by a simple processor having independently programmable data processing circuitry, but which is basic to the programmable logic processor and the data processing circuitry; Defining the actions to be performed based on the conditions and data signals generated by selected switches on the machine and the operator, the control of the slide can be manually set and operated in response to which processor (5) Since the present invention provides an economical machine control having a basic and simple slide control circuit, it can replace conventional automatic control for manually controlled machines. It is also easy to adapt.

Although the preferred embodiments of the present invention shown in the accompanying drawings have been described in detail above, the present invention is not limited to such detailed description, and the present invention includes all matters described in the claims and within the spirit thereof. This includes variations, permutations, and equivalents.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a machine control system, and FIGS. 2a and 2b show input and output data from a data bus to input/output devices of a remote machine control panel by being coupled to each other along connection lines. FIG. 3 is a detailed block diagram showing the equipment needed to transmit the signals in series; FIG. 3 is a detailed block diagram showing the equipment needed to generate a velocity signal indicative of the desired velocity of the moving element; FIG. 1 is a detailed block diagram showing the equipment necessary to control displacement; FIG. Explanation of symbols, 10...Machine, 12...Movable element, 16
...Motor drive circuit, 18...Logic processor, 20
...Data processor, 22...Connection bus, 26...Storage device, 34...Input interface device, 42
...Output interface device, 50...Program storage device, 52...Arithmetic unit, 60...Feed rate control circuit, 65...Light, 66...Push button, 68...
Reading device, 88... external data interface circuit, 90... internal data interface circuit.

Claims (1)

[Claims] 1. A first I/O device including a first output device 48 that operates in response to an output status signal that commands a machine operation, and a first input device 36 that generates an input status signal in response to the machine operation. 36, 48, and a first circuit 260, 262, 26 for generating a speed signal representative of a desired speed of a movable element mechanically coupled to the drive mechanism.
4,290,295 and a second circuit 306-320,334 for converting a speed signal to control a drive mechanism that deflects a movable element in response to the speed signal;
336, 16, the machine generates input data in response to output data;
8, 60, and 62, and is characterized in that it includes the following (a), (b), (c), and (d). (a) a programmable machine function controller including the following (a), (b), (c), and (d); (b) a connection bus 22 for transferring said input and output status signals; (b) said input and output data; a data bus 56 for transferring signals; (c) a logic processor 18 connected to the connection bus 22 and executing a stored set of logic instructions in response to the input status signals and generating the output status signals; (d) A processor connected between the connection bus 22 and the data bus 56 and operating simultaneously and asynchronously with the logic processor 18 to output the data indicated by the input data signal in response to the selected output status signal. a data processor 2 for executing a stored set of arithmetic instructions using a data processor 2 to generate an output data signal and another input status signal;
0, (b) an interface circuit 34 connected to the controllers 22, 56, 18, 20 and controlling the transfer of the input and output status signals between the 1 I/O devices 36, 48 and the connection bus 22; , 42, (c) a speed control circuit 266, 268, 270, 2 within the second I/O device that increases or decreases the magnitude of the speed signal in accordance with the signal from the connection bus 22;
72, 278, 280, 292, 294; O deviation control circuits 324, 326, 328, 330, 332 in the device, (a) the data bus 56 and the second circuit 30;
a down counter circuit 324 connected to said second circuit 306-320, 334, 6-320, 334, 336, 16 and storing a deflection signal representative of the desired deflection of the movable element;
a down counter circuit 324 having a clock input for causing the stored deviation signal to be decremented by the speed signal in response to signals from 336, 16; and (b) the down counter 324 and the second circuit 306. - 320, 334, 336, 16, and generates a proper position signal in response to the output of a down counter circuit 324 that decrements the deviation signal to zero, thereby generating a proper position signal.
06-320, 334, 336, 16, a zero decoder 332 for stopping the movement of the movable element in response to the proper position signal. 2. According to claim 1, the first circuit comprises an up-down counter (26) storing a digital speed signal in response to a signal from the connection bus (22).
4, and a digital-to-analog converter 29 connected to the counter 264 and generating an analog speed signal.
0, the speed control circuits 266, 268,
270, 272, 278, 280, 288, 29
A machine control device characterized in that No. 2,294 further comprises the following (a), (b), and (c). (a) a first storage device 270 for storing command signals representing changes in the speed of the movable element in response to signals from the connection bus 22; (b) a clock signal for storing command signals in response to signals from the first storage circuit 270; (c) a clock signal source 278, 280 having an input to generate the up-down counter 264 and an output connected to the up-down counter 264 so that the digital speed signal in the counter is modified as a function of the command signal; A control circuit 292, 294 having an input for controlling the rate of change of the analog velocity signal in response to the signal and thereby providing acceleration and deceleration control to the movable element. 3 In paragraph 1 of the claims, the following (a) and (b)
and the second I/O device 58, 60, 62
the second I/O devices 58, 60 .
62 and the controllers 22, 56, 18, 20
interface circuits 86, 88, for serially transferring the input and output data signals between the
A machine control device comprising: 90. (b) Disposed in the second I/O device 58, 60, 62, this second I/O device 58, 60, 6
transmitting the output data signal to 2;
an external bus 86 for transmitting input data signals from the second I/O devices 58, 60, 62, and (b) an external bus 86 connected between the external bus 86 and the data bus 56,
18, 20, and periodically transmit the input data signal and the output data signal between the two buses by converting the input and output data signals into first and second serial data signals, respectively. Communication circuits 88, 9 transmitting to
0. 4. The machine control device according to claim 1, wherein the logic processor 18 further comprises the following (i) and (ii). (i) a memory device 26 for storing a sequence of logical instructions defining the desired state of the input state signal necessary to generate the output state signal; (ii) an output from the memory device 26 and the input state signal; a logic circuit 40 responsive to the output status signal for generating the output status signal when the actual status of the output status signal of the connection bus 22 matches the desired status of the input status signal stored in the storage device 26; 5. A machine control device according to claim 1, wherein the data processor 20 includes the following (i), (ii), and (iii). (i) a program storage device 50 that selects a storage program for arithmetic instructions in response to one of the output status signals; (ii) a data storage device 54 that stores a data signal; (iii) the storage program and the data signal. and operates according to the input data signal to execute the arithmetic instruction simultaneously and asynchronously with the logic processor 18 to generate the output data signal;
a computing unit 52 for making the further input status signal available on the connection bus 22 for use by the logic processor 18; 6. A machine control device according to claim 3, wherein the communication circuits 88, 90 include the following (i), (ii), (iii), and (iv). (i) The second I/O device 5 operates asynchronously with the controller 22, 56, 18, 20;
(ii) a first transceiver 104 disposed with 8, 60, 62 for periodically transmitting the first serial data signal and receiving the second serial data signal for multiplexing; 104 and is connected between the first transceiver 104 and the data bus 56 to periodically transmit the second serial data signal and transmit the first serial data signal for multiplexing. a second transceiver 102 for receiving; (iii) the first transceiver 104;
and the external bus 86, the first multiplexing circuit 202, 20 controls the transfer of the output data signal and the input data signal between the first transceiver 104 and the external bus 86.
4,210,218, operating in each cycle of said first transceiver 104 and said second I/O device 58,6;
a circuit 240 operative to transfer all input data signals from the first transceiver 104 to the first transceiver 104; A third circuit 202, 204, 210, 21 operates so that all output data signals are transferred to two I/O devices 58, 60, 62.
8,226,228,230, (iv) including the following: connected between the second transceiver 102 and the data bus 56, and for transferring input data signals and output data signals therebetween; The second multiplexing circuit 108, 110, 136, 140, 15 that controls
0,158,164,166,174,11
2, 114, 118, 122, 130, a transmission signal storage device 108 that stores the output data signal, a reception signal storage device 110 that stores the input data signal, and a transmission signal storage device 110 that stores the input data signal; a transmit cycle control circuit 13 operative to transfer all output data signals from the transmit signal storage device 108 to the second transceiver 102 during each cycle of the transmitter 102;
6,140,150, a receive cycle control circuit 158,1 responsive to the second transceiver 102 and operative to transfer all input data signals from the second transceiver 102 to the received signal storage device 110;
64, 166, 174, 180, and the controller 2 via the data bus 56.
2, 56, 18, 20 to the transmitted signal storage device 108, and the received signal storage device 1
10 to the controller 22, 56, 1
a cycle control circuit 112, 114, 1 that controls the transfer of the input signal to 8, 20;
18, 122, 130. 7 In claim 6, said second I/
The second I/O device 58 , 60 , 62 further comprises a pushbutton 66 for generating said input data signal, a light 65 and a readout device 68 for receiving said output data signal, and for receiving said second I/O device 5 .
8, 60, 62 and the external bus 86 for transferring the input data signal and the output data signal.