JPS6127754B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to digital display circuits.

In recent years, with the spread of microprocessors, many unique products have been created in the fields of measurement equipment, computer-end equipment, etc. If we consider the characteristics of these devices, we can point to the miniaturization of devices through the use of microprocessors, diversification of functions, and increased complexity. Therefore, the display section, which can be called the face of the device, needs to be devised to present more information in a limited space. Liquid crystals have come into use.

For example, LED numeric displays are small, have a long life, and have simple drive circuits, so they have been used in many devices. These are measuring instruments,
Measurement results, input information, etc. are displayed temporarily, and when new data is generated, the old data is deleted and the new data is displayed.

Now, as devices such as system devices become more complex and are operated by being connected to many other devices, the incidence of failure increases. Therefore, the types of failures and the number of causes increase, and if each was displayed using a lamp or LED display, the cost would increase and the equipment itself would have to be larger. Therefore, recently, a method has been used in which various factors that cause these failures are coded, and when a failure occurs, the coded numbers are displayed on a common number display.
This not only increases the efficiency of space usage, but also
The user can be made aware of even the finer details, making maintenance easier.

The present invention thus provides a simple and useful digital display circuit for displaying a plurality of coded numbers.

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To achieve this objective, the present invention comprises a first counter that calculates the number of write pulses and generates a write address signal, and a second counter that counts a constant frequency clock and generates a read address signal. a comparator that generates a clear signal to the second counter based on the result of comparing the values of the write address signal and the read address signal; and a comparator that generates a clear signal to the second counter based on the result of comparing the values of the write address signal and the read address signal; With a configuration including a memory capable of storing and simultaneously outputting data at a read address corresponding to the read address signal, as many data as the number of write pulses are displayed on the same display at the same cycle. It is designed to be displayed.

An embodiment of the present invention will be described below based on the drawings. FIG. 1 shows a configuration example of the present invention, in which up to 16 two-digit numbers can be sequentially displayed using two LED numeric displays. FIGS. 2 and 3 show timing waveforms during writing and reading, respectively.

The first write pulse WT causes the output WFF of the flip-flop 1 to become "H". Further, the write pulse WT passes through an integrator circuit consisting of a resistor 5 and a capacitor 6 and an inverter 4, and then passes through a memory 10.
Give the write signal WTi to. Also write pulse
WT is while the output WFF of flip-flop 1 is present.
Write clock pulse through NAND gate 2
It is input to counter 3 as WCL. Since the outputs WA to WD of the counter 3 are initially "0", the write data WD0 to WD7 (DATA0) sent at the same time as the first write pulse WT are
It is written to address “0” in memory 10. When the second write pulse WT comes, the flip-flop output WFF is “H”, so the NAND
The output WCL of the gate 2 becomes "L", and the write address outputs WA-WD of the counter 3 become "1".
Therefore, the second write data (DATA1) is written to address "1" of the memory 10. In this way, the write data (DATAN) sent to address N is sequentially written to address N-1 of the memory 10.

On the other hand, the oscillator 7 generates a clock φ with a constant period.
is constantly generated and sent to the counter 8. The outputs RA to RD of the counter 8 are read addresses of the memory 10. The memory 10 is always in the read mode, independent of writing, and the read data RD0 to RD7 are sent to the decoder drivers 11 and 1.
2 and is constantly displayed on the LED numeric displays 13 and 14.

Now, in memory 10, there are 4 pieces of data (DATA0), (DATA1), (DATA2), (DATA3).
Assume that has already been written. At this time, the outputs WA to WD of the counter 3 are "3". Comparator 9 compares the values of outputs WA~WD of counter 3 and outputs RA~RD of counter 8, and when the value of RA~RD becomes larger, a clear signal is sent to counter 8.
SCL is sent, and RA to RD change values from "0" to "3" at the cycle of clock φ, so
(DATA0), (DATA1) (DATA2) (DATA3)
The numbers will be sequentially displayed on the LED numeric displays 13 and 14 at the same cycle. Also, the reset signal
By applying RST to flip-flop 1 and counter 3, it is possible to return to the initial state.
In Figure 1, there are four address designation signals, so
Up to 16 pieces of data can be stored from addresses "0" to "15" and displayed sequentially.

According to the present invention, for example, up to 16 two-digit numbers can be sequentially displayed. Furthermore, it is extremely easy to increase the number of display data and the number of display digits by increasing the number of counters and memories. Therefore, any number of data can be displayed periodically but simultaneously using the same display.

One use of the present invention is to display errors in system equipment using microprocessors.
When an abnormality occurs in the system, the code numbers of the elements causing the abnormality are written in sequence to notify the user. The display will be repeated periodically unless it is reset, so the user will not be able to overlook it.
All failure causes can be recognized, making maintenance easier.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure shows a timing diagram when writing according to the present invention, and FIG. 3 shows a timing diagram when reading according to the present invention. 1...Flip-flop, 3, 8...Counter, 7...Oscillator, 9...Comparator, 1
0...Memory, 13,14...LED numerical display〓〓〓〓〓
WT...Write pulse, WA~WD...Write address signal, RA~RD...Read address signal, SCL
...Clear signal. 〓〓〓〓〓

Claims (1)

[Claims] 1. A first counter that calculates the number of write pulses and generates a write address signal, a second counter that calculates a clock of a constant frequency and generates a read address signal, and a counter that calculates the number of write pulses and generates a read address signal. a comparator that generates a clear signal to the second counter based on the result of comparing the values;
a memory capable of storing display data at a write address corresponding to the write address signal in response to the write pulse, and at the same time outputting data at a read address corresponding to the read address signal, the number of which is equal to the number of the write pulses. What is claimed is: 1. A digital display circuit characterized in that the data of the following are displayed on the same display device at the same period.