JPS61276357A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To increase the integrating rate of static RAMs, etc., by providing with resistor regions in connecting holes, and by connecting directly the upper and lower wiring layers by the resistor regions. CONSTITUTION:Transistors Q11-Q14 constitutes a flip-flop, in which the transistors Q11, Q12 serve as drivers, and the transistors Q13, Q14 serve for the puspose of switching. Through the inter-layer insulating film INS betwen the upper wiring VDD and the lower wiring, the connecting holes H11, H12 are formed in which high relative resistance material R12, R12 such as poly-Si having a small amount of O and N, or N added is buried, in order to connect the electrode wiring patterns L1A and L1B. In this way, the integrating rate can be increased, the stray capacitance owing to the load resistors R11, R12 can be minimized, and the device can be speeded up.

Description

[Detailed Description of the Invention] [Summary] By providing a resistance region in a contact hole and directly connecting the upper and lower electrode wiring layers with the resistance region, an SRAM is produced.
Improve the degree of integration of semiconductor devices such as

[Industrial application field]

The present invention relates to the structure of a semiconductor device applied to a static random access memory (hereinafter referred to as SRAM), and particularly relates to a resistor formation technique.

[Conventional technology]

Conventionally,! A technique called "resistor-on-transistor" is generally applied to iRAM cells. Figure 4 shows an isometric circuit diagram of a resistive loaded SEAM cell, and Figure 5 shows a conventional "resistor, on transistor" circuit diagram.
φ represents a pattern diagram of a resistive load SRAM cell portion realized by φ. In FIGS. 4 and 5, the same parts are indicated by the same reference numerals.

In FIG. 5, the pattern seen from the top side of the resistive load cell is shown. The thick line frame is formed on the semiconductor substrate and is marked by a 9% diffusion region, and the diagonal line area is the electrode wiring layer on the semiconductor substrate.
The region marked with many dots is the second wiring layer, and the region marked with vertical lines is the third wiring layer. In the second wiring layer, transistors Q1. Q2
Load resistors R1 and R2 are formed. R1+R
2 is a through hole Hs (black rectangular frame (corresponding to connection node No.)
The other end of R1 is in contact with the switching transistor Qs, the tangential node N of the F/F transistor Q1, and the gate of the transistor Q2 through a through hole H1. The other end is in contact with a connection node NB of the switching transistor Qa, the drain of the F/F transistor Q2, and the gate of the transistor Q1 through a through hole H2t.

In addition, in FIG. 4 and FIG. 5, WL is a word line of EIRAM, and Bit and Bit are bit lines.

VDD and van represent high and low power supply lines.

In this way, conventionally, a load resistor Rl + R is placed above a field effect transistor formed on a semiconductor substrate and bonded.
If the area occupied by the load resistor Rj + R2 itself is small (as compared to the lower field effect transistor region), it is effective in reducing the cell area.

[Problem that the invention seeks to solve]

However, due to advances in the semiconductor device manufacturing process associated with the increase in the capacity of SRAMs, the area of the lower field effect transistor has been reduced and has become equal to or smaller than the load resistance, and the area of the load resistance area has decreased. has become a problem.

Furthermore, in the "resistor-on-transistor", there is an insulating film between the lower field effect transistor and the upper load resistor, and the stray capacitance between them has a negative effect on the speeding up of SRAM.

In the "ta, r resistor-on-transistor" structure, at least three contact holes are required for the load resistance, and when considering large-capacity semiconductors, the larger the number of contact holes, the lower the yield. Become.

[Means for solving problems]

In the present invention, when looking at the structure of an SRAM, one of the load resistors is always connected to the power supply line, and there is an insulating film between the power supply line and the field effect transistor, and a contact hole is provided for the connection. This was done by focusing on the necessity of forming the load resistance region of the 11RAM directly in the contact hole.

[Effect]

According to the above, since the load resistance can be formed to the size of the contact hole, the degree of integration of the EIRAM is improved.

Furthermore, stray capacitance due to load resistance can be reduced, high-speed operation can be achieved, and the number of contacts can also be reduced.

Further, as the resistance material formed in the contact hole, a high resistance material that has a higher specific resistance and is more stable than the conventional polycrystalline silicon can be used.

〔Example〕

Figure 1 shows an SRAM pattern according to an embodiment of the present invention [6], which is a plan view seen from above the substrate, and the pattern indicated by the thick line frame is the % diffused layer on the substrate. Butter 7 is the electrode wiring pattern on the substrate; double octagonal part @, and ■ indicate ohmic contact with the type 5 diffusion layer, and the pattern with vertical lines is the upper wiring layer. W
L represents the word line s Bs t + B *
1 is a complementary bit line, mVss is a low power supply line + 1'DD is a high power supply line.

FIG. 2 shows a cross-sectional structure taken along line 0A-A' in FIG. 1. FIG. 5 shows an isometric circuit for the SRAM cell of FIG.
This is a 4-transistor static memory circuit. In FIGS. 1 to 3, the same parts are indicated by the same reference numerals.

To explain from Figure 1, Q111Q12 is a flip
Driver transistor and Q+s+ forming 70 tubes
Q1a is a switch/gutra/distor (see Figure 3). Contact holes H11, ff+2 (represented as INS in Figure 2) are formed in the interlayer insulating film between the vDD line of the upper layer wiring and the wiring of the lower layer, and a resistive material is embedded as shown in Figure 2. ing. As this resistance material, a small amount of oxygen, nitrogen acid, carbon, etc. (1~5X10 asa
2) Doped polycrystalline S (etc.) is used, but it is not limited to this, and any stable high specific resistance material can be used.Resistance R11 of the contact hole formed with these resistance materials and R1, the electrode wiring pattern 7L1 and LlB are connected, respectively.

Although one embodiment has been described above, the upper and lower electrodes to which the resistor is connected may be made of a low-resistance material such as a diffusion layer or metal; Any other location may be used as long as a contact hole can be formed therebetween.

〔Effect of the invention〕

As is clear from the above, the present invention provides the following effects.

(2) The area required to form the load resistor may be the same as that of a contact hole, making it possible to improve device density.

■ Minimizing the stray capacitance caused by load resistance can also increase the speed of the device.

■ There is no need to secure wiring m to form a resistor. Since the number of contacts can also be minimized, yield can be improved.

[Brief explanation of drawings]

FIG. 1 is a pattern diagram of an SRAM according to an embodiment of the present invention. Figure 2 is a sectional view taken along line 0A-A' in Figure 1, Figure 3 is an equivalent circuit diagram of Figure 1, Figure 4 is a circuit diagram of a resistive load SRAM cell, and Figure 5 is a diagram of a conventional resistive load SRAM cell. It is a pattern diagram. Rt+ l R+2...Resistor Hn+R12 (formed in the contact hole)...Contact hole Qn~Q14
...Transistor yss...Low power supply line VDD...High power supply line

Claims (1)

[Claims] 1. A semiconductor element region formed on a semiconductor substrate, a first electrode wiring layer connected to the semiconductor element region, a second electrode wiring layer formed on the upper layer, and a first electrode wiring layer connected to the semiconductor element region. 1. A contact hole formed in the insulating film between the first and second electrode wiring layers is filled with a high specific resistance material, and the high specific resistance material includes an insulating film between the first and second electrode wiring layers. A semiconductor device characterized in that first and second electrode wiring layers are connected by a material. 2. In the semiconductor element region formed on the semiconductor substrate,
A field effect transistor is provided with source and drain regions, and has a gate electrode that is a part of the first electrode wiring layer between the source and drain regions, and the field effect transistor is a drive transistor constituting an inverter. A semiconductor device according to claim 1, characterized in that: 3. Claim 2, characterized in that two of the inverters are flip-flop connected to each other.
1. Semiconductor device described in Section 1. 4. The semiconductor device according to claim 3, wherein a transfer field effect transistor is connected to each of the flip-flop connected inverters to constitute a memory cell.