JPS61276269A - Hetero-junction type field-effect transistor - Google Patents

Abstract

PURPOSE:To manufacture a high-speed transistor having not only an enhancement mode but also depletion mode characteristics by adding an extremely thin GaAs-doped layer in several dozen Angstrom or less through a method, through which an n-type GaAs layer is formed into an undoped AlGaAs layer, or a method, etc. through which a GaAs layer holding an n-type planar doped layer is shaped. CONSTITUTION:Undoped GaAs 2 is laminated on a semi-insulating GaAs sub strate 1. An undoped AlGaAs layer 3 is laminated in approximately 200Angstrom . The mixed crystal ratio (x) of Al in the AlGaAs layer is selected in 0.4. An undoped GaAs layer 8 is laminated to 10Angstrom , and silicon is doped in a planar manner. The quantity of surface-doping of a planar doped layer 9 is selected in 5X10<11>-1X10<12>cm<-2>. The undoped GaAs layer 8 is grown in 10Angstrom again, and the undoped AlGaAs layer 3 is grown on the layer 8 in 300Angstrom . Lastly, an n<+>-GaAs (impurity concentration N0=5X10<17>cm<-3>) layer 4 is grown in 0.1mum, thus completing the formation of an element section.

Description

Detailed Description of the Invention [Summary] A GaAs/AlGaAs heterojunction is used to create a crystal region (GaAs) where electrons travel and a crystal region (GaAs) which supplies electrons.
Many field-effect transistors have been developed that utilize the high electron mobility of GaAs by spatially separating GaAs from GaAs to reduce the influence of impurity scattering of electrons. Among these heterozygous FET families, the present invention uses S
We have improved the IS type FET.

[Industrial application field]

The present invention relates to improvements in field effect transistors (FETs) using GaAs/AlGaAs heterojunctions.

When a donor is introduced into the stacked heterostructure of ultra-thin GaAs and ultra-thin AlGaAs, the supplied electrons are confined in the GaAs layer, which has a strong electron affinity.

At this time, the movement of electrons in the direction perpendicular to the film surface is prohibited, so the two-dimensional electron gas (2D dimensional electron gas) has a degree of freedom only in the direction along the film surface.
It is known that Ga5=2DEC) is formed.

On a semi-insulating substrate, undoped GaAs, n-AlGaAs doped with silicon, and n-GaAs are stacked,
HEMT is known as a HEMT that utilizes 20EG supplied from the n-AlGaAs layer to the heterointerface with the undoped GaAs layer.

On the other hand, it is known that if a sufficiently strong electric field can be applied to the interface of the AlGaAs/GaAs heterojunction, a 2DEG can be formed at the interface even if the AlGaAs layer is not doped with donors. S
I S (Sem1 conductor I n5u
la-tor Semiconductor) type FE
It is announced as T.

The present invention relates to this SIS type FET structure. In the conventional SIS structure, the threshold voltage always has a positive characteristic, and the threshold voltage is O1 or F, E, which has a negative characteristic.
Efforts are being made to improve the T.

[Conventional technology]

The cross-sectional structure of a conventional SIS type FET will be explained with reference to FIG.

A semi-insulating GaAs substrate 1 is coated with an undoped GaAs layer 2 of about 1 μm, and then an undoped AlGaAs layer of about 500 μm thick is coated on the semi-insulating GaAs substrate 1.
It is racially stratified. Further, an n''-GaAs layer 4 of 0.1 μm is laminated as a contact layer for the gate electrode 5. After introducing impurities into the source and drain contact regions, a source electrode 6 and a drain electrode 7 are formed to complete the transistor. .

The energy band diagram at this time becomes negative as shown in FIG. FIG. 4(a) shows the state when no voltage is applied to the gate electrode, and FIG. 4(b) shows the state when a positive voltage is applied to the gate electrode.

It is clear from the figure that in the state of gate voltage vc"0, GaAs
Since 20EG is not formed at the /AlGaAs hetero interface, no drain current flows.

Only when VG becomes >0.3 to 0.4v, 2DEC is formed at the hetero interface, and the drain current begins to flow.

[Problem that the invention seeks to solve]

In the conventional SIS FET structure described above, if a positive voltage is not applied to the gate voltage, no drain current flows and the threshold voltage of the FET always takes a positive value.

Therefore, in terms of FET characteristics, the SIS type always operates in enhancement mode.

There is a need for a technology that can freely control the threshold voltage of the SIS type structure and manufacture depletion mode FETs.

[Means for solving problems]

The above problem is caused by the undoped A of the conventional SIS FET.
This problem is solved by adding the following n-doped layer to the structure of the lGaAs layer.

That is, this problem can be solved by forming an n-type GaAs layer within the undoped AlGaAs layer, or by adding an extremely thin GaAs doping layer of several tens of angstroms or less by forming GaAs layers sandwiching an n-type planar doping layer.

[Effect]

By providing a very thin n-type doped layer as described above, even when the gate voltage is 0, the bottom of the conduction band in this layer is lower than the Fermi level at the hetero interface.

By adopting such an energy band structure, 2DEG is supplied to the hetero interface to form an n-type channel layer.

By controlling the amount of n-type planar doping or the position of the doped layer from the hetero interface, the threshold value of the FET characteristics can be selected to a desired value.

〔Example〕

An embodiment according to the present invention will be described in detail with reference to the drawings. 1st
Although the figure is a cross-sectional view of the structure, explanations of the same reference numerals used in the section of the prior art will be omitted.

The process of laminating undoped GaAs 2 on the semi-insulating GaAs substrate 1 remains unchanged.

Next, about 200 undoped AlGaAs layers 3 are formed. The mixed crystal ratio X of AI in the AlGaAs layer is selected to be 0.4.

Next, after stacking 10 undoped GaAs layers 8,
Planar dope silicon. The planar doping amount in the planar doped layer 9 is selected to be 5.times.10.sup.11 to 1.times.10"cm.sup.-".

Again, 10 layers of undoped C, aAsli 8 are grown, and 300 layers of undoped AlGaAs layer 3 are grown thereon. The X value of the AlGaAs layer in this case is also 0.
．． It is selected as 4.

Finally, n”-GaAs (impurity concentration No = 5xlO'7
The formation of the element portion is completed by growing the layer 4 (cm-') to a thickness of 0.1 μm.

FIG. 2 shows an energy band diagram of the above-described FET having the structure of the present invention at gate voltage vG=0. v of conventional SIS structure
Similar to 6>0, band bending can be generated between the hetero interface and a 2DEC channel layer is formed at the hetero interface.

As a FET characteristic, it is also possible to make the threshold voltage negative.

In the present invention, the doping amount of the planar doped layer 9 and the Al
By controlling the doping position within the GaAs layer 3, it is possible to freely control the threshold value of the FET characteristics.

〔Effect of the invention〕

As explained above, by using the heterojunction field effect transistor having the structure of the present invention, a high-speed transistor with FE and T characteristics not only has enhancement mode characteristics like the conventional SIS type, but also has depletion mode characteristics. becomes possible.

[Brief explanation of drawings]

Fig. 1 is a structural cross-sectional view of a heterojunction field effect transistor according to the present invention, Fig. 2 is an energy band diagram of the present invention, Fig. 3 is a structural cross-sectional view of a conventional SIS type FET, and Fig. 4 (al, (b)
shows the energy band diagram of the SIS type FET. In the drawings, 1 is a semi-insulating GaAs substrate, 2.8 is an undoped GaAs layer, 3 is an undoped AlGaAs layer, 4 is an n''-GaAs layer, 5 is a gate electrode, 6 is a source electrode, 7 is a drain electrode, and 9 is a drain electrode. The n-type planar doping layer is shown respectively.

Claims (1)

[Claims] An undoped GaAs layer (2) and then an undoped AlGaAs layer (3) are laminated on the substrate (1), and on the AlGaAs layer (3), an n-type GaAs layer (4),
Alternatively, the gate electrode (5) is formed by stacking metals, and the undoped GaAs layer (2) and the undoped AlGaA
In a field effect transistor in which a two-dimensional electron gas at the heterojunction surface with the s-layer (3) is used as a channel layer, an n-type GaAs layer or a GaAs layer sandwiching an n-type planar doping layer (9) within the undoped AlGaAs layer. (8)
A heterojunction field effect transistor characterized by being provided with.