JPS61276252A - CMOS semiconductor device - Google Patents
CMOS semiconductor deviceInfo
- Publication number
- JPS61276252A JPS61276252A JP60117112A JP11711285A JPS61276252A JP S61276252 A JPS61276252 A JP S61276252A JP 60117112 A JP60117112 A JP 60117112A JP 11711285 A JP11711285 A JP 11711285A JP S61276252 A JPS61276252 A JP S61276252A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type
- well
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
- H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は相補型ＭＯ８半導体装置（以下ＣＭＯＳトラン
ジスタという）に関し、特に高耐圧を有するＮチャネル
ＭＯ８）ランジスタの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MO8 semiconductor device (hereinafter referred to as a CMOS transistor), and particularly to the structure of an N-channel MO8 transistor having a high breakdown voltage.
従来、０ＭＯ８）ランジスタを構成するＮチャネルＭＯ
Ｓトランジスタは第２図に示すように、Ｎ型基板１０に
Ｐウェル９が形成され、Ｐウェル９内に深さ約０．５〜
１．０μのソース拡散層１．ドレイン拡散層２．チャネ
ルストッパー７が配置され、そして厚さ約３００〜８０
０人のゲート酸化膜１２上に厚さ４０００〜７０００人
のポリシリコンのゲート電極３が形成され、絶縁層とし
て厚さ約１μのフィールド酸化膜８及びゲート電極を覆
う厚さ約２００〜１０００人の酸化膜１１が形成された
構造となっている。Conventionally, 0MO8) N-channel MO constituting a transistor
As shown in FIG. 2, in the S transistor, a P well 9 is formed in an N type substrate 10, and a depth of approximately 0.5 to
1.0μ source diffusion layer1. Drain diffusion layer 2. A channel stopper 7 is arranged and has a thickness of approximately 300-80 mm.
A polysilicon gate electrode 3 with a thickness of 4,000 to 7,000 µm is formed on a gate oxide film 12 of 0 µm, and a field oxide film 8 of about 1 µm in thickness as an insulating layer and a field oxide film 8 with a thickness of about 200 to 1,000 µm covering the gate electrode. The structure has an oxide film 11 formed therein.
ＮチャネルＭＯ８）ランジスタは、０ＭＯ８トランジス
タ回路内において、Ｐウェル９及びソース拡散層１に対
しドレイン拡散層２に十の電圧が印加され、ゲート電極
３の電位を変化させることによシ、動作させることがで
きる。The N-channel MO8) transistor is operated by applying a voltage of 10 to the drain diffusion layer 2 with respect to the P well 9 and the source diffusion layer 1 and changing the potential of the gate electrode 3 in the 0MO8 transistor circuit. be able to.
上記従来構造のＮチャネルＭＯＳトランジスタを有する
０ＭＯ８ＩＣは、５ｖ以下の電源ラインで使用されるの
が一般的であるが、最近２０Ｖ程度の耐圧を有する０Ｍ
Ｏ８ＩＣが要求されてきている。しかしながらこの様な
高耐圧の０ＭＯ８ＩＣは下記の理由によシ従来構造での
実現は難かしい。The 0MO8IC having the N-channel MOS transistor of the conventional structure is generally used in a power supply line of 5V or less, but recently the 0MO8IC has a withstand voltage of about 20V.
O8IC is required. However, it is difficult to realize such a high voltage 0MO8 IC with a conventional structure for the following reasons.
α） ドレイン耐圧を上げるためドレイ／接合を深くす
ると、ドレイン逆バイアスのとき空乏層がソース側にま
で伸び、耐圧が低下する。そのためチャネル長を大きく
とる必要があシ、微細化ができない欠点がある。α) If the drain/junction is deepened to increase the drain breakdown voltage, the depletion layer will extend to the source side when the drain is reverse biased, reducing the breakdown voltage. Therefore, it is necessary to have a large channel length, and there is a drawback that miniaturization is not possible.
（２） ドレイン逆バイアスの場合、ドレインのゲート
酸化膜直下で電界が集中し、ホールがＰウェル内に注入
される。この注入電流が多くなるとソース、Ｐウェルビ
レ４フ間でｎｐｎバイポーラトランジスタの動作が生じ
、大電流によシ素子の破壊が起る欠点がある。(2) In the case of drain reverse bias, the electric field concentrates directly under the gate oxide film of the drain, and holes are injected into the P-well. If this injection current increases, the operation of the npn bipolar transistor occurs between the source and the P-well bottom 4, which has the drawback of causing destruction of the silicon element due to the large current.
本発明の目的は上記欠点を除去し、高耐圧のＣＭＯＳ半
導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a CMOS semiconductor device with high breakdown voltage.
本発明のＣＭＯＳ半導体装置はＰウェル領域に形成され
たＮ型のソース拡散層及びドレイン拡散層と、このソー
ス拡散層を囲んでＰウェル領域内に形成されたＰ＋型拡
散層と、ドレイン拡散層の少くともチャネル領域側に形
成されたＮ−型拡散層とを含んでなるＮチャンネルＭＯ
Ｓトランジスタを有するものである。A CMOS semiconductor device of the present invention includes an N type source diffusion layer and a drain diffusion layer formed in a P well region, a P+ type diffusion layer surrounding the source diffusion layer and formed in the P well region, and a drain diffusion layer. an N-type diffusion layer formed at least on the channel region side of the
It has an S transistor.
次に、本発明の実施例について図面を診照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第１図において、Ｎｉ基板１０上には表面濃度が５Ｘ１
０”個／ ｃｍ３程度のＰウェル６が形成されておシ、
このＰウェル６内にはＮ型のソース拡散層１及びドレイ
ン拡散層２が形成されている。そしてこのソース拡散層
１はＰウェル６よシ高濃度のＰ＋型拡散層４（表面濃度
〜１×１０１６個／ａｍ３）で囲まれており、一方ドレ
イン拡散層２は低濃度のＮ−型拡散層５（表面濃度〜１
×１０個／ｃｍ）とケート側で接続されている。In FIG. 1, the surface concentration on the Ni substrate 10 is 5X1.
P-wells 6 of about 0"/cm3 are formed,
In this P well 6, an N type source diffusion layer 1 and a drain diffusion layer 2 are formed. The source diffusion layer 1 is surrounded by a P+ type diffusion layer 4 with a higher concentration than the P well 6 (surface concentration ~1 x 1016 atoms/am3), while the drain diffusion layer 2 is surrounded by a low concentration N- type diffusion layer 4. Layer 5 (surface concentration ~1
×10 pieces/cm) and connected on the gate side.
尚、ソース拡散層１及びドレイン拡散層２の深さは０．
３〜１．０μ、Ｐ＋型拡散層４の深さは１．０〜３．０
μ、Ｎ−型拡散層５の深さは１．０−２．０μである。Note that the depth of the source diffusion layer 1 and the drain diffusion layer 2 is 0.
3 to 1.0μ, the depth of the P+ type diffusion layer 4 is 1.0 to 3.0μ
The depth of the .mu., N- type diffusion layer 5 is 1.0-2.0 .mu..
また、ソース拡散層１とドレイン拡散層２０間のチャネ
ル長は３〜５μでアシ、チャネル部において、ソース拡
散層１のゲート側ｌ端部からＰ＋型拡散層４のゲート下
Ｉ縁端までの距離は１．０〜３．０μ、ドレイン拡散層
２のゲート側ｌ端部からＮ−型拡散層５のゲート下Ｉ緑
端までの距離は１．０〜３．０μに構成されている。In addition, the channel length between the source diffusion layer 1 and the drain diffusion layer 20 is 3 to 5 μm. The distance is 1.0 to 3.0 .mu., and the distance from the gate side l end of the drain diffusion layer 2 to the gate lower I green end of the N- type diffusion layer 5 is 1.0 to 3.0 .mu..
このように構成された本発明の実施例によれば次のよう
な改良点がある。According to the embodiment of the present invention configured as described above, there are the following improvements.
α） Ｎ−型拡散層５によシトレイン耐圧を上げること
ができる。α) The N-type diffusion layer 5 can increase the cytrain breakdown voltage.
■ 従来構造ではドレイン拡散層２とＰウェル９による
接合が逆バイアスされると空乏層は殆んどＰウェル９側
に伸るが、本発明による構造においては、Ｎ−型拡散層
５側にも空乏層が伸びるためチャネル長を長くせず高耐
圧化が可能となる。■ In the conventional structure, when the junction between the drain diffusion layer 2 and the P-well 9 is reverse biased, the depletion layer mostly extends toward the P-well 9 side, but in the structure according to the present invention, the depletion layer extends toward the N-type diffusion layer 5 side. Also, since the depletion layer is extended, high breakdown voltage can be achieved without increasing the channel length.
（３） 更にソース側のＰ＋型拡散層４が、上記空乏
層のストッパーとして働く。(3) Furthermore, the P+ type diffusion layer 4 on the source side acts as a stopper for the depletion layer.
（４） ドレイン側からホールがＰウェル内に注入さ
れた場合、Ｐ＋型拡散層４によりホールを吸収すること
ができる。(4) When holes are injected into the P well from the drain side, the holes can be absorbed by the P+ type diffusion layer 4.
以上説明した様に１本発明によればＮチャネルＭＯＳト
ランジスタの高耐圧化が可能とな夛、２０Ｖ程度の耐圧
を有するＣＭＯＳ半導体装置が得られるのでその効果は
大きい。As explained above, according to the present invention, it is possible to increase the withstand voltage of an N-channel MOS transistor, and a CMOS semiconductor device having a withstand voltage of about 20V can be obtained, which is highly effective.
第１図は本発明の一実施例の断面図、第２図は従来のＣ
ＭＯＳ半導体装置の断面図でおる。
１・・・・・・ソース拡散層、２・・・・・・ドレイン
拡散層、３・・・・・・ゲート電極、４・・・・・・Ｐ
＋型拡散層、５・旧・・Ｎ 型拡散層、６・・・・・・
Ｐウェル、７・・・・・・チャネルストッパー、８・・
・・・・フィールド酸化Ｌ ９・・・・・・Ｐウェル、
１０・・・・・・Ｎ型基板、１１・・・・・・ゲート絶
縁膜、１２・・・・・・ゲート酸化膜。FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a conventional C
It is a sectional view of a MOS semiconductor device. 1... Source diffusion layer, 2... Drain diffusion layer, 3... Gate electrode, 4... P
+ type diffusion layer, 5, old...N type diffusion layer, 6...
P well, 7...Channel stopper, 8...
...Field oxidation L 9...P well,
10...N-type substrate, 11...Gate insulating film, 12...Gate oxide film.
Claims (1)
イン拡散層と、該ソース拡散層を囲んでＰウェル領域内
に形成されたＰ＾＋型拡散層と、前記ドレイン拡散層の
少くともチャネル領域側に形成されたＮ＾−型拡散層と
を含んでなるＮチャンネルＭＯＳトランジスタを有する
ことを特徴とするＣＭＯＳ半導体装置。An N-type source diffusion layer and a drain diffusion layer formed in the P-well region, a P^+-type diffusion layer surrounding the source diffusion layer and formed in the P-well region, and at least a channel of the drain diffusion layer. A CMOS semiconductor device comprising an N-channel MOS transistor including an N^-type diffusion layer formed on a region side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117112A JPS61276252A (en) | 1985-05-30 | 1985-05-30 | CMOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117112A JPS61276252A (en) | 1985-05-30 | 1985-05-30 | CMOS semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61276252A true JPS61276252A (en) | 1986-12-06 |
| JPH0344425B2 JPH0344425B2 (en) | 1991-07-05 |
Family
ID=14703712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60117112A Granted JPS61276252A (en) | 1985-05-30 | 1985-05-30 | CMOS semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61276252A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02307272A (en) * | 1989-05-22 | 1990-12-20 | Matsushita Electron Corp | Semiconductor device |
| WO1996032747A1 (en) * | 1995-04-12 | 1996-10-17 | National Semiconductor Corporation | Structure and fabrication of mosfet having multi-part channel |
| US6020227A (en) * | 1995-09-12 | 2000-02-01 | National Semiconductor Corporation | Fabrication of multiple field-effect transistor structure having local threshold-adjust doping |
-
1985
- 1985-05-30 JP JP60117112A patent/JPS61276252A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02307272A (en) * | 1989-05-22 | 1990-12-20 | Matsushita Electron Corp | Semiconductor device |
| WO1996032747A1 (en) * | 1995-04-12 | 1996-10-17 | National Semiconductor Corporation | Structure and fabrication of mosfet having multi-part channel |
| US5744372A (en) * | 1995-04-12 | 1998-04-28 | National Semiconductor Corporation | Fabrication of complementary field-effect transistors each having multi-part channel |
| US6078082A (en) * | 1995-04-12 | 2000-06-20 | National Semiconductor Corporation | Field-effect transistor having multi-part channel |
| US6576966B1 (en) | 1995-04-12 | 2003-06-10 | National Semiconductor Corporation | Field-effect transistor having multi-part channel |
| US6020227A (en) * | 1995-09-12 | 2000-02-01 | National Semiconductor Corporation | Fabrication of multiple field-effect transistor structure having local threshold-adjust doping |
| US6127700A (en) * | 1995-09-12 | 2000-10-03 | National Semiconductor Corporation | Field-effect transistor having local threshold-adjust doping |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0344425B2 (en) | 1991-07-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |