JPS61274537A - Time division communication system - Google Patents

Abstract

PURPOSE:To store effectively the communication having a small holding time by setting a prescribed number of communication channels within a time division communication network in the 1st period and then using these set channels to perform communication of a prescribed number of user information. CONSTITUTION:A transmitter 1 gives the time division multiplex to the transmission data given from transmission terminals 11...13 in a frame cycle T and performs the transmission control of data for each multi-frame cycle (N1+N2)T. A selection circuit 113 for transmission terminal receives N pieces of address information (N>=2) from a transmission buffer 112 in a period N2T and then receives N pieces of user information from a transmission buffer 12 in a period N2T. Then the time division multiplex signal is sent to a transmission line 3 from a multiplexing circuit 14. While a receiver 2 leads the reception signals to a synchronizing circuit 25 and a separating circuit 27. The address information is sent to a development control circuit 26 from the circuit 27. Then the user information is sent to a developing circuit 24. The user information on transmission terminals 11-13 are received by receiving terminals 21 and 23 since the address and user information supplied to the circuit 24 correspond to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time division communication system that provides communication from a transmitting end to a receiving end.

(Prior art and its problems) There are two typical communication systems that provide communication from a transmitting end to a receiving end. One is to set up a line between the sending end and the receiving end to perform communication, and the other is to add address information to user information and convert it into a packet for communication. The former communication system is disclosed in US Pat. No. 4,253,179 [Time Division Digital Switching System (Time Division Digital Switching System)].
divisj-on digital switch
ng system) J. In such a communication system, a communication path is set up by circuit switching control, and the setting and restoration of such a communication path, that is, a line, is carried out by a central control unit each time in response to a request from a transmitting end. This example is suitable for providing communication that has a fixed bandwidth and has a long hold time, such as telephone communication. That is, 54kb/
It is sufficient to set up the line s between the transmitting end and the receiving end, and since the holding time is long, the throughput of the communication system does not decrease significantly even if the processing for setting up and restoring the line takes time. However, it is not suitable for providing large-capacity communications or communications with short hold times. For example, IMb/
The sending end and receiving end that want to communicate with S are 64kb/s.
16 line ports must be provided, making the communication system complex and large-scale. Furthermore, if the holding time becomes shorter and becomes equal to or less than the processing time for setting up and restoring the line, throughput will decrease.

In contrast, IEEE Qlobal Telecommunications Conference Record Globecom'83 (IEEE Qlobal Teleco-
communications conference R
The paper “Asynchronous Triggered Packet Loop Four-Wideband Mant Multiple Services is Communications (A 5ynchron
ously Lr-rigged packet 1
oop for wideband and multi
ple 5 services communicat
There is a packet communication system described in J. ions) J. In such a communication system, address information identifying the receiving end is added to the user information of the sending end, and the information is exchanged. Although this packet switching system can efficiently provide communication in various bands, it takes time to assemble packets at the transmitting end and disassemble them at the receiving end, resulting in delays unlike telephone communications. Not suitable for accommodating restricted communications.

(Objective of the Invention) It is an object of the present invention to provide a communication system that can set up a communication path at high speed and efficiently accommodate communication with a short holding time.

Another object of the present invention is to provide a communication system that accommodates communication in various bands.

Still another object of the present invention is to provide a communication system that integrates real-time communication such as voice and standby communication such as data.

Another object of the present invention is to provide a communication system that can shorten delay time for real-time communication.

(Structure of the Invention) The time division communication system of the present invention has a period Ts (-'f I
+T! ) Communication control is performed for each. During the first period TI, each transmitting end transmits address information after acquiring the right to transmit. Based on this address information, the communication network
N time-divided communication channels are set. At the transmitting end, the time or time slot number at which the transmission right was acquired is stored and held. On the other hand, at the receiving end, the received time or time slot number is stored and held. In the second period T2, the transmitting end transmits user information based on the stored and retained communication channel setting information, and the receiving end also receives user information based on the communication channel setting information.

A transmitting end that wants to perform large-capacity communication occupies a plurality of communication paths to perform communication. In addition, real-time communication acquires the transmission right with priority over waiting-type communication during period TI.

(Example) First, an example in which the present invention is implemented in a multiplex transmission device will be described.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The multiplex transmission device in this figure is transmitter 1. It consists of a receiving device 2 and a transmission line 3. The transmitting device 1 has transmitting ends 11, 12 .
13 and a multiplexing circuit 14. Synchronous circuit 15. It consists of a multiplex control circuit 16. The synchronous circuit 15 receives a control signal 151
The selection circuits 113, 12 of the transmitting ends 11, 12 and 13
3,133 selection inputs are controlled. Sending end 1
An address circuit 111 and a transmission buffer 112 are connected to the input of the first selection circuit 113. Transmission end 12.13
has a similar configuration. FIG. 2 shows the multiplex control circuit 16.
Show details. This multiplex control circuit 16 has a counter 16
4° control memory 162. It is composed of a processor 163.

The operation of the transmitter 1 having the above configuration will be explained with reference to diagram 1X3. The transmitting device 1 has a Breme period T
The transmission data from each transmitting end is time-division multiplexed and transmitted, and transmission control is performed in units of multi-frame periods (N+Nt)'r. That is, address information is transmitted during the period NIT, and the period N! User information is transmitted at T. The synchronization circuit 15 supplies a control signal 151 to the selection circuit of each transmitting end in order to separate the period N=T and the period NT (FIG. 3(a)). Selection circuit 1 of transmitting end 11
13 selects the output of the address circuit 111 when the level of the control signal 151 is 1, and selects the output of the transmission buffer 112 when the level is 0. During the period N=T, the address circuit 111 sends out address information ADI that specifies the receiving end or the pair of the sending end and the receiving end, and during the period N and T, the sending buffer 112 sends the user information IN.
Send out F.

Now, the frame period T is 100 usec, it consists of eight 8-bit time slots, one of which is used for the synchronization signal, and the multiframe period is 1 m5ec and t, N--.
2, N1-8. Therefore, if one time slot is allocated in a multi-frame period, user information of up to 8 bits X Ni - 64 bits can be transmitted. Therefore, by using m time slots, up to 64m bits of user information can be sent. In a certain multi-frame period, the processor 163 shown in FIG. 2 allocates one, two, and four time slots to the transmitting ends 11, 12, and 13, respectively, and as shown in FIG. The transmitting end 11 is connected to the memory cell of the corresponding control memory 162.
．． 1213 address U 1. U2. Write U 3. In this figure, SYN is the address of the synchronization circuit 15, which is fixedly written in the control memory 162. The counter 164 operates with a period T, and the control memory 162 outputs the address of the transmitting end written in each time slot. This output control signal 161
is applied to the control input of multiplexing circuit 14. The control signal 161 at this time is shown in FIG. 3(b).

The synchronization circuit 15 performs transmission in the first time slot of each frame, sends out a multiframe synchronization signal MF in the first frame of a multiframe, and sends out a frame synchronization signal F in other frames. The transmitting end 11 performs transmission in the second time slot. Address information A in the first N-(-2) frames of the multiframe
The user information INFOL is sent in N (-S) frames after sending out the DI. The signal on the transmission line 3 at this time is shown in FIG. 3(C).

16-bit address information AD bow! 8-bit ADH and ADI! It is divided into 64-bit user information INFO and 8-bit INF...
-, INFH@ and sent in a period NzT. FIG. 3(d) shows the relationship between the address information AD=, the user information INFO-, and the signal frame on the transmission path 3 that is time-division multiplexed and sent out.

Transmission using one time slot has been described above, but when transmitting twice as much user information as this, two time slots are used for transmission. Transmission of multiple information will be explained using transmission by the transmitting end 12 as an example. 128
Bit's INFOR is INF=・Kamo INF Yuki・Yi...
・It is divided into 16 8-bit data of INF river and INFH art, and the period N! T, using the third and fourth time slots of each frame. In this case, the address information ADI is AD! l and A D * s and 2
It is divided into 8-bit data and sent during the period NIT, but in the 3rd and 4th time slots of the first frame, the AD
Send out laziness*. The same holds true when transmitting four times as much user information as from the transmitting end 31. That is, 256 bits of I
NFO3 has 32 8-bit data INF'In=,
lNFm1H, -, INFIS=lNl;'ms is divided and sent at will, and 16-bit address information AD8 is
The data is divided into DS Otori and AD Kawako, and sent out as shown in FIG. 3(d).

Next, the receiving device 2 will be explained. In the receiving device 2, the input signal on the transmission line 3 is supplied to a synchronization circuit 25 and a separation circuit 27. The synchronization circuit 25 detects the multi-frame synchronization signal MF and the frame synchronization signal F. The separation circuit 27 supplies address information of the signals on the transmission line 3 to the expansion control circuit 26 and user information to the expansion circuit 24.

Details of the expansion control circuit 26 are shown in FIG. counter 26
4 is initialized by a control signal 251 based on the multi-frame synchronization signal MF detected by the synchronization circuit 25. Output 265 of the counter outputs is the control memory 2
65 address input, and performs address control. On the other hand, the output 263 has a multi-frame period (N=
Give periods NIT and NIT out of 10Nz)'r. A control output 263 is supplied to a control input of the separation circuit 27 and controls the separation of address information and user information. The separated address information 271 is supplied to the expansion control circuit 26, and the user information 272 is supplied to the expansion circuit 24.

The control output 263 is also supplied to the expansion circuit 24, and the period N=
At T, the expansion circuit 24 is placed in a prohibited state.

In the expansion control circuit 26 of FIG.
2 is in the writing state in the period NIT according to the control output 263, and the period N! Press T to start reading. Therefore, the period NI
Address information 271 is input at T, and control memory 2
Address information corresponding to each time slot is stored in 62 memory cells as shown in FIG. Period NIT
Then, the stored address information is read out every time slot with a period T, and is sent to the expansion circuit 24 as a control signal 261.
supplied to Since the address information supplied to the expansion circuit 24 and the user information supplied from the separation circuit 27 correspond, the user information from each transmitting end is received by a predetermined receiving end 21, 22, 23.

In this embodiment, the delay time for continuous communication such as voice communication will be explained using FIG. 7.

The voice PCM has a period T (-125
usec). The generated voice PCM is transmitted over the period NET as user information. This is shown in the same figure (b)
Shown below. At the receiving end, the signal is returned to an audio PCM sequence with a constant interval T, as shown in FIG. 3(C). As a result, the delay time of the audio signal can be reduced to (NI+1)·T.

Now, since it is set to Nl-2, it becomes 375 usec.

For conventional packet transmission, time (NI+N2+1)
- Since there is a delay of T, that is, 1125 usec, the delay time can be shorter than that of conventional packet transmission.

In this embodiment, since address information can be changed in a multi-frame cycle, switching of lines for multiplex transmission can be performed at high speed. Furthermore, by occupying a plurality of time slots, transmission of multiple pieces of information can be realized.

A second embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 shows a transmitter used in this embodiment. In the first embodiment, the processor 163 controlled multiple lines, but in this embodiment, each transmitting end is distributed. The system performs such control.

The transmitting end 11 includes a control section 114, and this control section 114
controls the address circuit 111, and notifies the multiplexing control circuit 16 of a transmission request via the control line 115 when data to be transmitted arrives at the transmission buffer 112. The transmitting end 12.13 also has the same configuration, and the control lines 125, 1
35 to notify the transmission request. The multiplexing control circuit 16 inputs transmission requests from the transmitting ends 11, 12, and 13, and outputs the address of the transmitting end that is granted transmission permission.
5 and counter 164. It is composed of a control memory 162.

The arbiter 165 enters the operating state only for the first frame of each multi-frame by the control signal 153 of the synchronization circuit 15 shown in FIG. It becomes a dashi state. Suppose that requests to transmit user information of 64 bits, 128 bits, and 256 bits are made to the transmitting ends 11, 12, and 13, respectively. The counter 164 is initialized by the control signal 152 shown in FIG. 9(b), and the counter 165 outputs the address SYN of the synchronization circuit 15. This output address is supplied to the multiplexing circuit 14 via the control line 161 and written into the control memory 162 which is in the write state.

Since counter 164 has been initialized, address SYN is written at the location shown in FIG.

At the same time, the transmission line 3 is transmitted from the synchronization circuit 15 to the multiplexing circuit 14.
A multi-frame synchronization signal MF is sent out.

From the next time slot, the arbiter 165 starts controlling transmission permission to each transmitting end. First, an address Ul is output to the transmitting end 11 to permit transmission. This is also written into the 27th cell of the control memory 162 and simultaneously supplied to the multiplexing circuit 14, and the transmitting end 11 receives the address information A.
Send DII.

The length of the user information to be transmitted by the transmitting end 11 is 64 bits, which is the length that can be transmitted by occupying one time slot for one multiframe. Therefore, the transmitting end 11 lowers the transmission request when the transmission for one time slot is completed. Next, the arbiter 165 outputs the address U2 to give the transmitting end 12 permission to transmit. Since the user information at the transmitting end 12 is 128 bits, the transmission request is lowered after occupying two time slots. Furthermore, the transmitting end 13 is then permitted to transmit. Arbiter 165 stops operating after the first frame period has elapsed. Figure 9 (C),
(dl, (e) and (f) control lines 115, 125
, 135 and the control signal to the multiplexing circuit 14. The control memo January 62 is in a writing state during the period, and at the end of the first frame period, the data shown in FIG. 4 is stored. From the next frame,
The control memory 162 enters the read state and performs exactly the same operation as in the first embodiment.

As described above, according to this embodiment, multiple line allocation can be processed in real time in response to transmission requests from each transmitting end.

A third embodiment of the present invention will be described. In this example,
Immediate communication and standby communication are integrated by priority control, and FIG. 10 shows a transmitting device used in this embodiment. The transmitting device shown in FIG. 10 is the transmitting device shown in FIG. 8 with a priority control circuit 17 added, and the configuration of the priority control circuit 17 is shown in FIG. In the priority control circuit 17, the counter 172 receives the control signal 15 at the same time as the start of the multi-frame.
3 Initialized from this, the highest priority level is the priority signal 17
It is output as 1 to all transmitting ends. Each transmitting end compares this priority signal 171 with the priority of its own user information to be transmitted, and if the level indicated by the priority signal 171 is lower, it issues a transmission request.

Therefore, initially only the transmitting end having the highest priority user information is allowed to transmit. When all such priority communications are completed, there are no transmission requests, and specifically, the control lines 115,
125 and 135 are all 0, and the output of the NOR gate 173 is 1. As a result, the counter 172 becomes ready for counting and lowers the level indicated by the priority signal 171 by one. At this time, if there is a transmission request with such priority, NO
R gate 173 does not advance the count any further. When all communications at this priority level are completed, the output of the NOR gate 173 becomes 1 again, and the counter 172 advances the count by one more and lowers the priority.

The above priority control is performed in the first frame of the multiframe. Since the line allocation for this frame is held in the control memory 162 in the multiplex control circuit 16, there is no need to perform priority control for the remaining frames.

According to this priority control, low priority communication becomes possible immediately after high priority communication ends. Therefore, by assigning high priority to real-time communication such as voice communication and assigning low priority to waiting-type communication such as data communication, both communications can be efficiently integrated.

FIG. 12 shows another example of the receiving device used in the present invention.
An example is shown below. The receiving end 21 includes an address circuit 211 .
Receive buffer 212. Gate 213. It is composed of a control section 214. The receiving ends 22 and 23 also have the same configuration.

The synchronization circuit 25 supplies a control signal 251 giving a period NIT to all receiving ends. At the receiving end 21, the control unit 214 specifies the time position of the time slot to be received based on the signal received during the period NIT, that is, all the address information, and also sends the address information to be received to the address circuit 211. supply to. The control unit 214 makes the gate 213 conductive only in the time slot specified in the period NIT. Therefore, only the user information addressed to the user is received by the reception buffer 212. According to this embodiment, address information can also be held at the receiving end.

In the above embodiment, the frame synchronization signal F is inserted every cycle T, but such a synchronization signal is not necessarily necessary (as shown in Figure 313, only the multiframe synchronization signal MF is used as a signal for synchronization). It is also possible to give a first period N=T and a second period NET based on this.

FIG. 14 shows a fifth embodiment of the present invention. In this embodiment, the present invention is applied to an exchange system. In this embodiment, the terminal interface circuit 31.3233 control circuit 31
6. It is composed of a timing circuit 315 and a bus 30. Control circuit 316 has the same configuration as multiplex control circuit 16 in FIG. The terminal interface circuit 31 consists of a transmitting end 11 having the same configuration as the transmitting end shown in FIG. 8, a receiving end 21 having the same configuration as the receiving end shown in FIG. 12, and a decoder 11. The terminal interface circuits 32 and 33 also have the same configuration.

The timing circuit 315 operates in a multi-frame period, with a first period for sending address information to the terminal interface circuits 31, 32, and 33, and a second period for sending user information.
This gives a period of Furthermore, the timing circuit 31
5 is a control circuit 3 that performs the same timing control as the synchronization circuit 15 in FIG.
This is done for 16 people. A decoder provided in each terminal interface circuit, for example, the decoder 311 of the terminal interface circuit 31, inputs the address of the terminal interface circuit that is permitted to transmit and is output from the control circuit 316, and compares it with its own address. If they match, the transmitting end 11 is activated. That is, in the embodiment of FIG.
In contrast to i, in which signals were sent to the transmission path 3 via the multiplexing circuit 14, in this embodiment multiplexing control on the bus 30 is performed by decoders arranged in a distributed manner.

Therefore, communication is carried out between each transmitting end and receiving end in the same manner as in a multiplex transmission system.

(Effects of the Invention) (1) Since communication channels can be set for each multi-frame period, communications with short hold times can be efficiently accommodated.

(2) Since multiple time slots can be occupied depending on the band, multiple communication can be easily provided.

(3) Immediate communication and standby communication can be integrated by priority control.

(4) For real-time communication, the delay time within the communication network can be made shorter than the multi-frame period.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a first embodiment of the present invention.
Figure 3 shows the configuration of the multiplexing control circuit used in the embodiment.
4 is a diagram showing a multiplex transmission frame in the fourth embodiment, FIG. 4 is a diagram showing an example of data stored in the control memory in the multiplex control circuit used in the first embodiment, and FIG. 6 is a diagram showing an example of data stored in the control memory in the expansion control circuit used in the first embodiment. FIG. 7 is a diagram showing the configuration of the expansion control circuit used in the first embodiment. FIG. 8 is a diagram showing the configuration of a transmitting device used in the second embodiment of the present invention; FIG. 9 is a diagram showing the operation timing of the second embodiment; FIG. 10 is a diagram showing the transmission delay in the embodiment. 11 is a diagram showing the configuration of a priority control circuit in the transmitting device of the third embodiment, and FIG. 12 is a diagram showing the configuration of the transmitting device used in the third embodiment of the present invention. FIG. 13 is a diagram showing another configuration example of a multiplex transmission frame according to the present invention, and FIG. 14 is a diagram showing a fifth embodiment of the present invention. be. In the figure, 1 is a transmitting device, 2 is a receiving device, 3 is a transmission path, 11, 12.13 are transmitting ends, 21, 22.23 are receiving ends, 15.25 is a synchronization circuit, and 16, 26, 316. 114.214 is a control circuit, 14 is a multiplexing circuit, 24 is an expansion circuit, 27 is a separation circuit, 111 and 211 are address circuits, 112 and 212 are buffers, 113 is a selection circuit,
164, 264, 172 are counters, 162°262 is a memory, 163 is a processor, 165 is an arbiter, 17
is a priority control circuit, 173, 213 are gates, 31, 32
．． Reference numeral 33 indicates a terminal interface circuit 315, a timing circuit, and 311 (decoder). Figure 7 %W Figure // Figure 1? Figure 75 Figure lφ Figure

Claims (1)

[Claims] In a time division communication system consisting of one or more transmitting ends and receiving ends, and a time division communication network that provides a communication path between the transmitting ends and the receiving ends, N ( Communication control is performed using a third period consisting of a first period for communicating address information (N≧2) and a second period for communicating N pieces of user information corresponding to the address information. In the first period, N communication channels are set in the time-division communication network, and in the second period, the N user information is transmitted using the set N communication channels. A time division communication system characterized by communication. 2. The time division communication system according to claim 1, characterized in that the communication control is multiplex transmission control.