JPS61274339A - Gate array with RAM - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A gate array equipped with Rm, in which the SiW part is divided into several parts, a channel region is provided at the boundary thereof, and the length of the channel wiring is shortened.

[Industrial application field]

The present invention relates to gate arrays equipped with RAM, and in particular to RAM-equipped gate arrays.
M section (hereinafter referred to as cell, sense amplifier, write amplifier,
This invention relates to improvements in channel wiring in a configuration in which a RAM area (including drivers, decoders, etc.) is provided around the chip 10 and a gate array is provided in the center.

! FIG. 5 shows an example of the layout of the RAM and gate array. Four 81M sections 3 are arranged around the chip, and a gate array section 2 is arranged in the center. 4 represents a pad. By arranging the gates in one place and ensuring that they are not disconnected in the RAM section, there is an advantage that the degree of freedom in interconnection of the gate array can be ensured.

[Conventional technology]

In recent years, RAM sections have been increasing in size, and the area occupied by the RAM sections has become large. In particular, in the arrangement shown in FIG. 3, it is often necessary to wire to the internal gate 5 on the gate array side in the center of the chip. Therefore, a situation occurs in which the length of the channel wiring becomes long.

[Problem that the invention seeks to solve]

As the channel wiring becomes longer, stray capacitance and wiring resistance increase, which impedes speed-up of operation and causes fluctuations in input/output voltage levels.

[Means for solving problems]

In the present invention, as conceptually shown in FIG.
) is divided into several parts (in this case 2) in terms of layout, the channel region 7 is provided at the boundary between the parts, and the length of the channel wiring 6 is shortened, thereby solving the above problem.

As for how to divide the RAM section, even though the circuit itself is the same as the conventional chip W section, channels can be secured by dividing it into a memory cell area, a decoder area, a driver area, an amplifier area, etc. in terms of layout. is easy.

[For production]

As mentioned above, by dividing the RAJt section and providing a channel region at the boundary, the channel wiring can be shortened, its stray capacitance and wiring resistance reduced, speeding up the circuit, and increasing the input power. It becomes possible to reduce fluctuations in output level.

〔Example〕

R from the pad 4 around the chip 1 shown in FIG. 2 (2)
An embodiment in which the wire A) is wired beyond the portion 3 to the gate array portion 2 side is shown in FIG. 2 ω.

In FIG. 2), 91.9B is an EAH cell area, in which an X (column) decoder area 15 and an X driver area 16 are arranged in the center, and a Y decoder area 17 is also arranged. Hold circuits 10A and 1 ([? are arranged on the left and right sides of the RAM cell parts 9A and 9B,
On the row side of A and 9B, there are Y driver regions 12A and 12B connected to the bit line and a sense/write amplifier region 11A.
, 11B are arranged. 4A is an input pad for RA)vf, 5 is an internal gate (configured in gate array part 2), and 13 is an input port for RAM.

4B is the pad for the output of RA)t, 8 is the output pad.
), 14 is an output port of the RAM.

These arrangements and configurations themselves are common and will not be particularly explained.

In an embodiment of the invention, a centrally located X-decoder 15. X driver 16 and Y decoder 17 and their left,
Right Rm cell area 9A, 9BSY driver 12A, 1
2B and sense/write amplifiers 11A and 11B, forming channel regions 7A and 7E (hatched portions).

Cell regions 9A, 9 across channel regions 7A, 7B
The wiring connecting B and the
The wiring connecting the decoder 17 and the Y drivers 12A and 12B can also be combined into one layer of wiring.

Since there is no other wiring that needs to cross the channel region 71.7E, the wiring that crosses the channel region described above is combined into the first layer wiring, and the second layer wiring is connected to the channel region 7A,
Can be reserved for 7B.

As a result, as shown in FIG. 2@), it becomes possible to pass the wiring 6A from the input pad 4A to the internal gate 5 via the channel region 7A without bypassing the RAM section.

On the other hand, the pad 4B on the output side of the RAM is connected to the output gate 8, and the output is passed through the channel region 7B to the RA).
It can be connected to the output port 14 of t with a wiring 6B.

FIG. 3 shows another embodiment of the invention. This is an embodiment in which wiring is made from the pad 4 on the chip 1 shown in FIG. 2 to the gate array part 2 across the RAM section 3.

In ) of Fig. 3, the same parts as in ) of Fig. 2 are indicated by the same numbers. In this case, as is clear from the figure, the cell portions 9A, 9B and the X decoder region 15.
The arrangement of the X driver area 16 is the same as in the conventional case, while the cell areas 9A, 9B and the Y driver area 1
2A, 12B, and between the X driver 16 and the Y decoder 17 (: spaces are provided to ensure a channel region 7C.

Y driver regions 12A, 12E, sense-write amplifier regions 11A, 11B shown above, and RAM cell region 9A.

9B is just connected by 19A and 19B, so this only requires one layer of wiring. Therefore, for example, the connected bit lines 19A and 19BV are combined into only the second wiring layer, and the first wiring layer I:f layer region 7
C can be secured, and the wiring length can be shortened by passing the signal line through the region 7CI.

Although the embodiments have been illustrated and described above, various modifications can be made to the present invention. For example, it is possible to use the channel regions 7A, 7B, and 7C in FIG. 2(b) and FIG. 50 together.

For example, it is sufficient to secure 7A, 7B-Jk 2nd wiring layer, and 7(t-1st wiring layer &: ensure T) that intersects with this.

However, care must be taken to avoid crossing power lines.

In addition to the above example, C: may also be considered for the division of the RAM section,
For example, a channel region can be secured by providing a gap between the hold circuit regions 10A and 10B that are connected to the cell regions 9A and 9E only by word lines.

In the present invention, the width of the above-mentioned channel region secured across the RAM section is formed as narrow as necessary,
To suppress an increase in the length of word lines and bit lines due to division of a RAM section, and to prevent a decrease in operating speed of the RAM.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, RA
In the gate array equipped with M, channel wiring is connected to RAM.
Since the channel wiring can be formed without bypassing the circuit, it is possible to shorten the channel wiring, speed up the circuit, and reduce fluctuations in input/output voltage levels.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of the present invention, Fig. 2 (A) and (!?) are respectively a plan view and a layout diagram of main parts for explaining the embodiment, and Fig. 3 cAJ, @) is another embodiment. Fig. 4 is a schematic diagram of a conventional example, and Fig. 5 is a plan view showing an example of the arrangement of a conventional gate array equipped with an RA. . (Main symbols) 1...Chip 2...Gate array 3...RAM section 4...Pad 5...Internal gate

Claims (1)

[Claims] A gap is provided between a memory cell area of a RAM and an attached circuit area such as a decoder area, a driver area, a sense or write amplifier area, or a hold circuit area, and a signal line wiring area is provided in the gap. A gate array equipped with RAM that is characterized by being secured.