JPS61273012A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To prevent the oscillation when input terminal R,S both change from '1' to '0' by providing the 1st -7th transistors (TR), the 1st -3rd constant current sources and the 1st and 2nd constant voltage sources. CONSTITUTION:In inputting '1' of an input inhibition signal to both input termi nal R,S, both TRs Q13 are turned on and TRs Q9, Q10, Q11, Q12 are turned off, then the level of output terminals Q, -Q go respectively to '0', '1', the reset state, that is, application of '1' to the input R and '0' to the input S, is attained. From the state above, in giving '0' to both the input terminals R, S at the same time, the tRs Q9, Q11, Q13 are turned off and the TRs Q10, Q12 are turned on, then the output terminal Q goes to '0' and the output terminal -Q goes to '1'. Thus, no oscillation is caused when the inputs R, S are changed both from '1' to '0'.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention's logic circuit, %KECL type R-87 lip-flop circuit. [Prior Art] Conventionally, this type of 0R-87 lip-flop circuit is shown in FIG. As shown in the figure, use two 12-power NOR gates 1.2 and connect the output of each to one of the inputs of the other 0NOR gate, one of the remaining inputs is the R input, or reset input, and the other is the 8 input, or set input. It was structured as follows.

Both R and 8 input terminals are changed from a high level voltage (hereinafter abbreviated as w1t) in an inhibited state to a low level voltage (hereinafter abbreviated as I) in a maintained state.
(abbreviated as QI) Q when K signal is added.

The output of the Q output terminal changes from IQI to '1' IC, and N
Each input of the OR gate is input, and as a result, the outputs of the Q and Q output terminals become "O" again, and oscillation occurs in which IQI and Ill return to "O".

FIG. 3 shows a more detailed circuit diagram of an ECL type 7 lip-flop than the R-87 lip-flop circuit shown in FIG.
OR gate 1 is composed of transistors Q41Qs=Qs, Qs, etc., and NOR gate 2 is composed of transistors Qt-Q.
x eQs, Q7, etc.

[Problem that the invention seeks to solve]

The conventional 0R-8 flip-flop circuit described above has the drawback that oscillation occurs when the R and S inputs are set to 11'' and the inner inputs are simultaneously changed by K'0''K.

An object of the present invention is to provide a flip-flop circuit that prevents this oscillation.

[Means for solving problems]

The 0R-8 flip-flop circuit of the present invention gives priority to %R (large input or 8 input) when R and 8 inputs are set to @11, and outputs a positive output to 101 (or negative output "0").
A first transistor having a base connected to a set input terminal and a collector connected to a power supply terminal via a first resistor; a first transistor having a base connected to a first reference power supply and a collector connected to a second resistor; a second transistor whose base is connected to the power supply terminal via the positive output terminal K;

a third transistor whose collector is commonly connected to the collector of the first transistor and whose emitter is commonly connected to the emitters of the first and second transistors, whose base is connected to the second reference power supply and whose collector is connected to the first transistor; ．． Second. a fourth transistor connected to the third transistor emitter; a base connected to a reset terminal; a collector connected to the collector of the second transistor; and an emitter connected to the first constant current source together with the fourth transistor. a sixth transistor having a base connected to the collector of the second transistor, a collector connected to the power supply terminal, and one emitter connected to the positive output terminal and the second constant current source; has a collector of the first transistor, a seventh transistor whose collector is connected to a power supply terminal, and whose emitter is connected to a third constant current source and a negative output terminal.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

Figure 1 shows an R-
It is an 8 flip-flop circuit. Now S input terminal K” 1
', When a signal of 101 is applied to the R input terminal, the transistor Qss Qlt 5Qsx becomes conductive (hereinafter referred to as "O
(abbreviated as “N”) and transistor Qz.

Since Qss is in a cutoff state (hereinafter abbreviated as "OFF"),
Expanded to output terminal Q @ 1-9 10 expanded ports are output to output terminal Q. In this state), when the signal at the 8 input terminal changes from 111 to 101, transistor Q9 is 'OFF'
However, the base of the transistor Qll is one of the output terminals Q.
Since it is connected to 11, it remains ON. For that reason 1
Output terminals Q and Q are “1”*”O”of-*! ! 78
The state of human power "1" and R input 101 is maintained.

Also, when a signal of "1" is applied to the R input terminal and a signal of 101 is applied to the 8 input terminal, the transistor Ql is turned on, and the transistors Q1, Qll, and Qs+a are turned off), and the output terminal Q is 101. fil is output to the output terminal Q. In this state, the signal at the B input terminal is changed from "1-" to "0".
When changed to , the transistor Qts turns "OFF",
Transistor Qtt turns “ON”, but transistor Q
, and Qll are also "OFF", so the transistor Q1° is turned ON. Therefore, output Q and Q have 8 inputs.
The O' and R inputs maintain the state of 111.

Therefore, this circuit performs the operation of a normal R-8 flip-flop.

Next, when input prohibition signal wlm is input to both KR and 8 input terminals, transistor Qss is turned on and transistor Q and Q1゜5QtteQt* are turned off, so output terminals Q and Q are w□w and *1w, respectively. In other words, in the reset state, K is the same as when a signal of -01 is added to 1118 human power to the R input. From this state, if both R and 8 input terminals are set to '01' at the same time, transistor Q5QttsQ
ts is 0FFL, transistor Q1e s Qtx is "
In order to turn on', the output terminal Q becomes 0'' and the output terminal Q becomes 111.

Therefore, the phenomenon of oscillation when the R18 input is simultaneously changed from K@11 to 101, which has been a problem in the conventional n-87 lip-flop circuit, does not occur. Also R
When the input is changed to 8 input, the 8 input is changed to the R input, and each output of output terminals Q and Q is changed in the same way, and the signal 111, which prohibits human input, is applied to the 8 input terminal, the output is set, In other words, it goes without saying that the same function can be obtained even if the same state as when the 1" and R input ic I o I signals are added to the 8 inputs.

〔Effect of the invention〕

As explained above, according to the circuit of the present invention, even if the R1S input terminal changes from K"l" to 101, there is no oscillation.
7-lip 70 with fewer conventional circuit elements
A tube circuit is obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional 0R-87 lip-flop, and FIG. 3 is a circuit diagram thereof. R1, R,...Resistance, Q4~Qtm...
...Transistor, 11-I4... Constant current source, VBFI, VBrz-... Constant voltage source, R.
...Reset input terminal, S...Set input terminal, Q...Positive output terminal, Q...
Negative output terminal, Vcc...Power supply terminal, GND
・・・・・・Ground terminal. \, -1″・

Claims (1)

[Claims] a first transistor whose base is connected to a set input terminal and whose collector is connected to a power supply terminal via a first resistor;
a second transistor having a base connected to the first reference power supply and a collector connected to the power supply terminal via a second resistor;
a third transistor whose emitter is commonly connected to the emitters of the first and second transistors;
a fourth transistor having a base connected to a second reference power supply, a collector connected to the emitters of the first, second and third transistors; a fourth transistor having a base connected to the reset terminal and a collector connected to the second reference power source; a fifth transistor whose emitter is connected to the collector of the transistor and the emitter of the fourth transistor to the first constant current source, and whose base is connected to the collector of the second transistor;
a sixth transistor having a collector connected to a power supply terminal, an emitter connected to the positive output terminal and a second constant current source, and a base connected to the collector of the first transistor;
A flip-flop circuit comprising a seventh transistor having a collector connected to a power supply terminal and an emitter connected to a third constant current source and a negative output terminal.