JPS6126957A - Control signal detecting circuit - Google Patents

Abstract

PURPOSE:To detect surely a control signal by comparing the output of a waveform equalizing means to which both information and control signals are supplied with the reference value and sampling the comparison output to subject it to majority decision processing. CONSTITUTION:The pilot signal reproduced out of a magnetic tape 2 is supplied to a BPF20 and an equalizer 60 via a switch circuit 19 respectively. The waveform equalized output of the equalizer 60 is compared with the reference value by a zero-cross comparator 61. This compared output is sampled by a majority decision circuit 62 and undergoes the majority decision processing. This majority processed output is extracted through the BPF29 as an erasion signal SE. The signal SE is supplied to gate circuits 331-336 via a waveform shaping circuit 30 and a rise detecting circuit 31 respectively. Thus a pulse generating circuit 43 and a sampling pulse generating circuit 44 are controlled. Thus a control signal can be detected surely and a tracking control signal is outputted to a terminal 26.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention converts, for example, a video signal or an audio signal into a PCM signal, and records this as one diagonal track on a recording medium by a rotating head in units of time. The present invention relates to a control signal detection circuit suitable for use in a signal transmission system such as a recording/reproducing device for digital signals that reproduces a digital signal.

BACKGROUND TECHNOLOGY AND PROBLEMS A helical scan type rotary head device records video and audio signals on a magnetic tape once per unit time.
When recording by forming diagonal tracks one by one and reproducing them, it has been considered to record and reproduce video signals and audio signals by converting them into PCM. This is because PCM allows high-quality recording and reproduction.

In this case, tracking control to ensure that the rotating head correctly scans the recording trunk during playback is conventionally performed by sending a control signal recorded at one end of the tape widthwise by a fixed magnetic head to the fixed head. Normally, this is done by reproducing the signal and making sure that the reproduction control signal and the rotational phase of the rotary head have a constant phase relationship.

However, this method requires a fixed magnetic head specifically for tracking control.

Providing such a fixed magnetic head is inconvenient when it is desired to downsize the recording/reproducing apparatus due to the mounting location and the like.

Therefore, the present applicant previously proposed a method of controlling the tracking of a rotary head for reproduction by using only the reproduction output of the rotary head for reproduction without using this fixed head.

In this method, PCM signals can easily be compressed and expanded on the time axis, so unlike analog signals, it is not necessary to record and reproduce the signals continuously in time.
This method was developed by focusing on the fact that it is possible to easily record this PCM signal and a separate signal by dividing the areas into the tracks of a book.

That is, when compressing the time axis of a PCM signal and forming and recording diagonal tracks on a recording medium using a plurality of rotary heads to form a guard band, the PCM signal is compressed in the longitudinal direction of each trunk. records multiple tracking pilot signals independently as a recording area, and when playing back,
A recording track is scanned by a rotary head whose scanning width is wider than the width of the track, and the tracking of the rotary head is controlled by the reproduced output of pilot signals from tracks on both sides of the track being scanned by the rotary head.

The reference signal for recording and reproducing this pilot signal for dragging is a 30Hz pulse signal (PG ) is used.

However, when the PC signal is used as the detection position reference when reproducing the tracking pilot signal, the PG double signal reference position may shift due to mechanical changes in the device over time, temperature changes, etc. It appears as a kind of steady amount (offset) of tracking error.

For this reason, it becomes difficult to reproduce the tracking pilot signal at the same timing as during reproduction and recording, and to control the rotary head, and there is a problem in particular that compatibility between devices becomes incompatible.

In addition, since the sampling pulse for obtaining the reproduced output of the tracking pilot signal is formed over one rotation period of the head using the PG multiplied signal as a reference, the error increases in an integrated form, resulting in the effect of so-called jitter. As a result, the position of the sampling pulse may shift.

In addition, when considering tracking control in a rotary head type recording/playback device, consider not only normal playback but also variable speed playback where the tape speed is different from that during spring recording.
must be considered.

Therefore, during normal playback as well as variable speed playback, the tracking biloft signal is reliably reproduced and the rotating head is controlled correctly without being affected by mechanical aging, temperature changes, or jitter of the device, and the rotation head is controlled correctly. The present applicant has further proposed a digital signal recording and reproducing device that can achieve compatibility and simplify the circuit configuration when performing reproduction by switching between a plurality of reproduction speeds.

First, the apparatus will be explained in detail based on FIGS. 1 to 8.

Figure 1 shows the circuit configuration. For convenience, only the circuit configuration for recording the tracking pilot signal and the erasing signal and reproducing them by switching between normal playback and variable speed playback, for example, double speed and triple speed, is shown here. The circuit configuration for recording and reproducing recorded information such as a PCM signal is omitted.

In the figure, (IA) and (IB) are rotary heads, and (2) is a magnetic tape as a recording medium. As shown in Figure 2, the rotating heads (IA) and IB) rotate the drums (3
) is placed around the area. , on the other hand, the magnetic tape (2) is wound around the tape guide drum (3) over an angular range smaller than its 180° angular range, for example 90°. Then, the rotating heads (1^) and (IB) are rotated at a rate of 300 revolutions per second in the direction of arrow (4H), and the tape (2) is run at a predetermined speed in the direction of arrow (4T). Then, rotate the throat (IA) and (IB)
As a result, one diagonal magnetic track (5A) (5B) as shown in FIG. 3 is formed on the magnetic tape (2), for example, in a so-called overwritten state. That is, the head gap width (scanning width) W is made larger than the track width. In this case, the width directions of the gaps of the heads (IA) and (IB) are set in different directions with respect to the direction orthogonal to the scanning direction. In other words, the so-called azimuth angles are made different.

Then, a period occurs (this is the period of the 90 degree angular range bone in this example) during which the two rotating heads (IA) (IB) do not abut against the tape (2) together, and this period is utilized. The apparatus can be simplified by adding redundant data during recording and performing correction processing during reproduction.

(6) is an oscillator that generates a tracking pilot signal P, and the pilot signal P has a frequency fo that is relatively large in azimuth loss, that is, a frequency at which azimuth loss is effective, for example, about 200 kHz, and
recorded at relatively high levels.

Note that the frequency of this pilot signal P is preferably a frequency with relatively little azimuth loss, as long as the linearity of the tracking phase shift versus the pilot reproduction output can be guaranteed. Further, (6A) is an oscillator that generates a signal E for erasing the pilot signal, and the erasing signal E is later superimposed on the previously recorded tape while erasing the previously recorded information. This is used because when making a new record, the recorded trunk does not always match the previous recorded trunk, so it is necessary to erase the previously recorded pilot signal, and the frequency f1 is the same as the pilot signal. For example, the frequency fo is practically far away from the frequency fo.
The frequency is around kHz and has relatively large azimuth loss. Further, the recording level is also set at a level that can practically erase the pilot signal P. and,
This erasing signal E is used here as a positioning signal as a control signal for detecting the position of the pilot signal.

Further, (6B) is an oscillator that generates an erasing signal Eo different from the above-mentioned erasing signal E, and this erasing signal Eo
When the pilot signal P and the erasing signal E are overwritten, it is preferable that the erasing rate of these signals P and E is high, and the frequency f2 is, for example, 2 MHz.
A certain degree is used.

(7), (7A) and (7B) are recording waveform generation circuits, and an edge detection circuit (8A) detects an edge, for example, a falling edge, of a delay signal related to pulse PG, which will be described later.
, (8B), the generating circuit (
7) and (7A) are based on the biloft signals from the oscillators (6) and (6B), and the predetermined time is determined depending on how many biloft signals P and erasing signals Eo are inserted per track and in what arrangement. tp (tp is the recording time of each pilot signal and erasure signal Eo, however, erasure signal Eo
One hour of recording per recording area is a track (
The generator circuit (7B) continuously generates the pilot signal P and the erasure signal Eo having the time tp+ (the time tp is the sum of the two separate times in the trunk (5B)), and the generation circuit (7B) generates the oscillator (6A ), the erasing signal E having a predetermined time -tp is inserted at a predetermined interval T1 depending on how many erasing signals E are inserted per track and in what arrangement. Occur. (8F) is an OR circuit that logically processes the outputs of the generating circuits (7), .<7A) and (7B). (9) is a switch circuit for switching the rotary heads (IA) and (IB), and is switched by a switching signal S1 (FIG. 4A) from a timing signal generating circuit α0). This timing signal generation circuit αO) includes a rotary head (IA) obtained from a pulse generator (11) in synchronization with the rotation of a rotary drive motor (12) for the rotary head (IA) (IB).
)(IB) A 30 Hz pulse PC is supplied which indicates the rotational phase of (IB). In addition, a 30Hz pulse from the timing signal generation circuit Oω is supplied to the pulse PG to the phase servo circuit (13), and the servo output drives the motor (12).
) is controlled.

The pilot signal from the switch circuit (9) switched by the switching signal s1 from the timing signal generation circuit αΦ is amplified by the amplifier (14A) or (14B) and then sent to the contact point of the switch circuit (15A) or (15B), respectively. is supplied to the rotating head (IA) or (IB) via the R side,
Recorded on magnetic tape (2). Switch circuit (15
^) and (15B) are connected to the R side during recording, and are switched to the P side during playback.

Also, the output signal S2 from the timing signal generation circuit α
(Fig. 4C) is supplied to the delay circuit (16), and this
Rotating head (1^) (IB) and pulse generator (1)
After a delay corresponding to the distance between the mounting positions in 1),
The signal is supplied to the input side of an edge detection circuit (8A), and an edge, for example, a falling edge, is detected as a recording reference of a pilot signal. Note that the signal S3 delayed by the delay circuit (16)
The falling edge of the line (FIG. 4D) is made to coincide with the time at which the first head contacts the tape during one rotation period.

Also, (17A), (-17B), (17
C) , (170) and (17E) are each delay time T1 (1) Pilot signal P recorded on the rack,
time corresponding to the respective intervals of the erasing signals E and Eo),
T2 (2T1)T (time corresponding to half rotation period of the head), signal S3 from tp(,16) (Fig. 4D
) are supplied to delay circuits (17^) to (17C), respectively. Signal S4 from delay circuit (17^) (Fig. 4E)
is supplied to the edge detection circuit (8A), and the delay circuit (17
The signal Ss from B) (FIG. 4F) is supplied to the edge detection circuit (8B), and the signal Ss from the delay circuit (17C) is supplied to the edge detection circuit (8B).
6 (FIG. 4G) is directly supplied to the edge detection circuit (8B) and delayed by times T1 and T2 in delay circuits (17A) and (17B), respectively, to form the signal S? (FIG. 4H) and signal Ss (FIG. 4I) to edge detection circuits (8B) and (8A).

Signal S9( from edge detection circuits (8A) and (8B)
4J) and signal 5zo (FIG. 4K) are delayed by time tp and -tp in the delay circuits (170) and (17B), respectively, to produce signal 511 (FIG. 4L) and signal 512 (FIG. 4M).
). The signal S11 is supplied to the negative input terminal of the OR circuit (8C), and is delayed by a time -tp in the delay circuit (17B) to become a signal 513 (N in FIG. 4). This signal 313
is supplied to the - input terminal of the OR circuit (8D) and is delayed by 2 tp in the delay circuit (17B) to produce the signal 514 (
0) in Fig. 4, and this signal 314 is an OR circuit (8E).
The signal is supplied to the - input terminal of , and is delayed by time -tp in the delay circuit (17B) to become a signal 515 (FIG. 4P), which is supplied to the other input terminal of the OR circuit (8D).

Further, the signal 312 is supplied to the other input terminal of the OR circuit (8E) and is delayed by a time tp in the delay circuit (170) to become a signal 816 (Q in FIG. 4), and this signal 31G is supplied to the OR circuit (8D). The signal is supplied to another input terminal and is further delayed by a time tp in a delay circuit (170) to become a signal 517 (R in FIG. 4), which is supplied to the other input terminal of an OR circuit (8C).

Signals 818 (S in Fig. 4), signals 519 (T in Fig. 4) and signals 520 (U in Fig. 4) from the OR circuits (8C), (8D) and (8E) are respectively connected to the recording waveform generation circuit (7).
.

(7A) and (7B) as gate signals, and the pyroft signal P and erase signals Eo and E from the generators +6), (6B) and (6A), respectively, are supplied to the recording waveform generation circuits (71, ( 7A) and (7B) to the output side of the OR circuit (8F) as a composite signal 521 (FIG. 4M).

(18A) (18B) is a switch circuit (1) during playback.
These amplifiers (18A) are supplied with playback output from the corresponding rotary heads (IA) (IB) when 5A) (15B) is switched to the contact P side.
Each output of (18B) is supplied to a switch circuit (19). The switch circuit (19) receives the switching signal 81' of 30 & from the timing signal generating circuit QQI (Fig. 5A, 6
FMA and Fig. 7A), the head (I
The half-rotation period including the tape contact period of A) and the head (I
B) The half-rotation period including the tape contact period is alternately switched.

(20) is the passing center frequency f for extracting only the pilot signal P from the reproduction output from the switch circuit (19).
(21) is a peak hold circuit for holding the peak value of the output of the filter (20) in order to improve response characteristics; (22) is a peak hold circuit for holding the peak value of the output of the filter (20) in order to improve response characteristics; A sampling-and-hold circuit for sampling and holding, (23) a comparison circuit for comparing the outputs of the peak-hold circuit (21) and the sampling-and-hold circuit (22), such as a differential amplifier, and (24) a differential amplifier (23). ) is a sampling and holding circuit for sampling and holding the comparison error signal from these sampling and holding circuits (2
2) As will be described later, (24) essentially applies to both end portions of the trunks on both sides adjacent to the track currently being scanned during normal playback, and the central portion of the track currently being scanned during double speed playback. It works to sample and hold the crosstalk of each pilot signal recorded in the center or at the ends, or in the center or at both ends of the tracks on both sides adjacent to the track being scanned during triple-speed playback. And the sampling hold circuit (
24) is taken out as a tracking control signal to an output terminal (26) via a switch circuit (25).

Also, sampling hold circuit (22) (24)
In order to form sampling pulses, etc. for use, a narrow band pass filter (29) with a passing center frequency f is provided on the output side of the switch circuit (19) to extract only the erasing output E from the reproduced output. ,′ its output s, +
(FIG. 5, FIG. 6 1, FIG. 7 M) is waveform-shaped by the waveform shaping circuit (30), and the signal 522 (FIG. 5, FIG. 6
Figure J, Figure 7 L).

(31) is a rising edge detection circuit for detecting the rising edge of the signal from the waveform shaping circuit (30), and as will be described later, the rising edge of the erasing signal is detected every half rotation period of the head. The output of the detection circuit (31) is sent to a plurality of gate circuits (331) and (332).

(333), (a3=), (335) and (336), and their gate signals include, for example, window signals S, Wx to 5w5 from a window signal generation circuit (34) using a counter (Fig. 5). C-H) is used. The window signal generation circuit (34) counts the clocks from the clock terminal (42) in response to the output signal S2 from the timing signal generation circuit α, and generates a predetermined width that can cover at least both ends of the signal S22. Wind signals are generated according to a plurality of playback modes.

That is, when the window signal generation circuit (34) receives a command signal for setting the normal playback mode from the mode setting circuit (32), it sequentially generates the window signals Sw1 to SWS, and also generates a command signal for setting the double speed playback mode. When you receive it,
Wind signal sw2. sws or 3w3. When only Sv< is generated and a command signal for setting the triple speed playback mode is received, the wind signal SW2 +SW5 or SWl,3 is generated.
w3 and S w+ r S ws ).

Therefore, only the edges of the signal 322 that have entered within the period of these window signals SW1 to Sws are derived to each output side of the gate circuits (331) to (33s), and the OR circuit (the output side of the Output signal 523 (M in Fig. 5, M in Fig. 6)
, FIG. 7M), and is supplied to one input side of a delay circuit (36) using a counter, for example, as approximately 6 start pulses.

Also, a plurality of delay time setting circuits (38) and (39)
is provided, and the setting circuit (38) sets a delay time ta from the time of generation of the signal 323 during double speed and triple speed playback until the actual sampling of the pilot signal starts;
The setting circuit (39) sets a delay time tb from the time of generation of the signal 323 to the actual sampling time of the biloft signal during double speed reproduction.

In this way, each delay time set by the setting circuits (38 and (39)) is selected by the window signals Sν1 to Swε from the window signal ordering circuit (34) in the delay time setting selector (37). The signal is supplied to the other input side of the delay circuit (36).Therefore, the delay circuit (36), which is a counter, uses the signal 323 as a start pulse, and uses the signal 323 as a start pulse directly if no delay is required, or to set the delay if a delay is necessary. The clock from the clock terminal (42) is counted for the time that is counted, and at the end of the count, a narrow signal 524 (FIG. 5M, FIG. 6, and FIG. 7M) is generated on the output side.

(43) is a pulse generation circuit using a counter, for example, which counts the clock from the clock terminal (42) using the signal S24 from the delay circuit (36) as a trigger pulse, and counts the clock from the clock terminal (42) during normal playback and triple speed playback ( In the first method (first method), a pair of pulses Pi (FIG. 5 0, FIG. One of Pi (6th
Figures M, P, and Figure 7 R) are generated corresponding to each pilot signal to be detected. This pulse Pi is supplied to a peak hold circuit (21) and also to a sampling pulse generation circuit (44) using, for example, a D-type flip-flop circuit.

The sampling pulse generation circuit (44) generates sampling pulses SP1 and SP2 to the sampling and hold circuits (22) and (24) in response to the pulse pt.

Further, (51) is a comparison circuit provided on the output side of the filter (29), and this comparison circuit (51) is connected to the output of the filter (21), that is, the reproduction output of the erasing signal E and the reference power source (52). ), and if the reproduced output exceeds the reference value, an output signal 525 (C in Figure 8) is generated, and the clock terminal of the D-type flip-flop circuit (53) is generated as a latch pulse. supply to. Further, a circuit (54) for detecting, for example, the falling edge of the switching signal S1' from the timing signal generation circuit a[a] is provided, and outputs the output signal 826 (eighth
E) is generated and supplied to the reset terminal R of the flip-flop circuit (53) as a reset signal. Also, the switching signal 81' is inverted by the inverter (55) and the signal 31' is inverted by the inverter (55).
'(Fig. 8F), and the flip-flop circuit (53)
is supplied to the input terminal of

Further, a circuit (56) for detecting, for example, the rising edge of the switching signal S1' is provided, and generates an output signal 52T (FIG. 8G) in synchronization with the rising edge of the switching signal 81', and outputs a D-type flip-flop as a clock signal. It is supplied to the clock terminal of the circuit (57). The output signal 8 of the flip-flop circuit (53) is connected to the input terminal of the flip-flop circuit (57).
28 (Fig. 8H) is supplied, and the flip-flop circuit (
57) output signal 529 (Fig. 8 ■) is sent to the switch circuit (
25) is used as a switching control signal. That is,
As will be described later, the switch circuit (25) receives the control signal 3
29 force (one level, for example, high level (in the old case, contact point a)
Connected to the side and outputs the tiger knocking control signal (
26) and performs normal operation, but the control signal S2
When 9 is at the other level, for example, low level (L), it is connected to the contact side, and a constant potential Vcc is taken out from the terminal (58) to the output terminal (26), and this is used as a tracking control signal for the capstan servo system. to force the scanning head into a normal tracking state.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the signal waveforms shown in FIGS. 4 to 8.

First, during recording, a pulse PG from a pulse generator (11) indicating the rotational phase of the rotary heads (IA) (IB) is generated.
In response, the timing signal generating circuit Ql generates a signal S2 as shown in FIG. A signal S3 as shown in Figure 4 is output. This signal S3 is supplied to the direct and delay circuit (17) as described above.
A), (17B) via the edge detection circuit (
8A), its edge (falling edge) is detected, and a narrow signal S9 as shown in FIG. 4J is generated on the output side in synchronization with this edge. Also, a delay circuit (17B).

Signals Ss, Ss and S from (17C) and (17A)
7 is supplied to an edge detection circuit (8B), which detects the edge (falling edge), and generates a signal S10 as shown in FIG. 4K at its output side in synchronization with this edge. Signal S9. Ssa is the delay circuit (170) and (
17E) and is delayed as described above (4th
(See Figures L-R), resulting in OR circuits (8C) to (8B)
On the output side of each, a signal 31 as shown in FIG.
s~320 are taken out and these signals S1s+S
By zs and S20, substantially the head (IA),
(IB) biloft signal P, erasure signal Eo
and recording start standards for the erasing signal E are established.

The signals Sis+ Szs and S2+) are supplied to recording waveform generation circuits (7), (7A) and (7B), respectively, and the recording waveform generation circuit (7) generates signals from the oscillator (6) in synchronization with the supplied signal Sze. The pilot signal P is passed for a predetermined time tp at predetermined intervals as shown in FIG. The erasing signal Eo from the source is passed for a substantially predetermined time tp at predetermined intervals as shown in FIG. The erasing signal E from the oscillator (68) is passed for a predetermined time -tp at predetermined intervals as shown in FIG. 4U.

The output signals from the recording waveform generation circuits (71, (7A) and (7B)) are added by an OR circuit (8F), and a signal S2t as shown in FIG. 4 (2) is taken out at its output side.

Incidentally, at this time, for example, if we consider the case where the head (IB) is recording track (5B2) in FIG.
The first, second and third pulses of signal S1e in FIG. 4S are pilot signals P A21 P A4 and P
The first of the signals Sts in FIG. 4T, corresponding to Afl,
The second and third pulses correspond to the erasing signal Eo adjacent to both sides of the erasing signal EA2°EM4 and one side of the erasing signal EA6, respectively, and also correspond to the first and third pulses of the signal S20 in FIG. 4U. The second and third pulses correspond to the erasing signals E A2 , E A4 and EM adjacent to Eo, respectively, and are signals corresponding to the arrangement of these signals, that is, EM2 . E
o, E'A2. EO and EM4. E.O.

EM4. Eo and EM8. The combined signals of EO and EM6 are taken out to the output side of the OR circuit (8F) for each group.

For example, if we consider the case where the head (IA) is recording track (5A2) in FIG.
The first, second and third pulses of signal 31B in FIG.
The pulses are generated by erasing signals E 82 and E 84 adjacent to one side of erasing signal E 84 and on both sides of erasing signal EBQ, respectively.
o, and also the first of the signal S20 in FIG.
, the second and third pulses are respectively E above.

The erasing signal EB2. adjacent to the erase signal EB2. A signal that corresponds to EO4 and PH10 and corresponds to the arrangement of these signals, that is, E
H11EO+ PH1 and EO4, Eo, PH1
The combined signals of P B81 E o +EBB and Eo are taken out to the output side of the OR circuit (8F) for each group.

On the other hand, the timing stop signal generation circuit aω generates a switching signal S1 as shown in FIG. 4A in response to the pulse PG from the pulse generator (11), and this signal S1
is synchronized with the rotation of the rotating heads (IA) (IB), and as shown in FIGS. 4A and 4B, the head (I
A) is in contact with the tape (2), and the head (IB) is in contact with the tape (2) within a half-rotation period tB during which the signal S1 is at a low level. Then, the switch circuit (9) is switched by the switching signal S1 to the state shown in the figure during the period tA, and to the state opposite to the state shown in the figure during the period tB, thereby performing head switching.

Therefore, the signal S2 obtained at the output side of the OR circuit (8F)
1, when the switch circuit (9) is in the opposite state to the state shown in the figure, the amplifier (14B) and the switch circuit (15B)
) is supplied to the head (IB) through the R side of
At the beginning, middle and end of the contact period of the head (IB) in B with the tape (2), as shown in FIG.
5B) Equidistant 11111 from the longitudinal center position! (T
Tracking signal recording areas AT provided at both longitudinal ends of one trunk (equivalent to 1 trunk)
When the switch circuit (9) is in the state shown in the diagram, signal 31
? is supplied to the head (IA) through the R side of the amplifier (14A) and the switch circuit (15A), and is supplied to the head (IA) at the beginning, middle, and end of the contact period of the head (IA) to the tape (2) within the period tA. As shown in the figure, recording areas ATi similar to those described above are provided at both ends of the track (5A) in the longitudinal direction, which are equidistant # (equivalent to To) away from the center position in the longitudinal direction of the trunk (5A). and AT2 respectively time-jp
+tp+tP and a similar recording area A provided in the center of the track (5A).
+tp.

In addition, at times other than when these biloft signals and erasing signals are recorded, the audio PCM signal of the l segment portion that should be recorded as one track (not shown) is
During the period tA, the head (1^) is connected through the amplifier (14A).
and during period tB, it is supplied to the head (IB) through the amplifier (14B), and each track (5A) is supplied to the head (IB) through the amplifier (14B).
(5B) It is recorded in recording areas AP and APR other than the above-mentioned pilot signal recording area.

Next, reproduction of the signal recorded as described above will be explained.

During this reproduction, the motor (12) is driven by the phase servo circuit (13) in the same way as during recording.

phase servo is applied.

First, during normal playback, the rotating head (IA)
The signals extracted from the tape (2) by (IB) are sent to the switch via the contact P side of the switch circuit (15A) and the amplifier (18A), and the contact P side of the switch circuit (15B) and the amplifier (18B). It is supplied to the circuit (19). This switch circuit (19) uses a 30 Hz switching signal St' as shown in FIG. , and a half-rotation period tB including the tape contact period of the head (IB). Therefore, from this switch circuit (19), intermittent PCM of l segments as shown in Figure 5 (■) is transmitted.
A signal sR is obtained, which is supplied to a reproduction processor (not shown) and demodulated into the original PCM signal, and further supplied to a decoder, where data for each block is detected using a block synchronization signal, and error correction and decoding are performed. Processing such as interleaving is performed, and the signal is converted back to an analog audio signal by a D/A converter and outputted to the output side.

Tracking control is performed as follows.

For example, if the head (IB) is to scan a range of scanning width W that includes the track (5B2) as shown by the dashed line in FIG. 3, the head (IB) will scan the trunks ( 5A2 (5^1) and scan the area AT14 as shown in Figure 3.
In this case, the pilot signal PA of the truck (5B2)
2 and the pilot signal P of the trucks on both sides (5A2)
B2 and truck (57k) pilot signal PBi
and in area AT8, track (5B2)
Pilot signal PA4 and adjacent trucks on both sides (5^2)
The pilot signal PB4 of the truck (5^1) and the pilot signal PB8 of the truck (5^1) are reproduced, and in the area AT2, the pilot signal pae of the truck (5A2) on both sides, the biloft signal peg of the trunk (5^1), and the biloft signal peg of the truck (5^1) are reproduced. 5B2) Pyro.

and regenerates the target signal PAs. At this time, the switch circuit (1
The playback output of the head (IB) from 9) is supplied to a narrow band pass filter (2o) with a passing center ff wave number fO, and as shown in Fig. 5J, only the pilot signal is outputted as the output SF. This is taken out and supplied to the peak hold circuit (21).

The output of the switch circuit (19) is also supplied to the SRd' bandpass filter (29), where the fifth
Erasing signals S&- as shown in FIG. K are taken out. This signal is supplied to the waveform shaping circuit (30) and the 51st! I
The signal 322 as shown in L is then supplied to a rising edge detection circuit (31), where its rising edge is detected and supplied to gate circuits (331) to (33s).

Further, the window signal generation circuit (34) outputs a signal S as shown in FIG. 5B from the timing signal generation circuit Ql.
2, window signals SWt to SW as shown in FIG.
(33s) as a gate signal, therefore, the output side of these gate circuits has a window signal SW1.
~ Only the signals that entered during each period of SWS are substantially taken out, and as a result, the output side of the OR circuit (35) on the output side of the gate circuits (331) ~ (33a) is as shown in FIG.
As shown in FIG.
E A21 E A41 E Ae during period tB, EB2*EB4. during period tA. A narrow signal 323 that coincides with the starting edge of EBB) is obtained.

This signal S23 is supplied to a delay circuit (36).

However, during this normal reproduction, the signal 523 coincides with the vicinity of the center of the pilot signal to be sampled, so there is no need to delay it, and therefore the selector (
37) does not set the delay time for the delay circuit (36), and the delay circuit (36) sequentially generates the signal S24 that coincides with the signal 323, as shown in FIG. 5N.

This signal 324 is supplied to the pulse generation circuit (43),
Based on the signal 324, a pair of pulses Pi corresponding to each pilot signal to be detected is formed as shown in FIG.
) and a peak hold circuit (21). Based on the pair of pulses Pi, the sampling pulse generation circuit (44) generates sampling pulses SPz and SF3 as shown in FIG. ).

The pulse Pi thus obtained is supplied to the peak hold circuit (21), and the sampling pulses SP1 and SF3 formed based on this pulse Pi are supplied to the sampling and hold circuits (22) and (24), respectively. That will happen.

Therefore, while scanning the track (5B2>) with the head (IB), as is clear from FIG.
The pulse Pi1 peak-holds the crosstalk of the pilot signal PR2+PB4 and pea of the adjacent track (5A2) on the opposite side to the transport direction shown by the arrow (4T) (Fig. 3) in the peak hold circuit (21). state, and the peak hold circuit (2
The output of 1) is supplied to the sampling and hold circuit (22), where it is sampled by the sampling pulse SPt generated at the falling edge of the first pulse pH, and is sent to the differential amplifier (23) as an advanced phase tracking signal. )
is co-supplied to one input end of the .

Further, the second pulse Pt2 of the pulse Pi is the pyro throat signal P of the adjacent track (5^1.) on the tape transport direction side.
B1. The crosstalk of PB3 and PH1 is held at its peak in the peak hold circuit (21), and the output of the peak hold circuit (21) at this time is sent to the other input terminal of the differential amplifier (23) as a tracking signal with a delayed phase. Supplied. Therefore, the differential amplifier (2
3) are pilot signals PB2 and PBl, P'B4 and P
Tracking signals corresponding to the crosstalk of H1, PBe, and PH1 are sequentially compared.

The comparison error signal from the differential amplifier (23) is then supplied to the sampling hold circuit (24), where it is sampled by the sampling pulse SP2 generated at the falling edge of the second pulse P12.

Therefore, from this sampling hold circuit (24), the difference in re-input to the differential amplifier (23) is obtained as a tracking control signal, and this is sent from the output terminal (26) via the contact a side of the switch circuit (25). Although not shown, the tape is supplied to a capstan motor to control the tape transport amount, so that the level difference of the re-input to the differential amplifier (23) is zero.
In other words, when the head (IB) scans the track (5B2), the two trunks (5^2) and (5A1) on both sides
) are controlled so that they span the same amount. That is, scanning is controlled so that the center position of the gap in the bed (IB) in the width direction coincides with the center position of the track (5B2).

The same process is applied to other tracks. For example, when the head scans the track (5A2), as shown on the right side of FIG. and (582) pilot signal PA
t+ PAs+ PAls and PA2. PA4
Since the crosstalk of ゜PAll is obtained, the peak hold circuit (21) sequentially holds the peaks of these as described above, and the sampling pulse SP1 is supplied from the sampling pulse generation circuit (44) to the sampling hold circuit (22). Noiiro・nodo belief% P Av +
The crosstalk of P A11 + P A11 is sampled and a tracking signal is obtained, and this is sent to the next stage differential amplifier.

(23) and the pyro throat signal P A2
+P A4 +PAQ supplies the output from the peak hold circuit (21) corresponding to the crosstalk, and this output is output from the peak hold circuit (21) corresponding to the crosstalk of +PAQ. Ph3 and Ps4
By comparing the tracking signals corresponding to the crosstalk of s PAll and PAG, respectively, and sampling the comparison error signal with the sampling point SP2 supplied to the sampling hold circuit (24),
A tracking control signal for the node (IA) can be obtained.

Similarly, move the track (5B3) to the head (IB).
When scanning, as shown in FIG.
Since the crosstalk of +PB4 +PB8 is obtained, the pilot signal PR? l The crosstalk between PH8 and PBlt is sampled using the sampling pulse SPI, and the differential amplifier (23) outputs the pilot signal PB? and P
By comparing the tracking signals corresponding to the crosstalk of H1, PBII and PH1, and PBll and pea, respectively, and finally sampling the comparison error signal with sampling pulse SP2, a tracking control signal for the head (IB) is obtained. be able to.

Next, during double speed playback, scanning is performed so that the center of the gap width of the rotary head passes through the position shown by the broken line TD in FIG. In other words, one of two adjacent recording tracks (5A) (5B) formed by two rotating heads with different azimuth angles during recording, for example, track (5B).
is scanned in the first half of the tape contact period of each rotary head (IA) (IB), and the other track (5A), for example, is scanned in the second half.

With this scanning method, the rotating heads (IA) and (I
The signals taken out from the tape (2) by B) are connected to the contact P side of the switch circuit ('15A) and the amplifier (18), respectively.
A) and the contact P side of the switch circuit (15B) and the amplifier (
18B) to the switch circuit (19).

This switch circuit (19) is a timing signal generation circuit α
30 Hz switching signal S1 as shown in FIG. 6A from Φ
', the half-rotation period tA including the tape contact period of the head (IA) and the half-rotation period tB including the tape contact period of the head (IB) are alternately switched in the same manner as during recording. Therefore, from this switch circuit (19), an intermittent PCM signal sR is generated segment by segment as shown in FIG. 6G.
This is supplied to a reproduction processor (not shown), where it is demodulated into the original PCM signal, and further supplied to a decoder, where data for each block is detected using a block synchronization signal, and error correction, de-interleaving, etc. The signal is then processed, converted back to an analog audio signal by a D/A converter, and output to the output side.

Tracking control is performed as follows.

Now, for example, the head (IB) straddles two tracks (5A2') (5Ba) in FIG.
When scanning in the direction shown by D, the head (IB
) is the pilot signal FAT of the trunk (5B3) and the truck (5B3) in the area ATL as shown in FIG.
2) Pilot signal PA2 and track (5A2)
In the area AT3, the pilot signal PA8 of the truck (5B3), the pyro throat signal PA4 of the truck (5B2), and the pilot signal PB4 of the trunk (5A2) are reproduced. At T2, the pilot signal PBtt+ of the truck (5A3), the pilot signal pBa of the rack (5A2), and the pyro throat signal PA of the trunk (583).
11 Play. At this time, the reproduced output of the head (IB) from the switch circuit (19) is supplied to a narrowband bandpass filter (20) with a passing center frequency fo, and its output SF As such, only the pilot signal is extracted and supplied to the peak hold circuit (21).

For example, when the head (IA) scans the two tracks (5A3) and (5B4) in the direction shown by the broken line Tp in FIG. ) pilot signal FAT and truck (5B3) pilot signal FAT and truck (5B3).
5A3) pilot signal PB? and play area A
At T3, the pilot signal P of the truck (5B4)
AIO and trunk (583) pilot signal pes
and in the area AT2, the trunk (5^4)
The pilot signal PR121 of the track (5A3) and the pilot signal PAi2 of the track (5B4) are reproduced. At this time, the reproduced output of the head (IA) from the switch circuit (14) is supplied to the bandpass filter (20), and only the pilot signal is taken out as its output Sp, as shown in the right part of Fig. 6H. At the same time, this peak hold circuit (2
1).

In addition, the output SR of the switch circuit (19) is supplied to the bandpass filter (29) in the same manner as described above, and the erasing signal S as shown in FIG. , EA9, E A1□3 During period tA, EBB, EBB, EBll) are typically taken out. These signals S,+ are supplied to a waveform shaping circuit (30) to form a signal S22 as shown in FIG. Circuit (331) ~ (33s)
supplied to

In addition, during double speed playback, a setting command signal from the mode setting circuit (32) causes the window signal generating circuit (3'4) to generate a wind signal SW2 as shown in FIG. 6C and F.
and 8w5 are generated and the gate circuit (332> and (3
3s> as a gate signal, therefore, the output side of the gate circuits (332) and (33s) receives the signal 322 that entered during the period of the window signals SW2 and Sν5.
As a result, the output side of the OR circuit (35) on the output side of the gate circuits (332) and (336) receives the signal S22 as shown in FIG. 6K. A narrow signal 323 that coincides with each rising edge is obtained.

This signal 323 is supplied to a delay circuit (36).

Also, at this time, the delay time setting circuit (38) is selected in the selector (37), and the delay time ta is set in the delay circuit (36).
is set for. The delay circuit (36) has a period tB
Inside, as shown in the left part of the sixth diagram, the signal S23
A signal 324 delayed by the time ta is generated, and the signal 324 is delayed by the time ta.
In A, as shown on the right side of the sixth diagram, a signal S24 corresponding to the signal 323 is generated. This signal S24 is supplied to the pulse generation circuit (43),
Based on the signal 324, as shown in FIG. 6M, a pulse Pi corresponding to each pilot signal to be detected is determined.
is formed and supplied to the sampling pulse generation circuit (44) and the peak hold circuit (21).

In this double-speed playback, one tracking error signal is obtained only during the rainy periods of periods tB and tA, that is, one rotation period of the head.

゛ Therefore, in this case, for example, in the period tB, the first pulse P11 of the pulse Pi from the pulse generation circuit (43)
The pilot signal that appears last in the central area of the track being scanned, that is, the head (IB)
2) and (583), use Figure 6H.
And as shown in M, the peak hold circuit (21
), and during period tA, the second pulse P12 of the pulse Pi from the pulse generating circuit (43) causes the pilot signal that first appears in the central area of the track being scanned, that is, the head (IA) is held at the track (5 ^3)
When scanning across (5B4), the 6th F! ! J
As shown in H and M, the crosstalk of track (5B4) 05 pilot signal PAIO is held at its peak.

Therefore, in this mode, the pulse generating circuit (43) generates only the first pulse Pi of the pulse Pi during one scanning period of the head, for example, the period tB, and generates only the first pulse Pi of the pulse Pi during the other scanning period of the head, such as the period tA. Pulse PI2 of
only occur.

As mentioned above, for example, when the bed (IB) scans across two tracks (5A2) and (5th), the pilot signal PB in the area ATa is
The crosstalk of 4 is the pulse P of the pulse generation circuit (43).
The peak of the first pulse left 11 (M in FIG. 6) of i is held in the peak hold circuit (21), and the output of the peak hold circuit (21) at this time is the sampling pulse 5Pz from the sampling pulse generation circuit (44). (6th
In order to have the same polarity as the tracking error signal during normal playback, the differential amplifier (2
3) is supplied to the other input terminal.

Also, the head (IA) has two tracks (5A3) and (
5B4), the crosstalk of the pilot signal P^1° in the area A'7B causes the second pulse Pi of the pulse generating circuit (43) to scan.
The peak hold circuit (2
1), and the output of the peak hold circuit (21) at this time is supplied to one input terminal of the differential amplifier (23).

Then, the comparison error signal (tracking error signal) from the differential amplifier (23) at this time is sent to the sampling pulse generation circuit (24) in the sampling hold circuit (24).
44) from sampling pulse SP2 (Fig. 6 O
) is sampled by the output terminal (
26).

This derived control signal is supplied to the capstan motor to control the tape transport amount, and the differential amplifier (-23
) is zero, that is, the head (1B) is connected to the track (5A2) and (5B3), and the head (I
When A) scans over two tracks (5^3) and (5B4.), the rotary head is controlled so as to draw a scanning locus as shown by the broken line TD in FIG.

Note that during the above-mentioned double speed playback, the crosstalk of the viroft signal recorded in the central area of the track being scanned is used, but as shown in Figure 6 P to R, Crosstalk of biloft signals recorded at the ends of the tracks may be used.

For example, when the period is set to 1, the peak hold circuit (21) detects the star stalk of the pilot signal PA□□ that appears last in the end area of the track being scanned, and the first pulse of the pulse Pi as shown in Fig. The peak is held in Pi1, and in the period tA, the crosstalk of the pilot signals "P and BT that appears last in the beginning area of the track being scanned is held in the peak bold circuit (21) at the sixth
The peak is bolded at the second pulse P12 of the pulse pt as shown in Figure P.

Then, in period tB, the output of the peak hold circuit (21) is exposed to the sampling hold circuit (22), and is sampled by the sampling pulse sP1 as shown in FIG. As in the case of reproduction, it is supplied to one input terminal of the differential amplifier (23), and during one period tA, the peak hold circuit (
21) is supplied to the other input terminal of the differential amplifier (23), and the comparison error signal (tracking error signal) from the differential amplifier (23) at this time is sampled in the sampling hold circuit (24). Pulse generation circuit (
44) as shown in FIG. 6R, and output this as a tracking control signal to the output terminal (26) side.

At this time, the window signal generating circuit (34) generates the Indian signals SW3 and SW as shown in Figure i6 and E in response to the setting command signal from the mode setting circuit (32). , these signals SVa and SW4
Only the rising edge of the signal S22 that entered during the period is extracted, and the signal 523 (K in Fig. 6) is sent to the output side of the OR circuit (35).
Try to get the following.

At this time, the selector (37) also selects the setting circuit (39).
) is selected, a delay time tb is set for the delay circuit (36), a signal 524 (Fig. 6L) delayed by a time tb from the signal S2x is generated on the output side, and this is sent to the pulse generation circuit (36). 43) to obtain a pulse Pi as shown in FIG. 6P described above.

Also, when playing at 3x speed, the adjacent trunk (5x
A) Even if (5B) have different azimuth angles, the rotating heads (IA) and (IB) scan alternately at 3 track pitches, so the heads scan trunks with different azimuths as in the case of double speed. It doesn't matter. Therefore, in this example, the rotary head is controlled so as to draw a scanning locus as shown by the two-dot chain line TT in FIG.

Now, for example, if the head (IB) is
When scanning a range of scanning width W including a track (5h) as shown by T, the head (IB) scans the tracks (5A3) on both sides of this track (5B3).
(5A2), and as shown in FIG. In the area AT2, the pilot signal P Bt□ of the trunk (5A3) on both sides and the pilot signal PB8 of the truck (582), and the pilot signal PB8 of the truck (582) are reproduced.
B3) and the pilot signal PA11 are regenerated. At this time, the playback output of the head (IB) from the switch circuit (19) is supplied to a narrowband bandpass filter (20) with a passing center frequency fo, and as shown in FIG. 7J, the output SF is a pilot signal. Only the signal is extracted and supplied to the peak hold circuit (21).

In addition, the output SR of the switch circuit (19) is supplied to the band pass filter (29) in the same manner as described above, thereby producing an erasing signal SE (typically E^71) as shown in FIG. 7K.
EA81 EAll ) is taken out. This signal S
, is supplied to the waveform shaping circuit (30) and converted into a signal S22 as shown in Figure 7, and then sent to the rising edge detection circuit (30).
1), where its rising edge is detected and supplied to gate circuits (331) to (33g).

In addition, during triple speed playback, the window signal generation circuit (34) generates window signals SW2 and SW5 as shown in FIGS. ) and (33
5) as a gate signal, therefore, the output side of these gate circuits is supplied with window signals SW2 and SW8.
Only the rising edge of the signal 322 that entered during each period of w5 is substantially taken out, and as a result, the gate circuit (332
) and (336), a narrow signal 323 corresponding to the rising edge of the signal S22 is obtained as shown in FIG. 7M.

This signal S23 is supplied to a delay circuit (36).

However, in this case, as in normal reproduction, the signal S23 coincides with the vicinity of the center of the pilot signal to be sampled, so there is no need to delay it, and therefore, at this time, the delay time for the delay circuit (36) by the selector (37) is is not set, and the delay circuit (36) generates a signal 324 that matches the signal S23, as shown in FIG. 7N.

This signal S24 is supplied to the pulse generation circuit (43),
Based on the signal S24, a pair of pulses Pi corresponding to each pilot signal to be detected is formed as shown in FIG.
) and a peak hold circuit (21). Based on the pair of pulses Pi, the sampling pulse generation circuit (44) generates sampling pulses SPz and SP2 as shown in FIG. supplied to

Therefore, while scanning the track (5B3) with the head (IB), as is clear from FIG.
The pulse pH of the pulse is determined by the peak hold circuit (2
1), the peak hold state is reached, and the output of the peak hold circuit (21) at this time is supplied to the sampling hold circuit (22), and the third pulse P
Sampling pulse SP1 generated at the falling edge of i1
The signal is sampled by , and is supplied as an advanced phase tracking signal to one input terminal of the differential amplifier (23) as in the case of normal reproduction.

Further, the second pulse P12 of the pulse pt is the pilot signal PB4 of the adjacent track (5A2) on the tape transport direction side.
The peak hold circuit (21) holds the crosstalk at its peak, and the output of the peak hold circuit (21) at this time is supplied to the other input terminal of the differential amplifier (23) as a tracking signal with a delayed phase. . Therefore, the differential amplifier (23) uses the pilot signal PB9
The tracking signals corresponding to the crosstalk of PH1 and PH1 are compared. The comparison error signal from the differential amplifier (23) is then supplied to the sampling hold circuit (24), where it is sampled by the sampling pulse SP2 generated at the falling edge of the second pulse P12.

Therefore, from this sampling hold circuit (24), the difference in re-input to the differential amplifier (23) is obtained as a tracking control signal, and this is sent to the switch circuit (25).
The tape is supplied to a capstan motor (not shown) from the output terminal (26) through the contact a side of the tape to control the amount of tape transport, so that the level difference of the re-input to the differential amplifier (23) is zero, that is, Pilot signal PB8 of central area A T8
and PH1, the head (IB) is
It is controlled to draw a scanning locus as shown by the arrow.

The same process is performed for the other tracks, for example, when the head (IA) scans the track (5A4) that is three tracks behind the track (5B3) as shown by the two-dot chain line in Figure 3. 7th FI! As shown in the right part of JJ, the pilot signal Pnt of truck (5^4)
rr PBzo, Psx2 and the pilot signals P of the trucks (5Bs) and (5B4) on both sides thereof
A13 r PA16 + PANT and PA8
1 P AX OI P A12 crosstalk can be obtained, so among these, the tracks on both sides (5BS)
The peak hold circuit (21) successively peak-holds the crosstalk of the pilot signals PA1s and PAlo recorded in the central part (area ATs) of ) is supplied to the sampling pulse SP□ to sample the crosstalk of the pilot signal PA15 to obtain a tracking signal, which is then supplied to the next-stage differential amplifier (23) and outputs a peak corresponding to the crosstalk of the pilot signal PA10. The output from the hold circuit (21) is supplied, and the pilot signal P^16 and the tracking signal corresponding to the crosstalk of PAlo are compared, and the comparison error signal is supplied to the sampling and hold circuit (24). By sampling with the sampling pulse SP2, the head (I
A tracking control signal for A) can be obtained. .

Note that during the above-mentioned 3x speed playback, the crosstalk of the pilot signal recorded in the central area of the trunk being scanned is used, but as shown in Figure 7 RT, Crosstalk of biloft signals recorded at the ends of the tracks may be used.

For example, during the period tB, the pilot signal PB appears last and first in the beginning and end regions of the track being scanned, respectively.
A peak hold circuit (
21), the first pulse Pi as shown in FIG.
On the other hand, during the period tA, the peak hold circuit (2
1), the first pulse Pi as shown in FIG.
The peak hold is performed using the pulse Pit and the second pulse P12.

Then, in period tB, the output of the peak hold circuit (21) (corresponding to the pilot signal PR2) is processed by the sampling pulse SPi as shown in FIG. 7S from the sampling pulse generation circuit (44) in the sampling hold circuit (22). It is sampled and supplied to the other input terminal of the differential amplifier (23) in order to have the same polarity as the tracking error signal during normal playback, and is also supplied to the peak hold circuit (21) corresponding to the biloft signal PBxs.
) is supplied to one input terminal of the differential amplifier (23), and the comparison error signal (tracking error signal) from the differential amplifier (23) at this time is sent to the sampling hold circuit (24) as a sampling pulse. Generation circuit (44
) from the sampling pulse SP as shown in FIG.
2 and output it to the output terminal (26) as a tracking control signal. Also, during the period tA, the pilot signal PA8 and EAl
Perform the same operation for 7.

At this time, in response to the setting command signal from the mode setting circuit (32), the window signal generating circuit (34) generates the wind signal S as shown in FIG. 7 C, E, F, and H.
Wl, SW3 and SW+, S%/s are generated to generate the signal 32 which enters during the period of these wind signals.
Only the rising edge of signal 2 is taken out, and a signal 523 (M in FIG. 7) is obtained at the output side of the OR circuit (35).

At this time, the selector (37) also selects the setting circuit (38).
) is selected, a delay time ta is set for the delay circuit (36), a signal 524 (N in FIG. 7) delayed by the time ta from the signal S23 is generated on its output side, and this is sent to the pulse ordering circuit (36). 43) to obtain a pulse Pi as shown in FIG. 7R described above.

Also, in this case, as mentioned above, the frequency f1 of the erasing signal E is
Since the value of azimuth loss is selected in advance and recorded, the relationship between the azimuth of the head and the azimuth of the track being scanned cannot be ignored.
If the azimuth is different, that is, if the track shifts from the track being scanned and enters an adjacent track, the crosstalk component of the erasing signal E will be reduced accordingly.

Therefore, in this case, when the amount of track deviation of the head is within a predetermined range, the normal operation of detecting the tracking error output according to the amount of trunk deviation and performing tracking control as described above is performed, and the amount of deviation of this trunk is within a predetermined range. If the range is exceeded, the control amount is fixed at a certain potential Vcc, thereby forcibly controlling the head tracking.

The reference values to be compared at this time are the reproduced output of the erasing signal E (reverse azimuth) of the adjacent track when the head is scanning a track with the same azimuth, and the reproduction output of the erasing signal E (reverse azimuth) when the head is scanning a track with the same azimuth. Among the playback outputs of the erasing signal E (same azimuth) for adjacent tracks when the head is scanning tracks with the same azimuth, the minimum value is determined so that it is larger than the playback output of the higher level one. The maximum value is determined so as to be smaller than the reproduced output of the erasing signal E of that track, and the reference value is set at an arbitrary point within the range between the minimum value and the maximum value.

Furthermore, to explain in detail the setting of this reference value, in order to set this reference value without considering the influence of jitter etc.,
For example, in FIG. 3, the head (IB) is connected to the track (5
B2 ) with just tracking, the maximum value is smaller than the playback output of the erasure signal EA2 of the same azimuth, and the minimum value is the adjacent track (5A2) or (5A
Adjacent when scanning a reverse azimuth track (5^2) or (5A1) with just tracking, which is larger than the playback output of the reverse azimuth erase signal EB2 or EBi in 1) and whose head (IB) is shifted by one track. Truck (5
B3 ) or (5B2) erasing signal EA? or EA2
' (both have the same azimuth) or the adjacent track (5
B2 ) or (5B1) erasing signal EA2 or EAl
(both have the same azimuth), and set the reference value within the range of this maximum value and minimum value.

However, if there is an effect such as jitter, as in this example, the recording time of the erasing signal E may be at least shorter than the recording time of the pilot signal P (equivalent to -tp in this example), and the signal adjacent to the trunk being scanned may Since the erasing signals E of both tracks partially overlap and the starting edge of the erasing signal E cannot be detected, a self-clock cannot be formed and there is a possibility that tracking control may malfunction.

For example, if the end of the erase signal EAT and the start of the erase signal EA2 overlap due to the influence of jitter, the head (IB) shifts by one track and just tracks the opposite azimuth track (5A2). The erasing signal EA that has the same azimuth when scanned with ? The sum of the reproduction output of EA2 and the reproduction output of EA2 will be detected. Therefore, as mentioned above, one of the conditions for the minimum value of the reference value is E
A? Alternatively, even if it is determined to be larger than the playback output of EA2, it may cause malfunction. Therefore, in this case, the minimum value needs to be at least larger than the sum of the above-mentioned erasing signal EAT and the playback output of EA2, and that is all. , comparison circuit (
51), the range for setting the reference value will be narrow.

Therefore, as described above, the erasing signal E is recorded so that its starting end is located near the center of the pilot signal P of the adjacent trunk, and at least the ending point is located near the center of the pilot signal P of the adjacent trunk. In other words, the recording time of the erasing signal E is made to be at least shorter than the recording time of the pilot signal P, thereby avoiding the above-described overlap between the erasing signals E. Therefore, in this embodiment, there is no need to set a reference value that takes into account the overlap between these overlapped erase signals E, and the minimum value can be set wider, even if there is an influence of jitter, ivy, etc. This means that the standard value can be set within a wide range.

Incidentally, in this case, the minimum value of the reference value is the reproduction output of the erasing signal E (reverse azimuth) of the adjacent track when the head is scanning tracks of the same azimuth, and the head is shifted by one track. When scanning a reverse azimuth track, determine the reproduction output of the erasing signal E (same azimuth) of the adjacent trunk to be larger than the reproduction output of the higher level one, and determine the maximum value in the same way as above. Bye.

of Make sure it can be absorbed sufficiently.

Therefore, if the detected crosstalk output of the erasing signal E exceeds this reference value, the signal S
23 is generated, and based on this, sampling pulses SP1. Even though SP2 is formed, if it is less than the reference value, the head is no longer scanning the reverse track and the signal S23 is not generated, so that the sampling pulse SP1. SP2 is also not formed.

Therefore, in this embodiment, the erasing signal E
If the crosstalk output is less than this value, it is assumed that the head is significantly out of track, and the head is forcibly shifted to the correct position.

This operation is performed by the circuits after the comparator circuit (51) shown in FIG. The operation of this circuit will now be explained with reference to FIG.

Now, a filter (2) is connected to one input side of the comparison circuit (51).
When a signal SE as shown in FIG. 8B from 9) is supplied, this signal sg is compared with a reference value from a reference power supply (52) supplied to the other input side of the comparator circuit (51). ,
When the signal S is larger than the reference value, a signal 325 as shown in FIG. 8C is generated at the output side of the comparator circuit (51) and is supplied to the flip-flop circuit (53) as a latch pulse. On the other hand, prior to the generation of this signal S26, the falling edge of the switching signal S□' (D in FIG. 8) is detected by the falling edge detection circuit (54), and a signal 32G as shown in E in FIG. 8 is generated on the output side. The flip-flop circuit (53) is reset as shown in FIG. 8H.

Further, the input terminal of the flip-flop circuit (53) is supplied with a switching signal 81' as shown in FIG. When the latch pulse (latch pulse) is supplied, a high level (14) signal 828 is generated on the output side as shown in FIG. 8H, and is supplied to the next stage flip-flop circuit (57).

In addition, the switching signal S□' is detected by the rising edge detection circuit (56).
When the rising edge of S2? is detected, a signal S2? as shown in FIG. 8G is output to the output side. is output, and the flip-flop circuit (
57) is supplied to the clock terminal.

At this point, a high level signal S29 is generated on the output side of the flip-flop circuit (57) as shown in FIG. 8, and is supplied to the switch circuit (25) as a switching control signal. The switch circuit (25) is connected to the contact a side when the signal S29 is at a high level, so that the output terminal (26) receives the signal from the sampling and hold circuit (24) side. A tracking control signal is derived.

On the other hand, if the signal S is less than the reference value, the comparison circuit (51
Since the signal 3211 is not generated at the output side of ), the flip-flop circuit (53) remains reset to the signal 5211, and the output signal 5211 goes to a low level (L) as shown by the broken line in FIG. 8H. Maintained. In this state, the output signal 329 of the flip-flop circuit (57) is also at a high level as shown by the broken line in FIG.

Then, at the rising edge of the switching signal Sl', the detection circuit (56)
When the signal 527 (FIG. 8G) is supplied from the flip-flop circuit (57), the output signal 329 of the flip-flop circuit (57) changes from high level to low level as shown by the broken line in FIG. 8I, and this low level signal 329 is supplied to the switch circuit (25), and the switch circuit (25) switches to the contact side. As a result, the output terminal (26) has a constant potential V from the terminal (58).
A signal with cc is derived, and this signal is supplied to a capstan servo system (not shown) to perform tracking control.

For example, when the constant potential Vcc is positive, the tape is advanced through the capstan servo system, so the head essentially moves to the next track corresponding to its own azimuth and performs a normal tracking operation. Also, the potential Vcc is 0
In this case, the tape advance is slowed down so that the head is essentially pulled back to the track it is currently scanning, thereby entering normal tracking operation.

In this way, in this device, the signal E for erasing the pilot signal has a frequency with a relatively large azimuth loss, and it is also used as a positioning signal for the biloft signal, so that the so-called self-clock extraction circuit The configuration can be simplified and its performance can also be improved.

Furthermore, during playback, this device detects a pilot signal and self-generates a sampling pulse by substantially using the starting edge of the playback output of the erasing signal E recorded in the track as a reference. Since the clock is generated substantially from the track pattern, there is no adverse effect when the pulse PG, such as an offset, is used as a reference.

In addition, an erasing signal E having a frequency where azimuth loss is effective
When the crosstalk output of the head is below the reference value, the control amount is forcibly fixed at a constant potential to perform head tracking control, which enables highly accurate tracking control.

In addition, the tracking position is detected by generating a sampling pulse as described above during each scanning period of each head.In other words, each head generates self-cropping as a sampling pulse on the track pattern each time, and each trunk is tracked individually. Since the position is detected, the influence of jitter is also eliminated.

Furthermore, in each reproduction mode, the detection position of the pilot signal is determined by using the technique of the erasing signal E, or
Alternatively, since the delay time from this edge can be changed, most of the circuit configuration can be made common.

Furthermore, since we are recording in such a way that the starting edge of the erasing signal E, which detects the position of the pilot signal, is located near the center of the pilot signals of adjacent tracks, we take the trouble to set the starting edge of the erasing signal E to the position of the pilot signal. There is no need for a circuit for delaying the position near the center, and the circuit configuration is simplified accordingly. In addition, since the recording time of the erasing signal E is made to be at least shorter than the recording time of the viroft signal P, the erasing signal E of the adjacent trunk is held at a predetermined interval, and therefore, the recording time due to the influence of jitter etc. There is no possibility that the erase signal E generated by the signal E is substantially duplicated between adjacent trunks, so that the comparison circuit (5
It is possible to provide a margin for the setting range of the reference value in 1).

By the way, as mentioned above, the recording portions of the PCM signal as an information signal and the pilot signal for tracking control are divided, and the PCM signal is actually a high-level modulated signal by, for example, 8/10 conversion without a DC component. There is always almost no difference between the time when the level becomes low and the time when the level becomes low. FIG. 9 shows an example of this PCM signal, and it can be seen that the number of high level periods and low level periods is well balanced, and either level does not appear too much.

On the other hand, the pilot signal uses a low frequency that does not appear in the PCM signal, and is recorded directly as described above or by PWM modulation. Then, by detecting a positioning signal for detecting the position of the pilot signal as a control signal recorded in a predetermined relationship with the pilot signal as described above, the start of the pilot signal is detected, In practice, the head position is known from the difference in the crosstalk level of pilot signals of both adjacent tracks, and tracking control is performed.

As described above, the positioning signal can be written in a direct writing method or a method in which it is recorded by PWM modulation.In the case of the direct method, if the frequency is too low, crosstalk increases, so the magnetization is reversed at intervals of, for example, about 8T'. On the other hand, in the PWM modulation method, for example, as shown in FIG. 10, a modulated waveform as shown in FIG. 10A is recorded as a PWM modulated waveform as shown in FIG. 10B.
In order to show a magnetization reversal interval close to the signal, the crosstalk removal rate and override cancellation rate between adjacent trunks are improved.

When performing tracking control, it is necessary to reliably detect the positioning signal of the desired track, the positioning signal of the adjacent track must not be detected, and the remaining component of the override positioning signal must be detected. Do not mistake this for the original positioning signal.

However, in the conventional apparatus configured as described above, the positioning signal is actually detected when the signal is detected due to crosstalk from adjacent tracks, unerased components of override, or poor contact between the tape and the head. There are problems such as the desired positioning signal being difficult to detect at the desired level due to a decrease in the level, or noise components easily being mistakenly detected as the positioning signal. There was an inconvenience that the outgoing signal could not be detected.

OBJECTS OF THE INVENTION In view of the above, the present invention provides a control signal detection circuit that can reliably detect only desired control signals.

Summary of the Invention This invention transmits an information signal and a control signal with different maximum inversion intervals, and the information signal has the same high level and low level occurrence rate even when viewed at short intervals, and the control signal has a high level and a low level. In a signal transmission system in which the occurrence rate of a low level is largely uneven, a waveform equalization means to which the information signal and the control signal are supplied, a comparison means for comparing the output of the waveform equalization means with a reference value, and a comparison means for comparing the output of the waveform equalization means with a reference value; The control signal detection circuit is characterized in that it is equipped with majority decision means for sampling the output of the means and performing majority decision processing, and is capable of reliably detecting a control signal.

Embodiment Hereinafter, a case in which an embodiment of the present invention is applied to a digital signal recording/reproducing apparatus will be explained in detail based on FIGS. 11 to 15.

FIG. 11 shows the circuit configuration of this embodiment. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, the positioning signal to be detected has a frequency sufficiently lower than that of the PCM signal, and the PCM signal does not shift for more than the time it takes to reach either a high level or a low level like the positioning signal. This method was developed with a focus on converting the input signal to a high level or low level (“1” or “O”) signal using a comparing means, and then converting the signal to either a high level or a low level using a majority voting means. The parts with a low level are unified to a high level, and only the desired positioning signal is used.

Therefore, the switch circuit (19) and the bandpass filter (
29), an equalizer (6
0), a zero-cross comparator (61) as a comparing means, and a majority circuit (62) having a sampling function as a majority deciding means are connected in cascade.

The other configurations are the same as in FIG. 1.

As the majority circuit (62), for example, a plurality of D-type flip-flop circuits (63) to (6) as shown in FIG.
7) and a logic circuit (68). The flip-flop circuits (63) to (66) are connected in cascade, and the output of the comparator (61) (Fig. 11) is supplied to the input terminal of the first-stage flip-flop circuit (63) via the input terminal (69). and flip-flop circuits (64) to (66
) is connected to each input terminal of the previous flip-flop circuit (
Outputs from each output terminal Q of 63) to (65) are supplied. The input from the input terminal (69) and each output of the flip-flop circuits (63) to (66) are supplied to the logic circuit (68).

Further, a D-type flip-flop circuit (67) is provided,
The output of the logic circuit (68) is supplied to the input terminal, and the output from the output terminal Q of the flip-flop circuit (67) is taken out to the output terminal (7o). In addition, the flip-flop circuits (63) to (67) have clock terminals (
71). As this clock, a reproduced channel clock by a PLL or a clock near the channel clock frequency is used.

Furthermore, as a specific example of the logic circuit (68), the one shown in FIG. 13 is used, for example. In FIG. 12, the flip-flop circuit (66)
, (65), (64) and (63) are a, , b, c and d, the input obtained at the input terminal (69) is 010, and the output of the thick circuit (68) is 01lTPUT.
Then, this 0UTPIIT is expressed as follows.

0UTPUT = abc + abd + abe
+ acd ten ace+ ade + cde = (a+b) c (d+e) + (a+
b+c) de + ab (c+d+e) In other words, the circuit shown in FIG. 13 is constructed to satisfy the above equation. Next, the operation of the circuit shown in FIG. 11 will be explained with reference to the signal waveforms shown in FIG. 14.

Assume now that a positioning signal is recorded on the tape as a PWM modulated waveform as shown in FIG. 14A. When this playback output is passed through an equalizer (6o),
The waveform is equalized at the output side, and a signal with a waveform as shown in FIG. 14B is obtained on the output side. This signal waveform is deformed due to the influence of peak shifts that cannot be equalized, noise, fluctuations due to the envelope of low-frequency components, override residual components, crosstalk components, and the like. Even if this signal is passed through the band pass filter (29), the level of the positioning signal will not be stabilized. Therefore, first, the output of the equalizer (60) is supplied to the comparator (61) and the reference value (
A signal with a waveform as shown in FIG. 14C is obtained on the output side. This signal removes noise that does not exceed the reference value, but as can be seen from FIG. 14C, it is often erroneous.

The output of this comparator (61) is supplied to the majority circuit (62), which uses, for example, a channel clock extracted from the reproduced waveform (equivalent to the clock from the terminal (42)) or a clock with a frequency near the frequency of the channel clock. , sampling is performed as shown in Fig. 14 to obtain a signal with a waveform as shown in Fig. 14E. In other words, the majority circuit (6
2) Flip-flop circuits (63) to (66)
Sampling is performed in (Fig. 12).

The signal thus obtained is supplied to the logic circuit (6B) (FIG. 12 or 13) in the majority circuit (62) to perform majority decision processing. That is, for example, if three or more of the five inputs are "1", "1" is output, and if two or less are "1", "0" is output. This operation is performed sequentially while shifting one bit at a time, and as a result, a signal having a waveform as shown in FIG. 14F is obtained at the output side of the majority circuit (62).

From this, it can be seen that the noise of high frequency components is removed. This is because the majority circuit (62) can remove noise because the positioning signal involved in tracking control is a signal that maintains the same level for five consecutive points or more. In other words, the true positioning signal is the level (
This is because the signal needs to be unified to the level of the one with the greater number of "1" and "O").The signal obtained by the majority circuit (62) is passed through the band pass filter (29) to the waveform shaping circuit. (30), where the waveform is shaped into the signal Sl.

In this way, a true positioning signal as a control signal can be reliably detected.

In the case of Fig. 14, at least the positioning signal is PW.
This was the case when it was M-modulated and recorded on tape,
General waveforms other than PWM modulation waveforms, such as directly recorded waveforms, can also be processed in the same way.

FIG. 15 shows an example of this. For example, suppose that a positioning signal with a waveform as shown in FIG. 15A is recorded on a tape.
By passing through the signal, a signal with a waveform as shown in FIG. 15B is obtained. By using this signal as a reference value in the comparator (61), a signal having a waveform as shown in FIG. 15C is obtained at its output side.

By sampling this signal in the majority circuit (62) as shown in Figure 15, a signal having a waveform as shown in Figure 15E is obtained. By further subjecting this signal to the majority decision processing as described above, a positioning signal as shown in FIG. 15F is obtained at the output side of the majority decision circuit (62).

In this way, the true positioning signal can be reliably detected in this case as well. In other words, in this case as well, the frequency of the positioning signal is lower than that of the PCM signal, and the duration of the same level is longer, so that the majority circuit (62) can effectively remove noise.

Although not shown in FIG. 11, the PCM data reproduction system includes an equalizer and an equalizer on the output side of the switch circuit (19).
It is common to provide a zero-cross comparator, a demodulator, a decoder, and a D/A converter. Therefore, in order to obtain the above-mentioned control signal, an equalizer (60) and a zero-cross comparator (
61), the equalizer and zero-cross comparator used in the PCM data reproduction system may be shared.

Application Example In the above embodiment, the present invention is applied to a digital signal recording/reproducing device, but the present invention is not limited to this, and can be applied to other signal transmission systems that perform signal processing including control signals. is similarly applicable.

Effects of the Invention As described above, according to the present invention, the control signal is waveform-equalized and compared with a reference value, and the output thereof is sampled and subjected to majority voting processing, so that the control signal can be reliably detected.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram according to the prior art of the present invention, FIG. 2 is a diagram showing an example of the rotary head device used in FIG. 1,
FIG. 3 is a diagram showing an overview of the recording trunk pattern, FIG. 4 is a signal waveform diagram for explaining the recording operation in FIG. 1, and FIG. 5 is for explaining the normal playback operation in FIG. 1. Fig. 6 is a signal waveform diagram for explaining the double speed playback operation in Fig. 1;
The figure is a signal waveform diagram for explaining the triple speed playback operation in Figure 1, Figure 8 is a signal waveform diagram for explaining the playback operation in Figure 2, and Figures 9 and 10 are signal waveform diagrams for explaining the playback operation in Figure 1. FIG. 11 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 12 is a circuit diagram showing an example of the main part of the invention, and FIG. 13 is the logic circuit (68) of FIG. 12. of-
Connection diagrams illustrating examples, FIGS. 14 and 15 are signal waveform diagrams for explaining the operation of FIG. 11. (LA) (IB) is a rotating magnetic head, (2) is a magnetic tape, (6) is a pilot signal oscillator, (6A)
, (6B) is the erase signal oscillator, (?), (
7A), (7B) are recording waveform generation circuits, (16)
, (17A) to (17B). (36) is a delay circuit, (8A) and (8B) are edge detection circuits, (20) and (29) are pan and dopass filters, (21) is a peak hold circuit, ' (22
), (24) is ``sampling hold circuit, (
23) is a differential amplifier, (25) is a switch circuit, (30
) is a waveform shaping circuit, (31) is a rising edge detection circuit, (3
2) is a mode setting circuit, (331) to (33g) are gate circuits, (34) is a window signal generation circuit, (37)
is a delay time setting selector, (3B), (39) is a delay time setting circuit, (43) is a pulse generation circuit, (44)
(60) is an equalizer, (61) is a zero-cross comparator, and (62) is a majority circuit.

Claims (1)

[Claims] An information signal and a control signal having different maximum inversion intervals are transmitted, and the information signal has the same high level and low level appearance rate even when viewed at short intervals, and the control signal has a high level and low level appearance rate? In a signal transmission system with a large bias, a waveform equalization means to which the information signal and the control signal are supplied, a comparison means for comparing the output of the waveform equalization means with a reference value, and a sampling means for sampling the output of the comparison means. 1. A control signal detection circuit comprising: majority decision means for performing majority decision processing.