JPS61269498A - Terminal controller of time-division exchange - Google Patents

Abstract

PURPOSE:To permit terminal control packages which differ in the number of packaged circuits to be present on the same highway efficiently and to improve the use efficiency of the data highway by assigning respective channels to the highway without any vacancy. CONSTITUTION:Plural circuit package units 10 where terminal control circuits 14 less than a specific number and a timing generating circuit 12 which receives a control signal and controls the terminal control circuits are packaged are connected to a time-division channel network NW 100. The timing generating circuit 12 of one circuit package unit included in each group obtained by grouping terminal control circuits of plural circuit package units by a specific number is supplied with a main synchronizing signal SYNA synchronizing with the period of channels as many as the specific number and a corresponding start signal PKG and a group including remaining circuit packages units among those groups supplies timing generating circuits of the remaining circuit package units with a subordinate synchronizing signal SYNB which is out of phase with the main synchronizing signal by four channels equal to the difference between specific number of the number of terminal control circuits mounted on the circuit package unit, and a corresponding start signal PKG.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time division switch, more specifically, a time division switch including a terminal control circuit that is located between a line and a time division communication channel network and interfaces the two. The present invention relates to a terminal control device.

(Prior Art) As is well known, terminal control circuits such as line circuits and trunk circuits in the time division switching system are located between lines such as subscriber lines or trunk lines and the time division communication channel network, and are unique to each line. The two are interfaced by transmitting and receiving communication data in time slots, that is, time division channels assigned to the two.

For example, in a terminal control circuit package in which a predetermined basic number of terminal control circuits are mounted as modules in one package, the terminal control circuit package receives the control signals necessary for control from the time-sharing communication channel network to which it is connected, and performs various timing control circuits. This also includes a timing generation circuit that generates signals. Terminal control circuit packages equipped with such circuits are installed in accordance with the number of lines required and connected to the network and lines to form a switching device.

(Problem to be solved by the invention) However, in reality, depending on the circumstances in which the switching device is introduced,
The number of lines that is an integer multiple of the predetermined number of basic circuits mentioned above is not necessarily implemented, and depending on various conditions, there may be vacant terminal control circuits that do not accommodate lines or are not implemented. . In conventional switching equipment, free channels are assigned to the data highway of the time division network even for such free terminal control circuits.

These unused channels cannot be used by terminal control circuits of other packages, resulting in a decrease in channel usage efficiency for the highway as a whole. In other words, even though there are vacant channels, they cannot be allocated to other terminal control circuits, resulting in a shortage of channels that can be accommodated by the system as a whole.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a terminal control device for a time-division exchange, which eliminates the drawbacks of the prior art and achieves high channel usage efficiency as a whole device.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention has a predetermined number of terminal control circuits or less, and a system in which the terminal control circuits use highway channels in a time-sharing manner in response to a control signal. In a terminal control device for a time division exchange, the control signal is At least, a first synchronization signal is synchronized during a period in which the number of channels is equal to the predetermined number, and a first synchronization signal is synchronized in a period in which the number of channels is equal to the difference between the predetermined number and the number of terminal control circuits mounted in the circuit mounting unit. a second synchronization signal that is out of phase with the synchronization signal; and a plurality of activation signals that are out of phase with each other for a period of a number of channels equal to the predetermined number for activating the timing means, over a plurality of circuit mounting units. A corresponding one of the first synchronization signal and a start signal is supplied to the timing signal generation means of one circuit mounting unit included in each group in which terminal control circuits are divided into a predetermined number of groups, and In the case where the remaining circuit mounting units are included, the timing generating means of the remaining circuit mounting units is characterized by a terminal control device of a time division exchange that supplies the second synchronization signal and the corresponding activation signal.

(Function) According to the present invention, a circuit mounting unit in which fewer than a predetermined number of terminal control circuits are mounted constitutes a common group with other similar circuit mounting units, and among them, the former has a first synchronization and to the latter at least a second synchronization signal. Furthermore, a starting signal that commonly corresponds to the circuit mounting units included in each group is supplied to each group. Therefore, by such grouping, each terminal control circuit is accommodated on the highway so that there are no vacant channels.
Data is sent and received using the assigned channel. Therefore, even if terminal control circuit mounting units with different numbers of circuits are mixedly accommodated in the same way, empty channels will not occur, and the data highway will be used efficiently.

(Embodiment) Next, an embodiment of a terminal control device for a time division exchange according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, an example of a mounting unit of the terminal control circuit applied to the embodiment of the present invention is shown.

As an example of this terminal control circuit mounting unit, the terminal control circuit package 10 includes a timing generation circuit 12 and a terminal control circuit 14, which are mounted on one electronic circuit board. In this embodiment, four terminal control circuits 14 are installed.

The timing generation circuit 12 is a terminal control circuit package 1
0 is connected to the time division communication channel network (NW) 100 (Fig. 1) of the time division exchange equipped with the control signal CL.
K, SYN, and PKG are each received at terminal 20 to form various timing signals, and output terminals 22,
This is a circuit that outputs to 24, 26 and 28.

As can be seen from FIG. 3, the control signal CLK is a clock signal synchronized with each bit of network data sent from the network 100. SYN is a signal indicating the beginning of network data sent from the network 100. Further, the PKG is a signal indicating that the package 10 is energized. Signal line 22, 2
4.26 and 28 are data transmission/reception synchronization signals that define the periods during which the corresponding terminal control circuits 14 transmit and receive data with the network 100. Note that in the subsequent figures, signals are indicated by reference numerals of corresponding signal lines. A pit clock is supplied to the signal line 3o.

These signal lines 22, 24, 26, and 28 are connected to 11) $2.43 and ≠4 of the terminal control circuit 14, respectively, and the signal line 30 is connected to each terminal control circuit 14. The terminal control circuit 14 functions, for example, as a line circuit or a trunk circuit, and one of the ports 32
is connected via a transformer 34 to a line 36 such as a subscriber line or a trunk line. The other port 38 is commonly connected to the terminal 38 in each circuit 14 . The terminal 38 is connected to the highway of the network 100 and transmits and receives highway data DATA. As will be described, the terminal control circuit 14 uses the timing signal supplied from the timing generation circuit 12 to generate the highway data DA.
It has a function of interfacing the TA and the line 26.

As can be seen from FIG. 3, in this embodiment, the data DATA
consists of 8 bits, and the period of signal PKG assigned to one package 10 (T2 to be described later, FIG. 4) is used by four terminal control circuits 14 in a time-division manner.

Referring to FIG. 1, an embodiment of the present invention is shown in which six such packages 10 are mounted and connected to a network 100. In the figures explained below,
Components that are the same as those shown in FIG. 2 are designated with the same reference numerals.

In this embodiment, the two packages 1 on the left side in the figure
0 functions as a line circuit (LC)≠1 and ≠2,
Each package 10 has four circuits mounted thereon. In other words, all four circuits of the packages ≠1 and ≠2 accommodate subscriber lines in the terminal control circuit 14 included in each package, and function as line circuits. Also on the right side of them 4
The package 10 has a trunk circuit (TRK)≠1~
≠4, and each package 10 has two circuits mounted thereon. That is, those packages +1 to +4 are
A trunk line is accommodated in two terminal control circuits 14 included in each circuit, and functions as a trunk circuit.

The clock terminal 16 of each package 1θ is commonly connected to the CLK terminal 102 of the network 100. In addition, the synchronization signal terminals 18 of packages LC+1, LC2゜TRK+1 and TRK3 are connected to the network lθO.
The synchronization signal terminals 18 of the four cages TRK≠2 and TRK-IN are commonly connected to the 5YNB terminal 106 of the network 100. In this embodiment, the network 100 outputs a synchronization signal indicating the beginning of the network data sent from the network 100, that is, a main synchronization signal 5YNA, to the terminal 104, and outputs the signal 5YNA to the terminal 106, as shown in FIG. 1 to output a sub-synchronization signal 5YNB delayed by a two-channel period TI (FIG. 4).

Package L (PKG terminal 20 of 41 and LC+ 2
is the PKGI terminal 10g and P of the network 100.
They are respectively connected to the KG2 terminal 110. The PKG terminals 20 of the packages TRK≠1 and TRKS2 are commonly connected to the PKG3 terminal 112 of the network 100. Similarly packages TR13 and TRK4'
40PKG terminal 20, network 100 PKG4
They are commonly connected to terminal 114. As shown in FIG. 4, the package activation signals PKGI to PKG4 are supplied from the network 100 at timings that are out of phase with each other by a four-channel period 2T1.

Further, the data terminal 38 of each pancage 10 is commonly connected to the DATA terminal 116 of the network 100. As is clear from FIG. 4, in this embodiment, 16 channels CHI to CHI6 are allocated to each highway. More specifically, which channels
CH2-CH2 is line circuit LC temple IVc1CH5-C
H8 is line circuit LC1K, CH9 and CHI O is trunk circuit TRK+I KCHII and CH12 is trunk circuit TRK≠2, CHI 3 and CH14
is connected to the trunk circuit TRK≠3, connected CH15 and CH
I6 are respectively assigned to trunk circuits TRK≠4.

As will be seen from now on, in this embodiment, one frame of the data H/L way is divided into 16 channels, and each package 10 is divided into groups such that four terminal control circuits 14 form one group. There is. Therefore, two trunk packages TRK+l to TRK≠4 constitute one group.

That is, the package activation signal PKG- is commonly supplied to the two trunk packages, and one package in each group is supplied with the main synchronization signal 5YNA, and the other package is supplied with the sub-synchronization signal 5YNB.

In this example, there are only two types of packages: a package with four circuits and a package with two circuits, so there is only one type of sub synchronization signal 5YNB, and the phase difference with respect to the main synchronization signal is determined by the terminals that can be accommodated in each group. the number of control circuits 14;
That is, in this example, the period TI is set as the difference between "4" and the number of terminal control circuits 14 actually installed, that is, "2" in this trunk package example, that is, the number of channels equal to "2". ing.

Such channel allocation is realized by the following operation of this embodiment. First, the network 100 sets the package activation signal PKGI to high level to activate the package LC.
Start I. At the same time, the synchronization signal 5YNA is activated, and in response to this, the timing circuit 12 of the package LC≠1 sequentially sets the four transmission/reception synchronization signals 22, 24, 26, and 28 to high level to switch the terminal control circuit 14 from +1 to Activate sequentially up to +4. As a result, the four terminal control circuits 14 mounted in this package sequentially transmit and receive data DATA to and from the line 36 on highway channels CHI to CH4t.

Next, the network 100 sends the package activation signal PKG
3 to high level and packages TRK1 and TRK2
Start. At this time, first, the synchronization signal 5YNA is input to the package TRK≠1, and furthermore, after the lapse of two channel periods, the sub-synchronization signal 5YNB is input to the package TRK2. First, in package TRK+1, the synchronization signal S
In response to YNA, timing circuit 12 sequentially brings four transmit/receive synchronization signals 22, 24, 26, and 28 to a high level. However, in this embodiment, two terminal control circuits 14, +1 and +2, are mounted in the same package IO. Therefore, in response to the previous two synchronization signals 22 and 24, the +1 and +2 terminal control circuits 14 sequentially transmit and receive data DATA to and from the line 36 on the highway channels CH9 and CHIOK.

Next, in the package TRK≠2, the timing circuit 12 transmits the four transmission/reception synchronization signals 2 in response to the sub-synchronization signal 5YNH.
2, 24, 26 and 28 are raised to high level in sequence. In the same package TRK4I-2, two terminal control circuits 14 +1 and +2 are mounted in the present embodiment, similarly to the package TRK+1. Therefore, the previous two synchronization signals 2
2 and 24, the terminal control circuit 14 of +1 and +2
sequentially transmits and receives data DATA to and from line 36 on highway channels CHII and CHI2.

Next, the network 100 sends the package activation signal PKG
4 to high level and package TRK+3 and TRK≠4
Start. In the same way as above, pack Niji T
Synchronous signal 5YNA is connected to RK3, and package TR
14, the sub synchronization signal SYNB is input. Packages TRK+3 and TRK1 each have only two terminal control circuits 14 mounted therein. Therefore,
Same mK as for package TRK41 and TRK≠2
Then, in package TRK=#3, for channels CH13 and CH14, and i? In the cage TRK+4, data DATA is transmitted and received between the channels CH15 and CH16 and the line 36.

In this way, packages LC≠1, L(4
2.

Highway channels CHI-CH16 for each terminal control circuit 14 implemented in TRK≠1 to TRK≠4
Data is transmitted and received.

The embodiments described here are for illustrating the present invention, and the present invention is not necessarily limited thereto, and modifications that can be made by those skilled in the art without departing from the spirit of the present invention. and modifications are within the scope of the invention.

For example, in the illustrated embodiment, a cage LC≠1 accommodates four circuits, and a cage LC≠1 accommodates two circuits).
'RKl, etc. were accommodated together on the same highway. The present invention is not limited to this number, but can be effectively applied to devices with any other number of circuits that can be accommodated.

For example, packages with any number of circuits can be mixed and mounted, such as a package that accommodates 166 circuits, a package that accommodates 8 circuits, a pan cage that accommodates 6 circuits, a package that accommodates 4 circuits, a package that accommodates 2 circuits, a package that accommodates 1 circuit, etc. may be accommodated on the same highway. In that case, the network is configured to form sub-synchronization signals of a type corresponding to the type of the number of circuits accommodated, and to supply them to the corresponding packages.

These sub-synchronization signals are formed by delaying the main synchronization signal by a period corresponding to the number of channels to be mounted and the number of circuits accommodated in the cage. For example, when a package accommodating 166 circuits and a package accommodating 8 circuits are used together, the configuration may be such that two synchronization signals whose phases are shifted by 8 channel periods are supplied. 1. When a package accommodating 8 circuits and a pancage accommodating 2 circuits are used together, the configuration may be such that a sub sync signal whose phase is delayed by 6 channel periods with respect to the main sync signal is generated.

For comparison, in the conventional configuration example shown in FIG.
among which packages LC≠1 and L
Csu2 has four terminal control circuits J4, and packages TRKsu1 and TRKsu2 have two terminal control circuits 14.
The circuit is housed. As will be seen from now on, in the conventional configuration, unlike the embodiment of the present invention, each gas cage l0
All IIc are supplied with one type of synchronization signal SYN, and the package TRK≠1 has only two circuits mounted.
Similarly to the packages LCs1 and L (42) in which four circuits are mounted, the TRKs 2 and 4 are each supplied with their own gear activation signals PKGI to PKG4.

Therefore, as can be seen from the time chart of FIG. 6, the same channel period TI as that of packages LC≠1 and LC+2 is assigned to TRK+1 and TRK2 as well. Therefore, for packages TRK+1 and TRK2, which have only two circuits mounted, channels cH11, CH12 and CH3S
, CH16 is left empty, resulting in low channel efficiency. In this embodiment, the highway can be used efficiently without such vacant channels.

In this manner, in this embodiment, each channel can be assigned to a highway so that no vacant channels are left. Therefore, even if terminal control circuits/e-no-cages with different numbers of implemented circuits are mixedly accommodated in the same way, empty channels will not occur, and the data highway will be used efficiently.

As a result, the required network capacity of the entire switching system can be minimized, the amount of hardware constituting the network is reduced, and the configuration of the entire system including the control device therefor is also simplified. Moreover, due to such channel allocation with no available space, the exchange control program that controls the network can also handle each channel continuously. Therefore, the program configuration is also simplified.

(Effects of the Invention) As described above, according to the present invention, each channel can be assigned to a highway so that no vacant channels are left. Therefore, terminal control circuit packages with different numbers of implemented circuits can be efficiently accommodated on the same highway, and data and
・High efficiency in using iway.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention in which the terminal control circuit package shown in FIG. 2 is connected to a network, and FIG. 2 is a block diagram of a terminal control circuit package applied to the embodiment of the present invention. A functional block diagram showing an example; FIG. 3 is a waveform diagram showing signal waveforms appearing in each part of the circuit shown in FIG. 2; FIG. 4 is a timing waveform diagram for explaining the operation of the circuit shown in FIG. 1. , FIG. 5 is a diagram similar to FIG. 1 showing a configuration example of a terminal control device according to the prior art, and FIG. 6 is a timing waveform diagram similar to FIG. 4 showing the operation of the device shown in FIG. 5. . Explanation of symbols of main parts 10... Terminal control circuit package, 12... Timing creation circuit, 14... Terminal control circuit, 18... Synchronization signal terminal, 20... Gutsucage start signal terminal, 1
00...Network. Patent Applicant Oki Electric Industry Co., Ltd. Device 3 Relationship with the person making the amendment Patent application office (
105) 1-7-12-4 Toranomon, Minato-ku, Tokyo.
Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2 Oki Electric Industry Co., Ltd. Name (6892) Patent attorney Toshiaki Suzuki Telephone number 501-
31.11 (Major Representative) 5. Column 6 of "Detailed Description of the Invention" in the specification to be amended, contents of the amendment, attached sheet, contents of the amendment (1) Line 15 of page 2 of the specification. , page 3, ``time-division communication path'' in the ] and 9th lines is corrected to ``time-division communication path.'' (2) "Circuit 26" on page 8, line 17 of the same book is corrected to "circuit 36." (3) Insert the following sentence between lines 9 and 10 on page 13 of the same book. [Next, the network 100 sends the package activation signal PKG
2 to high level and start LC#2. At the same time, the synchronizing signal 5YNA is activated, and in response to this, the knock cage LC#2 is activated by the above-mentioned package LC#1.
In the same way as in the case of
Send and receive. "that's all

Claims (1)

[Scope of Claims] A predetermined number or less of terminal control circuits that control lines, and timing means that receives a control signal and controls the terminal control circuits so that the terminal control circuits use highway channels in a time-sharing manner. In a terminal control device for a time-sharing exchange, including a plurality of mounted circuit units and a control signal generating means for generating the control signal in response to the highway, the control signal generating means includes at least the predetermined number of circuits. A first synchronization signal synchronized during a period of the number of channels equal to generating, as the control signal, a second synchronization signal with a shifted phase and a plurality of activation signals for activating the timing means with phases shifted from each other by a period of a number of channels equal to the predetermined number; A corresponding one of the first synchronization signal and the activation signal is supplied to the timing signal generating means of one circuit mounting unit included in each group in which the terminal control circuits are divided into the predetermined number of groups across the mounting units. , in the group including the remaining circuit-mounted units, the timing generation means of the remaining circuit-mounted units are supplied with the second synchronization signal and the corresponding activation signal; Switch terminal control device.