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JPS61265835A - Formation of metallic pattern - Google Patents

Formation of metallic pattern

Info

Publication number
JPS61265835A
JPS61265835A JP10793785A JP10793785A JPS61265835A JP S61265835 A JPS61265835 A JP S61265835A JP 10793785 A JP10793785 A JP 10793785A JP 10793785 A JP10793785 A JP 10793785A JP S61265835 A JPS61265835 A JP S61265835A
Authority
JP
Japan
Prior art keywords
film
photoresist
metal
metal film
polycrystalline semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10793785A
Other languages
Japanese (ja)
Other versions
JP2544100B2 (en
Inventor
Atsuo Hattori
敦夫 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Gakki Co Ltd
Original Assignee
Nippon Gakki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Gakki Co Ltd filed Critical Nippon Gakki Co Ltd
Priority to JP60107937A priority Critical patent/JP2544100B2/en
Publication of JPS61265835A publication Critical patent/JPS61265835A/en
Application granted granted Critical
Publication of JP2544100B2 publication Critical patent/JP2544100B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To make it possible to perform minute patterning of metal, by using a photoresist mask, which is formed on a polycrystalline semiconductor film that is formed on a metal film to a specified thickness, as a mask, and performing dry etching of the metal film. CONSTITUTION:A metal film 14 is formed on an insulating film 12 on a semiconductor substrate 10. On the film 14, a polysilicon film 16 is formed as a polycrystalline semiconductor film so that the reflectivity with respect to the exposure wavelength becomes approximately minimum. On the film 16, a photoresist film 18 corresponding to a desired wiring pattern is formed by a photolithography technology. At this time, the light reflection from the lower layer of the photoresist is suppressed in photoresist exposure. Thus, the photoresist pattern characterized by less dispersion in size and shape is obtained. With the photoresist film 18 as a mask, dry etching is performed, and a metal film 14A and a polysilicon film 16A are obtained. Thus, the metal film 14A, which has excellent fidelity to the wiring pattern, can be obtained.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、LSI等の半導体装置の微細配線形成に用
いるに好適な金属パターン形成法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a metal pattern forming method suitable for use in forming fine wiring in semiconductor devices such as LSIs.

[発明の概要] この発明は、AI又はA1合金等の高反射率金属膜の表
面にポリシリコン膜を露光波長に対する反射率がほぼ極
小となる厚さで形成した後、その上にホトリソグラフィ
技術によりホトレジスト膜を形成し、このホトレジスト
膜をマスクとじてドライエツチングを実施することによ
り金属の微細パターニングを可能にしたものである。
[Summary of the Invention] This invention involves forming a polysilicon film on the surface of a high reflectivity metal film such as AI or A1 alloy to a thickness that makes the reflectance at an exposure wavelength almost minimum, and then applying photolithography technology on the polysilicon film. By forming a photoresist film and performing dry etching using this photoresist film as a mask, fine patterning of metal becomes possible.

[従来の技術] 従来、LSI等の微細配線形成にあたっては、半導体ウ
ェハ上面にAI又はA1合金等の金属膜を被着した後、
この金属膜上にホトリソグラフィ技術により所望の配線
パターンに対応するホトレジスト膜を形成し、このホト
レジスト膜をマスクとして金属膜をドライエッチする方
法が知られている。
[Prior Art] Conventionally, when forming fine wiring for LSI etc., after depositing a metal film such as AI or A1 alloy on the upper surface of a semiconductor wafer,
A method is known in which a photoresist film corresponding to a desired wiring pattern is formed on this metal film by photolithography technology, and the metal film is dry-etched using this photoresist film as a mask.

この方法によると、ホトレジストに配線パターンを露光
により転写する際、金属膜の材料であるAI又はA1合
金の反射率が高いため、ウェハ上の段差等による散乱反
射光がホトレジストの不所望の部分まで露光してしまい
、ホトレジストパターンの寸法や形状にばらつきが生ず
ることが多かった。このため、個々の配線に太りゃ細り
を生じ。
According to this method, when the wiring pattern is transferred to the photoresist by exposure, because the reflectance of AI or A1 alloy, which is the material of the metal film, is high, the scattered reflected light from the steps on the wafer, etc., reaches undesired parts of the photoresist. In many cases, the photoresist pattern was exposed to light, resulting in variations in the dimensions and shape of the photoresist pattern. For this reason, individual wiring becomes thicker or thinner.

信頼性低下の一因になっていた。This was a cause of decreased reliability.

このような問題に対処する方法としては、(イ) AI
又はA1合金等の高反射率金属膜の表面に反射率の低い
高融点金属膜を被着するもの(例えば特開昭5El−1
54027号公報参照)、(ロ)高反射率金属膜の表面
に光吸収性の有機絶縁膜(例えばBREWER5CIE
NCE INC,からrARClの名称で販売されてい
るもの)を被着するものなどが知られている。
As a way to deal with such problems, (a) AI
Or a method in which a high melting point metal film with low reflectance is applied to the surface of a high reflectance metal film such as A1 alloy (for example, JP-A No. 5 El-1)
54027), (b) a light-absorbing organic insulating film (for example, BREWER5CIE) on the surface of the high reflectance metal film.
Some are known, such as those coated with RARCl (sold under the name rARCl by NCE INC.).

[発明が解決しようとする問題点] 上記(イ)の従来法によると、使用可能な金属でAI等
より十分に反射率が低いものは少ないので、大きな反射
防止効果を期待することはできない。
[Problems to be Solved by the Invention] According to the conventional method (a) above, there are few metals that can be used that have sufficiently lower reflectance than AI etc., so a large antireflection effect cannot be expected.

また、上記(ロ)の従来法によると、相当の反射防止効
果を期待できるが、簡単な工程で細い配線幅を実現する
のが困難である。すなわち、ウェハ上で例えば0.5[
μmlの段差がある場合、有 −機絶縁膜を段差の上部
で十分な反射防止効果が得られる0、2  [pm]以
上の膜厚で塗布すると、段差の底部では0.5[μm1
以上の膜厚となる0通常、この種の有機絶縁膜は、ホト
レジストの現像時にホトレジスト現像液で選択的にエッ
チされ、この現像時のエッチ処理でホトレジスト直下の
部分に等方的なサイドエッチを受ける。従って、段差の
底部で0.5  [lLm]の厚さに有機絶縁膜を形成
した場合には、段差の上部ではホトレジスト直下の部分
に両サイドから0.5  [pm]ずつで合計1  [
pm]のサイドエッチが入ることになり、1  [gm
]以下の配線幅を実現することができない。
Further, according to the conventional method (b) above, a considerable antireflection effect can be expected, but it is difficult to realize a narrow wiring width with a simple process. That is, for example, 0.5[
If there is a step difference of μml, if an organic insulating film is applied at a thickness of 0.2 [μm] or more at the top of the step to obtain a sufficient antireflection effect, the thickness of the organic insulating film at the bottom of the step will be 0.5 [μm1].
Normally, this type of organic insulating film is selectively etched with a photoresist developer during development of the photoresist, and the etch process during development creates an isotropic side etch in the area directly below the photoresist. receive. Therefore, when an organic insulating film is formed to a thickness of 0.5 [lLm] at the bottom of the step, a total of 1
There will be a side etch of 1 [gm].
] It is not possible to realize the following wiring width.

このような微細な配線幅を実現するため、AI又はA1
合金の金属膜を形成する前に平坦化工程を追加すること
によってウニ八全面で0.2  [ILm]程度の膜厚
を確保することも可能であるが、これでは工程は著しく
複雑化するのを免れない。
In order to realize such a fine wiring width, AI or A1
It is possible to secure a film thickness of about 0.2 [ILm] over the entire surface of the sea urchin by adding a planarization process before forming the alloy metal film, but this would significantly complicate the process. cannot be avoided.

[問題点を解決するための手段] この発明は、上記した問題点を解決するためになされた
ものであって、簡単な工程で金属の微細バターニングを
可能にすることを目的とするものである。
[Means for Solving the Problems] This invention has been made to solve the above-mentioned problems, and its purpose is to enable fine buttering of metal in a simple process. be.

すなわち、この発明による金属パターン形成法は、基板
上にA1又はA1合金等の金属膜を形成した後、この金
属膜をおおってポリシリコン等の多結晶半導体膜を露光
波長に対する反射率がほぼ極小となる厚さで形成し、こ
の多結晶半導体膜上にホトリソグラフィ技術により所望
のパターンに対応するホトレジスト膜を形成し、このホ
トレジスト膜をマスクとして多結晶半導体膜及び金属膜
をドライエッチするようにしたものである。
That is, in the metal pattern forming method according to the present invention, after forming a metal film such as A1 or A1 alloy on a substrate, the metal film is covered with a polycrystalline semiconductor film such as polysilicon, which has an almost minimum reflectance at the exposure wavelength. A photoresist film corresponding to a desired pattern is formed on this polycrystalline semiconductor film using photolithography technology, and the polycrystalline semiconductor film and metal film are dry-etched using this photoresist film as a mask. This is what I did.

この発明において、金属膜上に形成する多結晶半導体膜
の厚さを、露光波長に対する反射率がほぼ極小となる厚
さに限定したのは、金属膜上に光を透過するような薄膜
を形成した場合、第5図に示すように反射率がlり厚の
変化に伴って周期的に極大又は極小を示すことによるも
のである。このような反射率の周期的変化は、薄膜中で
の定在波現象に起因するもので、ホトレジスト膜につい
てはすでに知られている。この発明では1反射率が極小
となるt+、tz、tz、taのような厚さ又はこれら
のいずれかに近似した厚さで金属膜上に多結晶半導体膜
を形成したことにより霧光波長に対して反射率の低い表
面を実現したものである。
In this invention, the thickness of the polycrystalline semiconductor film formed on the metal film is limited to a thickness at which the reflectance at the exposure wavelength is almost minimal.The reason for this is to form a thin film on the metal film that transmits light. In this case, as shown in FIG. 5, the reflectance periodically shows a maximum or minimum as the thickness changes. Such periodic changes in reflectance are caused by standing wave phenomena in thin films, and are already known for photoresist films. In this invention, by forming a polycrystalline semiconductor film on a metal film at a thickness such as t+, tz, tz, and ta where the reflectance is minimum, or a thickness close to any of these, it is possible to obtain a fog light wavelength. In contrast, it has a surface with low reflectance.

[作用] この発明の構成によれば、金属膜がAI又はA1合金等
の高反射率を有するものからなっていても、その上に上
記したような厚さで多結晶半導体膜を形成することによ
り反射率を該膜なしの場合(第5図で膜厚ゼロの場合)
に比べて約半分以下に低下させることができる。このた
め、多結晶半導体膜の上にホトレジストを被着した後露
光処理を行うと、ホトレジストの下層からの反射光が弱
いので、ホトレジストが不所望の部分で露光されること
がなくなり、正確なパターン転写が可能となる、換言す
れば、不均一な露光に基くホトレジストパターンの寸法
や形状のばらつきが抑制され、微細配線を形成するよう
な場合には、個々の配線の太りゃ細りを軽減することが
できる。
[Function] According to the structure of the present invention, even if the metal film is made of a material having a high reflectance such as AI or A1 alloy, a polycrystalline semiconductor film can be formed on the metal film with the above-mentioned thickness. The reflectance is calculated without the film (in the case of zero film thickness in Figure 5).
can be reduced to about half or less compared to For this reason, when exposure processing is performed after depositing a photoresist on a polycrystalline semiconductor film, the light reflected from the lower layer of the photoresist is weak, so the photoresist is not exposed in undesired areas, and an accurate pattern can be created. In other words, variations in the size and shape of the photoresist pattern due to non-uniform exposure can be suppressed, and when forming fine wiring, the thickening and thinning of individual wiring can be reduced. I can do it.

[実施例] 第1図乃至第4図は、この発明の一実施例による配線形
成工程を示すもので、各々の図番に対応する工程(1)
〜(4)を順次に説明する。
[Example] FIGS. 1 to 4 show a wiring forming process according to an example of the present invention, and the process (1) corresponding to each figure number is
- (4) will be explained in order.

(1)例えばシリコンからなる半導体基板10の表面に
シリコンオキサイド等の絶縁膜12を形成した後、この
絶縁膜12の上にAI又はA1合金(例えばAl−9i
 )からなる金属膜14を真空蒸着法、スパッタ法等の
任意の方法で形成する。金属膜14の上には、多結晶半
導体膜としてポリシリコン1li16をCVD (ケミ
カルφペーパー・デポジション)法等により被着する。
(1) After forming an insulating film 12 made of silicon oxide or the like on the surface of a semiconductor substrate 10 made of silicon, for example, the insulating film 12 is coated with AI or A1 alloy (e.g. Al-9i).
) is formed by any method such as vacuum evaporation or sputtering. On the metal film 14, polysilicon 1li16 is deposited as a polycrystalline semiconductor film by a CVD (chemical φ paper deposition) method or the like.

この場合、ポリシリコン膜16の厚さtは、露光波長を
436[nmlとし且つmlOまたはl、2・・・のよ
うな正の整数とすると、 t=8+48Xm±10[nml なる式に従って選定することができる。換言すれば、こ
の式を満足する厚さで反射率がほぼ極小となるものであ
る。
In this case, the thickness t of the polysilicon film 16 is selected according to the formula: t=8+48Xm±10[nml], where the exposure wavelength is 436[nml] and a positive integer such as mlO or l, 2... be able to. In other words, the reflectance becomes almost minimum at a thickness that satisfies this formula.

(2)次に5、ポリシリコン膜16の上に慣用の方法に
従ってホトレジストを被着した後、所望の配線パターン
を露光により転写し、さらに現像することによって該配
線パターンに対応したホトレジス)818を形成する。
(2) Next, 5, after depositing a photoresist on the polysilicon film 16 according to a conventional method, a desired wiring pattern is transferred by exposure and further developed to form a photoresist (818) corresponding to the wiring pattern. Form.

この場合、金属膜14には上記のような厚さでポリシリ
コン膜16を形成しておいたので、ホトレジスト露光の
際にホトレジストの下層からの光反射が抑制され、寸法
や形状のばらつきが少ないホトレジストパターンが得ら
れる。
In this case, since the polysilicon film 16 is formed on the metal film 14 with the above thickness, light reflection from the lower layer of the photoresist is suppressed during photoresist exposure, and variations in size and shape are reduced. A photoresist pattern is obtained.

(3)次に、ホトレジスト膜18をマスクとしてプラズ
マエツチング等のドライエツチングを実施することによ
り配線パターンに対応した金属膜14A及びポリシリコ
ン膜16Aを得る。この場合、ポリシリコン[18Aは
、殆どサイドエッチされず、金属Ifi14のためのエ
ツチングマスクとして作用する。従って、金属膜14A
としては、ホトレジスト膜18のパターン(配線パター
ン)に対する忠実度が極めて良好なものが得られる。
(3) Next, by performing dry etching such as plasma etching using the photoresist film 18 as a mask, a metal film 14A and a polysilicon film 16A corresponding to the wiring pattern are obtained. In this case, the polysilicon [18A is hardly side etched and acts as an etching mask for the metal Ifi 14. Therefore, the metal film 14A
Therefore, a photoresist film 18 with extremely good fidelity to the pattern (wiring pattern) can be obtained.

(4)この後、金属膜14A及びポリシリコン膜16A
をおおってCVD法等により絶縁膜20を形成する。こ
の絶縁膜20は、表面保護膜または居間絶縁膜となるも
のである。なお、ポリシリコン膜16Aは、絶縁膜20
の形成に先立って除去してもよいが、残しておくと、A
I又はAl−9i等におけるヒロック成長を抑えること
ができるので有益である。
(4) After this, the metal film 14A and the polysilicon film 16A
An insulating film 20 is formed by covering it by a CVD method or the like. This insulating film 20 serves as a surface protection film or a living room insulating film. Note that the polysilicon film 16A is similar to the insulating film 20.
may be removed prior to the formation of A, but if left,
This is advantageous because hillock growth in I or Al-9i, etc. can be suppressed.

[発明の効果] 以上のように、この発明によれば、金属膜上に多結晶半
導体膜を露光波長に対する反射率がほぼ極小となる厚さ
で形成した後、その上にホトリングラフィ技術により所
望パターンのホトレジスト膜を形成し、このホトレジス
ト膜をマスクとして多結晶半導体膜及び金属膜をドライ
エッチするようにしたので、次のような優れた作用効果
が得られる。
[Effects of the Invention] As described above, according to the present invention, after forming a polycrystalline semiconductor film on a metal film to a thickness that makes the reflectance at the exposure wavelength almost minimum, Since a photoresist film with a desired pattern is formed and the polycrystalline semiconductor film and metal film are dry-etched using this photoresist film as a mask, the following excellent effects can be obtained.

(1)露光処理の際にホトレジストの下層からの光反射
が抑制されるので、寸法や形状のばらつきが少ないホト
レジストパターンを得ることができ、このホトレジスト
パターンをマスクとしてドライエツチングを実施するの
で、LSIの配線等の微細な金属パターンにおいて局部
的な太りゃ細りが生ずるのを防止することができる。
(1) Since light reflection from the lower layer of the photoresist is suppressed during exposure processing, it is possible to obtain a photoresist pattern with less variation in size and shape. Since dry etching is performed using this photoresist pattern as a mask, LSI It is possible to prevent local thickening or thinning from occurring in fine metal patterns such as wiring.

(2)ドライエッチ処理の際に多結晶半導体膜には殆ど
サイドエッチが入らないので、高いエツチング精度が得
られる。すなわち、金属パターンには、従来の反射防止
用有機絶縁膜の場合に生じたようなサイドエッチに甚く
細りが生じない、従って、1  [ti−rn」以下の
配線幅を実現することも可能である。
(2) Since the polycrystalline semiconductor film is hardly side-etched during dry etching, high etching accuracy can be obtained. In other words, the metal pattern does not have the extremely thin side etch that occurs in the case of conventional anti-reflection organic insulating films, and therefore it is possible to realize a wiring width of 1 [ti-rn] or less. It is.

(3)従来の反射防止用*機絶縁膜を使用するには、塗
布、ベーキング、ホトレジストとの同時現像、エツチン
グ後の除去等の工程が必要であるが、この発明の方法は
金属膜上に多結晶半導体膜を被着するだけでよく、エツ
チング後も必ずしも除去する必要はなく、工程的に非常
に簡単である。
(3) Using conventional anti-reflection *mechanical insulating films requires processes such as coating, baking, simultaneous development with photoresist, and removal after etching, but the method of this invention It is only necessary to deposit a polycrystalline semiconductor film, and there is no need to necessarily remove it after etching, making the process extremely simple.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は、この発明の一実施例による配線形
成工程を示す基板断面図、 第5図は、金属膜上に形成した薄膜について膜厚と反射
率との関係を示すグラフである。 10・・・半導体基板、12.20・・・絶縁膜、14
・・・金属膜、16・・・ポリシリコン膜(多結晶半導
体膜)、18・・・ホトレジスト膜。
1 to 4 are cross-sectional views of a substrate showing a wiring forming process according to an embodiment of the present invention, and FIG. 5 is a graph showing the relationship between film thickness and reflectance for a thin film formed on a metal film. be. 10... Semiconductor substrate, 12.20... Insulating film, 14
. . . Metal film, 16 . . . Polysilicon film (polycrystalline semiconductor film), 18 . . . Photoresist film.

Claims (1)

【特許請求の範囲】 (a)基板上に金属膜を形成する工程と、 (b)前記金属膜をおおって多結晶半導体膜を露光波長
に対する反射率がほぼ極小となる厚さで形成する工程と
、 (c)前記多結晶半導体膜上にホトリソグラフィ技術に
よって所望のパターンに対応するホトレジスト膜を形成
する工程と、 (d)前記ホトレジスト膜をマスクとして前記多結晶半
導体膜及び前記金属膜をドライエッチする工程と を含む金属パターン形成法。
[Claims] (a) A step of forming a metal film on a substrate; (b) A step of forming a polycrystalline semiconductor film covering the metal film to a thickness such that the reflectance to the exposure wavelength is almost minimum. (c) forming a photoresist film corresponding to a desired pattern on the polycrystalline semiconductor film by photolithography; (d) drying the polycrystalline semiconductor film and the metal film using the photoresist film as a mask; A metal pattern forming method comprising the step of etching.
JP60107937A 1985-05-20 1985-05-20 Metal pattern forming method Expired - Lifetime JP2544100B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60107937A JP2544100B2 (en) 1985-05-20 1985-05-20 Metal pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60107937A JP2544100B2 (en) 1985-05-20 1985-05-20 Metal pattern forming method

Publications (2)

Publication Number Publication Date
JPS61265835A true JPS61265835A (en) 1986-11-25
JP2544100B2 JP2544100B2 (en) 1996-10-16

Family

ID=14471828

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812328A (en) * 1981-07-16 1983-01-24 Fujitsu Ltd Manufacturing method of semiconductor device
JPS6055642A (en) * 1983-08-12 1985-03-30 コミツサリア タ レネルギ− アトミ−ク Method of installing connecting wire of integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812328A (en) * 1981-07-16 1983-01-24 Fujitsu Ltd Manufacturing method of semiconductor device
JPS6055642A (en) * 1983-08-12 1985-03-30 コミツサリア タ レネルギ− アトミ−ク Method of installing connecting wire of integrated circuit

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