JPS61265660A - Execution mode switching control system in multiprocessor system - Google Patents

Abstract

PURPOSE:To avoid troubles due to a difference between execution modes in each processor by providing a memory where flag information showing the presence or absence of the package of a subprocessor and a temporary memory area in which information on system is saved and stored is allocated and stored. CONSTITUTION:When a device is turned on, an IPL and a test program, both of which are stored in a ROM 6, are activated, and the package state of the subprocessor 2 is checked. When it is packaged, a register MSW showing the state of a processor in a main processor 1 is set. After a system is initialized, an operation system OS is loaded in a system RAM 7 from a floppy disk 8. When the necessity of switching the operation in a virtual address mode occurs, the OS activates a superviser to check an MSW in the processor 1. When a subprocessor flag is set, the operation is switched in a virtual address mode in accordance with the instruction of the processor 2. Afterward, the processor 1 initializes for execution in a virtual address mode, and is switched in a virtual address mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an execution mode switching control method in a multiprocessor system.

[Technical background of the invention and its problems]

Due to advances in semiconductor technology, microprocessors and LSI
has become available at low cost.

By arbitrarily combining these microprocessors and LSIs, it is possible to construct a computer system that exhibits optimal performance for a specific problem. Looking at the Microphone 4 processor itself, the instruction set and architecture of the independent processor can be expanded by combining two types of processors (of processors) called independent processors and coprocessors to form a multiprocessor configuration.

As an example of the above, the main processes t, H that manage the system
- Let's assume a combination of processors such as a numerical processing processor. By adding this numerical arithmetic processor to the system, numerical arithmetic operations can be greatly speeded up. Each of the above processors has a virtual address mode and a real address mode as execution address modes, and each processor can be switched from the real address mode to the virtual address mode by software.

However, if the address modes differ between these processors, the program will not operate normally. Further, since the sub-processor does not have sufficient information for the main processor to recognize the current mode, it is difficult to switch the sub-processor from the main processor to a subordinate state. Therefore, the ff processor can only operate in one of the modes.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is a multiprocessor system that avoids the inconvenience caused by differences in execution modes among individual processors and improves performance by synchronizing address mode switching between each processor. The purpose of this paper is to provide an execution mode switching control method in a processor system.

[Summary of the invention]

The present invention relates to synchronization of execution modes between processors when a multigrossing system is constructed using processors having virtual addressing and real addressing in their execution modes. As a result, we have achieved synchronization of the addressing modes of the main processor and subprocessor. For this reason, we need a temporary storage device unique to the superpipe that temporarily saves system status information, a hardware reset switch that switches to real address mode and does not affect the temporary storage device mentioned above, and the presence or absence of a subprocessor implementation. It has flags to display and a program that outlines the steps below. When it becomes necessary to switch to the real address mode, the A4 saves some system information (current system status information) to its own temporary storage area, drives the switch mentioned above, and controls the main processor. A hardware reset is applied to only the and ff processors, and the main processor recognizes the restart for mode switching by checking the temporary storage area mentioned above, skips system initialization, performs recovery processing, and resumes operation. It was configured to return the state to the state at the time the switch occurred.

This makes it possible to avoid inconveniences caused by differences in address modes between processors, and improve performance.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a main processor (CPU), 2 is a sub-processor (Co-CPU) such as a numerical calculation processor, and a small-scale multiprocessor system can be constructed using these processors.

3 is a switch for resetting only the processors 1 and 2 mentioned above. In the embodiment of the present invention, Dart (Reset Dry/4) is exemplified. 4 is a display storage device (VRAM) in which display data is stored, 5 is a display control device (CRTC), and each is a system management program. The memory structure is shown in FIG. 2. That is, IPL & initial test, basic human output driver, and super pipe programs are stored. IPL & initial test is IPL
It is a program for performing hardware operation tests and hardware initialization, and the basic human output driver is a program for driving input/output covered hardware resources, that is, a floppy disk drive 8, a keyboard 9, and a display device 10. This is a program that manages the entire resource, such as switching the cylinder gram group and suit arm Paideha execution mode.

L is the main memory, so-called system RAM;
The storage structure is shown in the figure. As you can see from the figure, the operating system and 21 tasks being executed are stored.

Further, in a part particularly related to the present invention, a temporary storage area for system saving is allocated as a register area. FIG. 4 shows a system management mechanism based on the program group described above. 8 is an auxiliary storage device such as a floppy disk in which the above-mentioned operating system and user programs are stored; 9 is a keyboard; and 10 is a display device.

FIG. 5 is a 70-chart showing the operation of the embodiment of the present invention, and only the mode switching portion is extracted and shown. In the figure,
Solid lines indicate movement in real address mode, and wavy lines indicate movement in virtual address mode.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail with reference to the flowchart shown in FIG. First, when the power is turned on, the IPL &
The test program starts. At this time, the implementation state of one sub-processor 2 is checked, and if it is installed, a register (MSW) in the main processor 1 indicating the processor state is set. Next, when the system initialization is completed, the system A RAM 7i is transferred from the floppy disk 8.
C-k A rating system (O8) t-loading. Next, this O8 is activated and waits for the user's instructions. At this time, if it becomes necessary to switch to virtual address mode, O8 activates the super node. The above-mentioned condition (1) in the main processor 1 is checked, and if the sub-processor flag is set, the sub-processor 2 switches to the virtual address mode by an instruction. Thereafter, the main processor 1 performs initialization for virtual address mode execution and switches itself to virtual address mode. Thereafter, the process returns to O8, performs tasking processing for multitasking, and waits for a second task. In this state, the user task runs on subprocessor 2 in the same mode as main processor 1.
access is possible.

Next time a mode switch to real address mode occurs,
The O8 starts up the Sue/4' pipe again, saves part of the system (current system state) to the temporary storage area unique to the Sue i4 pipe, drives the reset switch or Dart 3, and returns the main processor? d)-Docuair reset is applied only to sub-processor 1 and sub-processor 2. Main processor 1
starts re-execution in the same way as when the power is turned on, but immediately checks the system save area and recognizes the restart for mode switching.

Here, if a mode switching operation is detected, the system initialization operation is skipped, and system recovery processing is performed to return the operating state to the state at the time of switching occurrence.

In this way, a user program written for real address mode can be executed.

Note that the processor used in the embodiment of the present invention can only be switched from virtual address mode to real address mode by hardware reset. In this way, the addressing modes of the main processor and the sub-processor can be synchronized by switching between the two addressing modes through the respective devices.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) In a multiprocessor system, problems caused by differences in addressing modes between processors can be avoided.

(2) Addressing modes can be switched quickly.

(3) Does not affect operations between tasks when switching addressing.

(4) Since mode switching can be performed quickly, it becomes possible for a user program for real addressing and a user program for virtual addressing to coexist.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the storage structure of the ROM shown in FIG. 1, and FIG. 3 is a diagram showing the storage structure of the system RAM shown in FIG. 1. Figure, 4th
The figure is a diagram conceptually showing the system management mechanism according to the present invention, and FIG. 5 is a flowchart showing the operation of the embodiment of the present invention. 1...Main processor, 2...Sub processor, 3.
...Reset driver, 7...ROM, 7...system RAM. Applicant's Representative Patent Attorney Takehiko Suzue FS1 Figure iIz Figure 13 Figure 4 Figure 5

Claims (1)

[Claims] The system consists of a main processor and sub-processors that have virtual addressing and real addressing in their execution modes, and a temporary storage area in which some system information is saved and stored, and flag information indicating whether or not the above-mentioned sub-processors are installed are allocated. a switching means for hardware reset that does not affect the temporary storage area for switching the execution mode to real addressing; evacuating current system state information and driving the switching means;
means for applying a hardware reset to the main processor and sub-processor, the main processor recognizes restart for mode switching by checking the temporary storage area, and performs return processing without initializing the system. An execution mode switching control method in a multiprocessor system, characterized in that the execution mode switching control method in a multiprocessor system is characterized in that the operating state is returned to the state at the time when the switching occurred.