JPS61264833A - Data transfer control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In a multiprocessor system connected in a ring, instead of specifying the receiving node (processor) of a transfer packet by an address, a bit pattern field indicating the destination node is included in the transfer packet. By providing a bit pattern and specifying a receiving node, any combination of destination nodes can be specified, and a sending node is specified by a bit pattern.

The present invention discloses a data transfer control method that enables efficient data transfer by determining this bit pattern and detecting a transmission end packet.

[Industrial application field]

The present invention is a multiprocessor system connected in a ring, in which processors in each node are connected in a ring.

This relates to a data transfer control method that determines whether or not a packet flowing through a ring is addressed to the node itself, and then imports the data.

[Conventional technology]

When a transfer packet is placed on a ring network and each processor sends and receives data, it is necessary to specify which node to send the packet to.

According to the conventional method, a sending node sets a destination address in a transfer packet to specify a receiving destination. The destination address is arbitrarily determined for each node in advance. In addition, when broadcasting globally to all nodes, for example, specify a special global address or set a global flag in the packet.
It was supposed to be specified.

[Problem that the invention seeks to solve]

According to the above conventional method, for multiple nodes.

When sending packets with the same data content, it is necessary to use packets with multiple destination address fields or to route multiple packets with different destination fields, resulting in poor data transfer efficiency.

[Means for solving problems]

The present invention aims to solve the above-mentioned problems and provides a means by which data can be transferred to any node by sending one packet, without distinguishing between global and individual nodes.

FIG. 1 shows a basic configuration diagram of the present invention.

In the figure, 10 is a ring network, 11 is a packet that is a unit of transmitted and received data, 12 is a transmitting node that is a processor that transmits the packet, 13 is a destination node bit pattern setting unit, 14 is a transmission end packet detector, and 15 is a packet 16 represents a bit pattern determination unit addressed to the own node, and 17 represents a bit inversion unit addressed to the own node.

The packet 11 includes a flag pattern F indicating the beginning of the packet, a bit pattern field DBP indicating the destination node of transmission, a source address SA, actual transfer data DATA, and a check pattern CHK for error checking. It consists of a trailer flag T field indicating the end of the packet. For example, DBP is 256 bits, SA is 8 bits, DATA is 1024 bits,
CHK is 20 bits.

Each bit of field DBP (A, B, C, . . .

X, . . . ) are each previously associated with one of the receiving nodes 15. Therefore, up to 256 processors can be connected as nodes.

The transmitter node 12 is a supervisor node that transmits data to each node on the ring and monitors the ring. When the destination node bit pattern setting unit 13 transmits the packet 11.

Set the corresponding bit position of the destination node in field DBP to 0'', and set the others to 1''.

Send packet 11 to the ring.

In each receiving node 15, if the node is capable of receiving packets, the self-node bit pattern determination unit 16 checks the field DBP and determines whether the packet 11 is addressed to the self-node. The bit corresponding to the own node is “
If it is "0", the data is taken in, and the bit inverter 17 for the own node rewrites the bit to "1".

Return to loop.

The transmission end packet detection unit 14 of the sending node 12 constantly monitors the packet 11 returned from the ring, and recognizes a packet in which all bits of the field DBP are "1" as a transmission end packet.

Remove from loop. This results in one packet 11
It becomes possible to send packets to multiple nodes, confirm that all destination nodes have received them, and remove unnecessary packets.

[Effect]

FIG. 2 is a diagram for explaining the present invention in detail. Second
In the figure, 1, for example, the transmitting node 12.

Suppose that packet 11 is transmitted to node 15A and node 15X. When the node 15A receives the packet 11,
The node 15X inverts the bit of its own node in the field DBP, and similarly, when the node 15X receives the packet 11, it inverts the bit of its own node. Therefore, sending node 12
In this case, the transmission end packet can be detected by field DBP.

For example, if node 15A is busy and packet 1
When 1 cannot be received, set “O” to field DBP.
Since the remaining bits remain, packet 11 circulates around the ring without being removed from the ring. That is, the field DBP is used to specify the destination node, and is also used to indicate a reception response (accept) from the receiving node.

This results in efficient data transfer.

〔Example〕

FIG. 3 shows an example of a packet transmitting/receiving circuit of a supervisor node serving as a transmitting node, and FIG. 4 shows an example of a packet transmitting/receiving circuit of a receiving node.

In the circuit shown in FIG. 3, 21 is an input terminal for the serial signal from the ring, 22 is a 256-bit shift register,
23 is a flag pattern F detector.

24 is a trailer flag T detector; 25 and 26 are delay units; 27 is a comparison value register that holds a comparison value for detecting the end of transmission; 28 is a comparator; 29 is a flip-flop;
0 is an AND circuit, 31 is a parallel load shift register, 32 and 33 are AND circuits, 34 is an OR circuit,
35 is first in, first out (FIF○)
buffer, 36 is an output terminal to the ring. Also,
CLK represents a clock signal.

The data input to the input terminal 21 is transferred to the shift register 2.
2 and is shifted in synchronization with the clock signal CLK. On the other hand, also to the detector 23.

Input data is sent and packets are monitored.

When the detector 23 detects the beginning of the packet,
The comparator 28 is enabled by the delay device 25 after a delay corresponding to the length of the field DBP. At this time, the contents of the field DBP are set in the shift register 22.

The comparison value register 27 contains a value for detecting the end of transmission.

That is, all "l" are stored, and the comparator 28 is
This value is compared with the contents of the shift register 22. If they are equal, flip-flop 29 is set. When the flip-flop 29 is in the set state, it instructs that a new packet should be transmitted, and when it is in the reset state, it instructs to transfer the input data as is.

The detector 24 detects the trailer flag T.

When the trailer flag T is detected, after a predetermined delay,
Reset the flip-flop 29.

Transfer data of a new packet is loaded into the shift register 31 by a communication control unit (not shown) of the processor, and when the flip-flop 29 is set, the AND circuit 33. The signal is output to the ring via the OR circuit 34 and buffer 35.

In the packet transmitting/receiving circuit of the receiving node shown in FIG. 4, 41 is an input terminal from the ring, 42 is a 256-bit shift register, 43 is a flag pattern F detector, 4
4 is a trailer flag T detector, 45 is a delay device, 47 is an ID register that holds a bit pattern indicating the node, 48 is a comparator, 49 and 50 are flip-flops, 51 to 53 are AND circuits, and 54 is a bit 55 is a shift register whose initial value is set to "1" in the bit position indicating the own node in the pattern.

The child circuit 56 is an output terminal to the ring.

The input data to the input terminal 41 is sent to the shift register 42 in synchronization with the clock signal CLK.

Shifted. On the other hand, input data is also sent to the detector 43, and packets are monitored. When the detector 43 detects the head of the packet.

Delay unit 45 enables comparator 48 after a delay equal to the length of field DBP. At this time, the contents of the field DBP are set in the shift register 42.

The ID register 47 stores bit pattern information of the node, and the comparator 48 checks whether the contents of the shift register 42 corresponding to this bit position are "0". If it is "0", it means that the packet is addressed to the own node. At this time, if the node is in a receiving state, the output of the flip-flop 49 is "1".
Therefore, the flip-flop 50 is set via the AND circuit 51.

By setting the flip-flop 50 to the set state, received data is read through the AND circuit 52. Furthermore, by the output of the shift register 54, the bit assigned to this node in the destination node bit pattern sent to the shift register 42 is inverted to "1" and sent out from the output terminal 56.

The detector 44 detects the trailer flag T.

When the trailer flag T is detected, the flip-flop 50
Reset. This completes the reception of the packet.

Now, consider that the sending node 12, which is a supervisor node, sends a series of data packets with a total number of N packets to all nodes. The number of packets that can be sent onto the ring from the supervisor node at one time is 9, which depends on the size of the buffer 35 shown in FIG. 3, for example. The number of packets that can be sent out on this ring at one time is M (MAN).
), the first M packets out of N packets are sent out.

The supervisor node is based on the circuit shown in FIG.

Packets returned from the ring are constantly monitored, and if there is a packet whose field DBP is all 1'', that packet is removed from the loop and the packet to be sent to the 9th time is sent to the ring.

Until the transmission of at least (NM) packets from the transmitting node is completed, M packets circulate on the ring, and among them, the packets captured by all the receiving nodes are removed in order. .

New packets are sent out one after another.

As described above, it is possible to divide a series of data into small-capacity packets, reduce the buffer size for data acquisition in each node, and make it easier to receive the packets. Furthermore, by sending a plurality of packets to the ring, it is possible to provide flexibility in the data acquisition speed of each node. That is, even if one receiving node is busy and cannot receive or accept packets, other receiving nodes can receive or accept packets. In addition, the supervisor node sets time information in the packet, etc., so that the supervisor node can
It is also possible to perform time monitoring.

In the circuit shown in FIG. 4, even if there is an error in the data, the destination node bit pattern field is updated, so the packet is received. Therefore, for example, a receive buffer for one packet is provided at the receiving node and the data is taken in.

If the destination node bit pattern field is updated after error checking, minor errors can be prevented from occurring.

In the above embodiment, an example of a system with one transmitting node was explained, but of course, even if there are multiple transmitting nodes,
Similarly, packet transfer is possible.

〔Effect of the invention〕

As explained above, according to the present invention, data transfer to any node can be realized using the same one packet, and data transfer efficiency is improved. Also, when sending out to multiple nodes.

Even if there is a node that cannot be received in - times of transfer, the packet will loop, so no special retransmission means is required.

By sending multiple packets in series, each node can independently capture as much data as it can capture, depending on its processing speed, so even if one receiving node cannot receive data, other receiving nodes will Nodes are not affected by it.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, FIG. 3 is an example of a packet transmitting/receiving circuit of a supervisor node, and FIG. 4 is an example of a packet transmitting/receiving circuit of a receiving node. In the figure, 11 is a packet, 12 is a sending node, 13 is a destination node bit pattern setting unit, 14 is a transmission end packet detection unit, 15 is a receiving node, 16 is a bit pattern determination unit addressed to own node, and 17 is a bit addressed to own node Inversion part, DBP
represents the field of the destination node bit pattern. Patent applicant Fujitsu Ltd. Representative Patent Attorney Hiroshi Mori 1) (1 other person)

Claims (1)

[Claims] In a multiprocessor system connected in a ring, a destination node is specified in a transfer packet (11) transmitted and received by each node by a bit pattern in which at least one bit corresponds to one receiving node. The transmitting node (12) sets a bit pattern indicating the destination node in the field (DBP), and determines the field (DBP) with the means (13) for transmitting the packet. The receiving node (15) determines whether the packet is addressed to its own node or not based on the bit pattern set in the field (DBP). The device is characterized by comprising means (16) and means (17) for inverting the bit corresponding to the own node in the field (DBP) and forwarding the received packet when the own node takes in the packet. Data transfer control method.