JPS61264830A - Phase synchronized bus method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Summary] Digital integrated service network (ISDN: Integ)
ratedService Digital Network
During automatic phase adjustment of the data transmission timing between the subscriber premises network terminal equipment (NT) and the subscriber terminal equipment (TE) in the NT side, the NT side reads the data including the monitor bit transmitted from the TE side, and When it becomes possible to read the data, a timing clock with an inverted phase with respect to the data is sent out, and on the TE side, the data is transmitted without any time delay.

[Industrial application field]

The present invention relates to a phase synchronized bus system in a digital integrated service network.

15DN is a network that integrates and provides a wide variety of services such as telephone and facsimile communication services in one digital communication network. In such an I5DN, the user/network interface is important as it has a great influence on its spread, and for this reason, the CCITT also recommends one interface as part of the ■ series recommendation group. The feature of this I interface is that it has four lines and is connected to a bus. That is, a network termination device connected to a switching network and a plurality of terminal devices are connected by an up and down bus. In such an interface, a maximum bus length corresponding to the wiring type is set.

[Conventional technology]

A phase-synchronized bus system has been proposed as one means to alleviate this bus length restriction. This phase-synchronized bus system adjusts the frame transmission phase of each terminal device so that the round trip delay from the network terminating device to all terminal devices is equal. Adjustment of the frame sending phase is automatically performed by sending out monitor bits and detecting and collating monitor echo bits that are sent back at the network termination device. After adjusting the frame sending phase, the network terminal device can read data from each terminal device at a fixed timing.

FIG. 5 shows an example of the configuration of one station in the phase synchronized bus system. In FIG. 5, a plurality of terminal devices 1゜2...n are connected to a network termination device 3 via a bus 5, and a subscriber line 6
It is connected to the digital exchange 4 via. FIGS. 6(a) and 6(b) are explanatory diagrams of the frame structure in the phase synchronized bus system. The transmission from the TE and terminal equipment to the network termination equipment is shown as <TE→NT as shown in FIG. 6(b), and one frame consists of 48 bits in 250 μs. Also, F is a frame bit inserted in each frame, L is a DC balance bit, D is a D channel pit, and E
is the D echo channel bit, Fa is the auxiliary frame bit, N is the inverted auxiliary frame bit, B1. B
2 is B channel 1 and 20 bits, A is startup bit, S
l and S2 are spare bits. Frame bit F is
A 2-bit offset is provided between the frame from the network termination device to the terminal device and the frame from the terminal device to the network termination device. Also, the arrow indicates D channel bit D
and the D echo channel bit E are shown. Also, M is monitor bit, m is monitor echo bit,
S is a spare bit, and G is a guard bit.

In FIG. 5, the number of an arbitrary terminal device is i, the delay time on the bus is T P s , and the delay time between transmission and reception is T
In the case of Pi, the pattern generator 21 phase detection circuit 2
3. The delay circuit 22 automatically adjusts the signal transmission timing.

The detailed circuit of the terminal device TE shown in FIG. 5 is shown in FIG. 7(a).
Furthermore, a partial circuit of the network termination device NT is shown in FIG. 7(b). A flowchart showing these operations is shown in FIG.

In FIG. 7(a), the terminal device includes a pattern generator 21, a timer 22, a phase detection adjustment circuit 23, a transmitter 24, a receiver 25, a τ time delay circuit 26, and a selector 27. The phase detection adjustment circuit 23 includes a multiplexer 231, a shift register 232 to which a clock signal HS-CLK is applied, a selector 233, and a comparison circuit 23.
4, counter 235, counter 236, multiplexer 2
37, a frame synchronization circuit 238, and an AND gate 239 are connected as shown.

FIG. 7(b) shows the data DATA' in the network terminal device NT.
A circuit 31 consisting of D-type flip-flops 311' and 312' connected in series for reproduction and monitor bit M detection.
′ is shown. The received data DATA is the flip-flop 31
1' is applied to the D input terminal. A clock signal CLK is applied to the clock terminal of the first flip-flop 311. Therefore, D of flip-flop 312'
Received data DATA delayed by one clock is input to the input terminal. A monitor bit detection clock signal MCK is applied to the clock terminal of the second flip-flop 312'.

The operation of the circuit shown in FIGS. 7(a) and 7(b') will be described with reference to the flow chart of FIG. 8 which shows the operation of the circuit shown in FIG. 7(a).

When the terminal device TE starts up, it detects the input of a frame synchronization signal (FIG. 8, step 5OOI).

In other words, when data is sent from the network terminal device NT,
The receiving unit 25 receives the data, and the frame synchronization circuit 238 detects the frame bit F from the received data. When frame bit F is detected, the index i that determines the delay in the sending timing of monitor bit M, that is, the phase synchronization timing, is set to i = 1 as an initial value (S OO
2). The phase adjustment work begins below.

Please set the index i above in the selector 233.
OO3), If there is a collision with another terminal device when a call is made via the sender 24, for example, when bus=0, the terminal waits (SOO4). When the state becomes ready for transmission, the following phase adjustment work begins (S005 to 5olo). That is, the counter 235 is set to an initial value of j=1 (5OO5),
Using the random data from the pattern generator 21 as the monitor bit M, the data DAT shown in FIG. 9(a) is
A is sent to the network terminal device NT via the AND gate 239, multiplexer 231, shift register 232, selector 233 and transmitter 24 (80.06). This transmission data is received by the network terminal device NT, the data is read, a monitor bit M is detected, and a monitor echo bit m is returned. The TE side receives the monitor echo bit m via the receiving section 25, and further sends it to the multiplexer 23.
1 to the comparator 234, and the comparator 234 detects whether or not the monitor echo bit m for the transmitted monitor bit M has been received (S007). If they do not match, the repetition index i is up to 25.
Repeat the above operation until reaching . Therefore, the index i is increased by 1 < (SO21,5O2
4,5O25). In this case, the sending timing of the monitor pins l-M is sequentially shifted. The reason why M=1 is set in step 5O22 is to bring the bus to the ground level so that other terminal devices can use the bus.

On the other hand, if the monitor bit M and the monitor echo bit m match, in order to determine the timing at which a match can be reliably achieved, trials are performed multiple times, 16 times in this example, to see if they match (SOO8° 5OO9). If 16
If it matches repeatedly, the index i at that time
The monitor bit M is transmitted at the phase synchronization timing based on the phase shift defined by . The monitor bit M=1 (5olo) allows other terminal devices to use the bus, and the automatic phase adjustment operation is completed. 16
Monitor bit M and monitor echo bit M
If they do not match, the index i is increased, that is, the phase shift is performed in the same manner as above. If the index i reaches 25, it means that phase synchronization could not be achieved in this case, so the monitor bit M = 1 (S
O22) Allow other terminal devices to use the bus and turn on the timer 22.5O23) Prepare for the next task.

That is, when the terminal device TE transmits data including the monitor bit M to the network termination device NT as shown in FIG. 6(b), the NT reads the monitor bit M as shown in FIG. 6(a). When this happens, the monitor echo bit m is returned. The network terminal device NT is designed to be able to read data from the farthest terminal device in a fixed phase. Therefore, each terminal device determines the timing at which the monitor echo bit m can be received with respect to the transmission of the monitor bit M. In other words, the monitor bit M is transmitted at the same timing, and if the monitor echo bit m is not received, the transmit timing of the monitor bit M is sequentially shifted, and phase synchronization is achieved at the timing when the monitor echo bit m can be stably received. .

On the network terminating device NT side, since the pulse phases from all the terminal devices TE match, it is sufficient to read data with a fixed phase. Therefore, the NT side synchronizes the received data using a clock signal of the same rate. The monitor bit M is detected by the circuit shown in FIG. 7(b) and a monitor echo bit m is generated to be sent back.

[Problem that the invention seeks to solve]

In the circuit shown in FIG. 7(b), when detecting the monitor signal M from the received data DATA, a shifter, etc. caused by a difference between the clock pulses on the network termination equipment NT side and the clock pulses on the terminal equipment TE is taken into account. For example, considering that the data DATA, which should originally be received at the timing shown in FIG. 9(a), is received with a time delay as shown in FIG. 9'(d), clock signal C
The signal hit once by K is monitored again by the monitor clock signal MCK.
(Figure 9(C))
I am trying to extract.

For this reason, on the TE side, during transmission, the monitor bit M is sent out with a delay of time τ in the delay circuit 26 so that the monitor bit M falls in the middle of the clock signal. That is, on the TE side, as shown in FIG. 7(a),
A delay circuit 26 is provided to delay the process by a time τ as shown in step 5011 of the flowchart shown in FIG.

However, such a delay on the TE side partially occupies or embeds the guard bit G provided before the monitor bit M. For example, when transmitting data at 192kHz, 1
The time for the bit is 5.2 m5ec, and the time for the guard bit G2 is 10.4 m5ec, but if the delay is delayed by half a bit τ time, the time corresponding to the guard bit G2 is actually 7 or 8 m5ec. It becomes m5ec.

The time of the guard bit G defines the distance between the NT and the farthest TE, so the fact that the guard time is reduced by the delay time as described above means that, for example, when the distance from the NT to the farthest TE is A problem has arisen in that although it is originally possible to travel up to 1 km, it is actually only possible to travel up to 750 m.

[Means and effects for solving the problem] In view of the above problems, the present invention provides a network termination device connected to a digital exchange via a subscriber line, and a network termination device connected to the network termination device via a bus. It has multiple terminal devices connected,
In the phase synchronized bus system, the phase difference between the signals that occurs depending on the distance between each of the plurality of terminal devices and the network terminating device can be automatically adjusted for each of the plurality of terminal devices. The network terminating device receives data including a predetermined bit sent from one of the terminal devices, reads out the predetermined bit of the received data using a single clock signal obtained by inverting the clock signal, and outputs the data, and outputs the predetermined bit of the received data to the terminal device. A phase synchronized bus system is provided, which is characterized in that data including predetermined bits is transmitted without delay.

〔Example〕

Embodiments of the invention will be described below with reference to the accompanying drawings.

FIG. 1(a) shows a circuit diagram of a terminal device as an embodiment of the present invention. The terminal device includes a pattern generator 21
, a timer 22, a phase detection adjustment circuit 23, a transmitter 24, and a receiver 25.

The phase detection adjustment circuit 23 includes a multiplexer 231 and a shift register 23 to which a clock signal H3-CLK is applied.
2, selector 233, comparison circuit 234, counter 235
, a counter 236, a multiplexer 237, a frame synchronization circuit 238, and an AND gate 239 are connected as shown. However, the τ time delay circuit 26 and selector 27 shown in FIG. 7(a) are not provided.

FIG. 1(b) shows a network termination device N as an embodiment of the present invention.
A circuit 31 for reproducing data DATA' in T and detecting monitor bit M is shown.

The circuit 31' in FIG. 7(b) has D-type flip-flops 311' and 312' connected in series; however, in this embodiment, the D-type flip-flops 311, 31
2 are provided in parallel.

The received data DATA is connected to both flip-flops 311°31
It is applied to the D input terminal of No.2. A clock signal CLK'' similar to that applied to the shift register 232 in FIG. 1(b) is applied to the clock terminal of the first flip-flop 311. A monitor bit detection clock signal MCK is applied to the clock signal MCK.

The operation of the circuit shown in FIGS. 1(a) and 1(b) will be described with reference to the flowchart of FIG. 2 and the timing chart of FIG. 3, which illustrate the operation of the circuit shown in FIG. 1(a).

When the terminal device TE starts up, it detects the input of a frame synchronization signal (FIG. 7, step 5OOI).

That is, when data is sent from the network terminal device NT as shown in FIG. 3(a), the receiving unit 25 receives the data (FIG. 3(c)), and the frame synchronization circuit 238 detects the frame bit F from the received data. do. Frame bit F
When detected, the index i that determines the delay in sending out the monitor via M, that is, the phase synchronization timing, is set to i=1 as an initial value (SOo, 2). The phase adjustment work begins below. The above operation is similar to the conventional case.

Set the above index i to the selector 233.5O
O3), If there is a collision with another terminal device when a call is made via the sender 24, for example, when bus=0, the terminal waits (SOo4). When the transmission becomes possible, the phase adjustment work described below begins (SOO5-5olo). In other words, the counter 235 is set to an initial value of j=1 and 5OO5.
), the random data from the pattern generator 21 is used as the monitor bit, and the data in the form of FIG. 3(d) is
It is sent to the network terminal device NT via the ND gate 239, multiplexer 231, shift register 232, selector 233 and transmitter 24 (S006). This transmission data is received by the network termination device NT, and the data DATAT is read by the circuit 31 in FIG.
is folded back. The TE side receives the monitor echo bit m via the receiving unit 25, and further applies it to the comparator 234 via the multiplexer 237, and applies the transmitted monitor bit M
The comparator 234 detects whether or not the monitor echo bit m has been received (S007). If they do not match, the above operation is repeated until the repetition index i reaches a maximum of 25. Therefore, the index i is increased by 1 < (SO21, 5O24
, 5O25). In this case, the sending timing of the monitor bits M is sequentially shifted as shown by the broken line in FIG. 3(d). The reason why M=1 is set in step 5O22 is to bring the bus to the ground level so that other terminal devices can use the bus.

On the other hand, if the monitor bit M and the monitor echo bit m match, in order to determine the timing at which a match can be reliably achieved, it is attempted multiple times, 16 times in this example, to see if they match (3008° 5009). If 1
If they match after repeating six times, the monitor bit M is sent out at the phase synchronization timing based on the phase shift defined by the index i at that time. The monitor bit M is set to 1 (3010), other terminal devices can use the bus, and the automatic phase adjustment operation ends.

If the monitor bit M and the monitor echo bit m do not match even after repeating the process 16 times, the index i is increased, that is, the phase shift timing is shifted, as described above. If the index i reaches 25, it means that reliable phase synchronization has not been achieved, so the monitor bit M
= 1 (S022) to enable other terminal devices to use the bus, turn on the timer 22 (5O23), and prepare for the next operation.

Regarding the above operation, the circuit 31 in the NT shown in FIG. 1(b) directly monitors the received data DATA (FIG. 4(a)) using the monitor clock signal MCK (FIG. 4(C)). Read bit M (FIG. 4(d)). That is, when the monitor bit M of the received data DATA becomes readable using the monitor clock signal MCK, the clock signal CLK (FIG. 4(b)) becomes readable at the center position of the data DATA. Therefore, unlike the delay circuit 26 in the terminal device described above, there is no need to perform such a delay on the terminal device TE side of this embodiment.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to delay the transmission timing of the monitor bit M on the terminal device side, and guard pit time is secured, so the distance from the network termination device to the connectable terminal device is eliminated. This has the effect of increasing the amount of

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a device as an embodiment of the present invention, and FIG. 1(a) shows a circuit inside a terminal device, and FIG.
Figure (b) shows a partial processing circuit within the network termination equipment, Figure 2 is an operation flowchart of the equipment shown in Figure 1 (a), Figure 3 is a timing chart of the equipment shown in Figure 1, and Figure 4 is Figure 1 (b) is a timing chart of the circuit; Figure 5 is a configuration diagram of the l5DN; Figures 6 (a) and (b) are diagrams illustrating the form of signal matching; Figure 7 is a conventional device circuit diagram. 7(a) shows a circuit in the terminal device, FIG. 7(b) shows a partial processing circuit in the network termination device, and FIG. 8 shows the circuit in the terminal device (
, a) Timing chart of the device; FIG. 9 is a timing chart of the device shown in FIG. 7. (Explanation of symbols) 1, 2...Terminal device, 21...Pattern generator, 22...Timer, 23...Phase detection circuit,
231... Multiplexer, 232... Shift register, 233... Selector, 234... Comparison circuit,
235...Counter, 236...Counter, 237.
...Multiplexer, 238...Frame synchronization circuit,
239...AND gate, 24...Transmission section, 25.
...Receiving unit, 3...Network termination device, 311, 312...
・D-type flip, bflop, 4...exchange machine. Fig. 2 Operation flowchart of the implementation device Fig. 3
timing chart L

Claims (1)

[Claims] 1. A network terminating device connected to a digital exchange via a subscriber line, and a plurality of terminal devices connected to the network terminating device via a bus, each of the plurality of terminal devices and the network terminating device In a phase synchronized bus system in which the phase difference of a signal that occurs depending on the distance between the terminal devices can be automatically adjusted for each of a plurality of terminal devices, a predetermined signal sent from one of the terminal devices The network terminal device that has received the data containing the bits reads and outputs a predetermined bit of the received data using a single clock signal obtained by inverting the clock signal, and the terminal device reads the data containing the predetermined bit without delay. A phase-synchronized bus system that is characterized by transmitting .