JPS61261941A - Communication control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention mostly relates to one communication weight transfer, and particularly to the transmission of response data to received data.

[Back of invention]

Ba Jf! 5. Connect electric bonds, etc. in i yen to each other and make a masterpiece.5. Various parties are proposing so-called vP home automation systems or home bus systems. The home bus system is a common connection (bus)
It is a 5 system in which a number of ρ1 electric machines, etc. are connected to the 5 system, and they are controlled via a bus and data is exchanged.

For the purpose of transmitting signals +5- onto the bus, transmission is performed in units of 1$ each with a packet consisting of multiple bits, and usually, in this packet unit, IM 1
IIIJ will be carried out. One of the 11i allocation methods is the 516-2r & Onien customs communications network con) 0-
It is written in a striped paper titled ``The Necessity of La and A Seishindan''. To put this into perspective, a synchronization code for sending/receiving@field is sent on the bus at regular intervals, and the transmitting terminal sends a telegram using the synchronization code. And at that time, C
5M A (Carrier Sgnca Mbtti
plm Accept ) method 4! 5゜Meanwhile, after receiving this message, the receiving layer ends,
Performs fA recheck, etc., and returns response data (ACK (ACK) when received normally) to messages received within a certain period of time.
wlsaki-°) data, N A Cf (N
o Ack owl - This is a return that includes the data.

Now, in the case of such a five-dimensional bus system, one floor extension simultaneously sends the same message to multiple other terminals fs1! I
There are things to do. This is 2a! Wealth, - Qi I W I Rights 5
However, in the case of simultaneous FIN, response data to the message is sent from multiple terminals at the same time. Therefore,
If multiple floor additions all respond with ACK or NACK responses, there will be no delay, but if ACK responses and NACK responses are sent at the same time, data collision will occur and normal response data will not be corrected. . In this case, if it is neither an ACK response nor a NACK response, it will be treated as a NACK response.1. q, resending the message ρ) is common, but...N
% normal for ACK responses.

There are several 11 [classes]. For example, if it is a simple) retail error, then NA C1! : If it is a response, it will be retransmitted and it will be 1 again! However, retransmitting the message in response to a large NACK response when reception is prohibited is not only unwise, but also leads to a decrease in the transmission efficiency of the path.

[Purpose of the invention]

The purpose of the present invention is to overcome the drawbacks of conventional techniques.

In a bus system, it is impossible to correctly transmit data in response data from a plurality of devices to data in a bus system.

[Summary of the invention]

Purpose '4r: In order to achieve this, the present invention has a method for transmitting response data, transmitting the data on the bus, receiving and receiving the data on the bus, and dividing the transmitted data and the writer's data bit by bit. Compare and if there is a difference, include the missing bits and 4! The feature is that the control circuit that stops the r is changed, and the response data that is to be retransmitted is incremented every time the response data has a higher priority on the bus than other response data. be.

[The bell of invention]

Hereinafter, embodiments of the present invention will be explained in one box.

Figure 1 shows 2mg according to the present invention! 1 is a block diagram showing an example of an i-control device; 1 is a transmitting circuit; FIG.

2 is a receiving circuit, 3 is a communication control circuit, and 4 is a clock generation circuit that supplies the trough or generates a voltage.

5 is a morning assembly f[1lJn circuit, and 6 is a path for transmitting signals.

7 is a transmission signal line, 18 is a reception signal line, 9 is a response period indicator 110 indicating a transmission period of response data, and 11 is a transmission control layer.
is the clock IiM number rising.

Next, the operation of this embodiment will be explained.

In the same figure, when a signal is input to the path 6, the M number is received by the receiving circuit 2, and the received signal is sent to the [communication system both times wr5] through the signal training 8. In the communication control circuit 6.

If the father gI signal is deciphered and the message addressed to you is the same authority signal, the response data is transmitted through the sending signal 7! ! The transmission circuit 1 outputs the response data onto the bus 6. that time.

The communication control circuit 3 sends a signal indicating the response data transmission period to the colliding side control circuit wr5, and causes the competition control circuit 5 to be manufactured during that period. The employee control circuit 5 receives the response data including 4M and the response data output on the screen 6.
Compare the received signal bit by bit with the sentence 1g in 1 and 2,
In that case, if the two ministries have different plans, the response data will be immediately included! Input the control value g for stopping (Iff) to the transmitting circuit 1 via the bit 10. 9. Stops the transmission of the response data after the last bit.

Diagram 2 shows one example of a specific circuit for implementing the present invention, and diagram N5 is a timing diagram of each part to clarify the operation of path 1 of diagram MI2.

In FIG. 2, the same parts as in FIG.
4 is a comparator, 15 is exclusive! ii saltwater gate, 1
6 and 17 are D type slip 7a tsu 1 (for example, TTL 7
4LS 74 ), 18 , 19 , 20 , and 21 are resistors, and a mismatch signal line that compares the transmitted IIM number of 22 with the received signal and transmits a mismatch signal that becomes rHJ when both ministries do not agree. FIG. 3 shows that LSB (Lgazt
5ilnJiaantB"m1lk lower bits"), and C) represents the signal on No. 11 corresponding to the code of F'J.

Next, the production of the circuit shown in Figure 2 will be explained.

First, the timing diagram in the ;i4s diagram shows that another device (not shown) sends a signal on bus 6 with "00000101 J (05H:I
indicates hexadecimal) 5F; When sending the answer data, the same time as I/C, from itself (from 1 communication control circuit 5)
"00000011 J (03H)" shows the case where 5 response data is transmitted. Also, in FIG.

When the rHJ signal and rLJ signal collide on the bus 6, the gI signal level on the bus becomes "L".

rLJiPI has priority. Therefore, as shown above, the response data "013000101 J (05H)" and "
If you try to send 00000011 J (0 fallen) from the LSB to the node at the same time, first, the second bit (D
, bit), and the signal level on bus 6 becomes r
Since this is an LJ, the device attempting to transmit the OJ detects the collision and stops transmitting the third and subsequent bits. Note that at this time, the device transmitting 0 protection will transmit without detecting a collision. Next, I will explain in detail the specific old method of centralizing this. , the signal (81) on the bus 6 received by the receiving circuit 2 appears in the signal gm8.Then, this
Signals (8 n) are input to the exclusive embedding gate 15 for the missing 1 on the 8th line, and when the two ministries are compared and there is no agreement, a mismatch signal (3rd flaw (22)) is output to the signal gate 22. In the example shown in Figure S, the first bit (Do bit) is both rHJ, but the second bit (D1 bit) is not connected to the bus even though the "I" signal is being transmitted as response data T7J. Since another device connected to 6 is transmitting the rLJM number, the received signal (8; is rLJ number and 7,
A mismatch signal (22) is output to the signal type 22. This fu-ku signal (22)'k7ritsu17c! Tsu, 716
．． 17, the timing is set to 0 tatami and the transmission control signal (1
0) and input it to one input layer of the NOR gate 12 via the 1N gate 10. This included 15 control signal (10) is included if you can say it! This is a prohibition signal, and since a signal mismatch was detected in the 11h range of 3rd generation, brown 2 bit) CD1 bit, the transmission of response data from the 5th bit onwards is prohibited. In this way, the two devices simultaneously transmit 0511 and 05#V as response data, and the nib and the other devices transmit 05M with priority. In other words, when transmitting response data, the response data has a certain amount of time. Therefore, in the present invention, in addition to assigning a code to the answer data, in the code used as the response data.

The code for the normal response (so-called ACK response) I/C is assigned a code with the lowest priority on the bus, and the code attached to the retransmission 11r: positive response is assigned a code with a priority of -
*Assign ai6 code. For example, in response to A
There are 28 types of CK response and NACK response, 03E and 0.
When using 5K, O5H'1tA with low priority
A CK response is assumed, and 05H, which has a high priority, is an NACK response. It was. As response data, there are 3111IM types such as ACK response, retransmission amazine response for abnormal reception, and reception system stop response indicating that receiving 15 thread is being stopped.When using 03M, 05H and 07H, ACK response 'a ' (17
li, foreign xfs stock pottery 6 answer is 05g, and ℃ reception prefecture north response is 03Ji.

As mentioned above, the communication control section 4 was explained in the first part 8 and in Fig. 2 as one of the most important factors, but in reality, this communication control part is connected to an electrical device, etc., and the communication content is Accordingly, a signal to control that electrical safety equipment or other electrical safety equipment carried on the bus is sent from the electrical safety equipment to the communication controller, and other electrical safety equipment is sent via the bus. 1 is made to divide the air + tA vessel.

In addition, in the embodiments shown in Figures 1 and 2, the sound attribute control circuit 5
was realized by hardware.

communication? ! tlJ(+1) The circuit 3 often includes an arithmetic processing unit, and can be implemented not only by hardware but also by software. .

The same parts as in FIG. 1141 are given the same reference numerals.

Furthermore, Fig. 5 shows an example of a diagram for controlling the merging of pictures that includes 1 byte (8 bits) of response data. In the flowchart for live streaming as is with software, the Nth bit of the response data sent by you is 'lk:A, and the corresponding received data '4r:B', and there is a case where these two ministries do not match * In this case, the transmission after that bit is stopped.

In the center Nga of Figure 2, the collector connection of the transistor is connected to the bus, so the rLJ signal has priority on the bus, but if a transformer is used to connect to the bus, the rHJ signal is Sometimes it takes priority. Further, in FIG. 3, a start-stop synchronization transmission in which a start bit and a stop bit are added as response data is used, and the data is transmitted from the LSB, but other foreclosure methods may be used.

Furthermore, there is no risk of surrendering from MSB.
! not. The point is that the response data is transferred onto the bus, and the signal on the bus is transmitted, instead of multiplying the response data by tt.
It compares the included 1j1 bit bit by bit, and if it does not match, it waits for the 2a signal It control unit to stop transmitting the next bit onwards, and then displays the 5th part of the code used for the response data. Just match the code of the response data you want with the code with the highest priority on the bus.

〔Effect of the invention〕

As explained above, in 5, according to the book @ Akira, when response data is sent simultaneously from multiple devices connected to the bus, J6 response data (including 8) is not required! - It is possible to preferentially transmit data, and to eliminate the shortcomings of the above-mentioned prior art, it is possible to use the proposed communication control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of communication control installation according to the present invention, and FIG. 2 is a block diagram showing an example of communication control installation according to the present invention. ! A circuit diagram showing an example of A type of communication control device, Figure 3 is the production of Figure 2.
Fig. 4 is a block diagram showing another embodiment of the communication control device by 2F-Kabuto, and Fig. M5 is an example of a flowchart in the case of using the dependent sound control software according to the present invention. This is what is shown. 1... Transmission circuit 2... Reception 1I21 path 3.
... 4 Shinsashi # (9) Road 5 ... Abusive Liu Go Circuit 6...
・Common transmission line (bus) Male 1 Figure No. 30 (lO) No. 41 ¥]

Claims (2)

[Claims] (1) In a communication control device that has a transmitting circuit that sends data onto a transmission medium and a receiving circuit that receives data on the transmission medium, the transmitted data and the received data are compared bit by bit and a mismatch is detected between the two. In this case, a contention control means is provided to stop the transmission of the next bit onward, and among the data used as response data to the received message, response data that involves retransmission of the message has a higher priority than other response data. A communication control device characterized in that when allocating high data and communicating the response data, the contention control means is operated to preferentially send response data requesting retransmission of a message onto the transmission medium. (2) The communication control device according to claim 1, wherein the competition control means is an arithmetic processing device.