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JPS61261472A - Bias sputtering method and its apparatus - Google Patents

Bias sputtering method and its apparatus

Info

Publication number
JPS61261472A
JPS61261472A JP60099505A JP9950585A JPS61261472A JP S61261472 A JPS61261472 A JP S61261472A JP 60099505 A JP60099505 A JP 60099505A JP 9950585 A JP9950585 A JP 9950585A JP S61261472 A JPS61261472 A JP S61261472A
Authority
JP
Japan
Prior art keywords
substrate
target
deposited
bias
bias sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60099505A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Kamoshita
鴨志田 和良
Hiroaki Nakamura
宏昭 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60099505A priority Critical patent/JPS61261472A/en
Priority to DE3650612T priority patent/DE3650612T2/en
Priority to DE3689388T priority patent/DE3689388T2/en
Priority to EP86106432A priority patent/EP0202572B1/en
Priority to EP93102886A priority patent/EP0544648B1/en
Priority to CA000508851A priority patent/CA1247464A/en
Priority to KR1019860003683A priority patent/KR900005785B1/en
Publication of JPS61261472A publication Critical patent/JPS61261472A/en
Priority to US07/075,208 priority patent/US4816126A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a flat thin film of high purity not contg. the constituent substance of a substrate by depositing the constituent element of a target on the substrate by sputtering without applying bias to the substrate, applying negative potential, and depositing the constituent element of the target by sputtering. CONSTITUTION:A target 3 is placed in a vacuum chamber 1 so that it confronts a substrate 2 in the chamber 1, and the constituent element of the target 3 is deposited on the substrate 2 by sputtering the target 3 with ions without applying negative potential to the substrate 2. After the lapse of a fixed time, negative potential is applied to the substrate 2, and the constituent element of the target 3 is deposited on the substrate 2 under the potential to form a thin film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路の製造に際し、凹凸がある基
板上に、平坦な表面形状を有し緻密な構造の薄膜を形成
するバイアススパッタ法およびバイアススパッタ装置に
関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bias sputtering method for forming a thin film with a flat surface and a dense structure on an uneven substrate when manufacturing semiconductor integrated circuits. and a bias sputtering device.

〔従来の技術〕[Conventional technology]

半導体集積回路等の製造工程において基板上に薄膜を堆
積する方法としては、スパッタ法が広く用いられてきた
。しかし通常のスパッタ法では。
Sputtering has been widely used as a method for depositing thin films on substrates in the manufacturing process of semiconductor integrated circuits and the like. However, with normal sputtering method.

凹凸がある段差部を、平坦部と同様な表面で連続的に被
覆する薄膜を形成することが困難であった。
It has been difficult to form a thin film that continuously covers uneven stepped portions with a surface similar to that of flat portions.

従来のスパッタ法における上記の欠点を改善する方法と
して、バイアススパッタ法が提案されている。この方法
はスパッタを行う基板に負の電位を印加することによっ
て、基板表面に加速したイオンを入射させ、凹凸がある
基板に平坦な表面形状を有する薄膜を形成するものであ
る。
A bias sputtering method has been proposed as a method for improving the above-mentioned drawbacks of the conventional sputtering method. In this method, a negative potential is applied to the substrate to be sputtered so that accelerated ions are incident on the surface of the substrate, thereby forming a thin film having a flat surface on an uneven substrate.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記バイアススパッタ法は基板表面に加速したイオンを
入射させるため、基板表面では堆積と同時にスパッタエ
ツチングが進行し、そのために堆積膜が基板上に十分堆
積されない初期には、スパッタエツチングされた基板の
構成元素が堆積膜中に混入して、形成された堆積膜の純
度を低下させることになる。また、同時に堆積膜の構造
を変化させるため、高品質の薄膜を形成できなくなるば
かりでなく、基板へのダメージが問題になるという本質
的な欠点がある。バイアススパッタ法で二真で示すが、
基板から飛散した酸素およびシリコンによってアルミニ
ウムの結晶粒成長が抑制されるため、結晶粒間に隙間が
ある柱状結晶が成長している。上記のようなアルミニウ
ム膜は無限大の抵抗値を示す。
Since the bias sputtering method described above injects accelerated ions onto the substrate surface, sputter etching progresses at the same time as deposition on the substrate surface. Therefore, in the early stage when the deposited film is not sufficiently deposited on the substrate, the structure of the sputter etched substrate is The elements will be mixed into the deposited film, reducing the purity of the formed deposited film. Furthermore, since the structure of the deposited film is changed at the same time, it not only becomes impossible to form a high-quality thin film, but also has the inherent disadvantage that damage to the substrate becomes a problem. The bias sputtering method is shown by two lines,
Since aluminum crystal grain growth is suppressed by oxygen and silicon scattered from the substrate, columnar crystals with gaps between crystal grains grow. The aluminum film described above exhibits an infinite resistance value.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、基板にバイアスを印加しない状態でターゲッ
トの構成元素をスパッタ堆積したのち、一定時間の遅れ
をおいて、上記基板にバイアスを印加しスパッタ堆積を
行うものである。
In the present invention, constituent elements of a target are sputter-deposited with no bias applied to the substrate, and then, after a certain time delay, a bias is applied to the substrate to perform sputter deposition.

〔作用〕[Effect]

本発明は上記のように、まずターゲット電源を動作させ
て、基板にバイアスを印加しない状態でスパッタを行い
、ターゲット構成元素を基板上に堆積させる。この堆積
膜は基板構成物質が混入しない高純度のターゲット構成
元素で形成されている。つぎに基板にバイアスを印加し
てバイアススパッタを行うが、この際、上記堆積膜はエ
ツチング作用を受けて構成物質が新たに形成される堆積
膜に混入する可能性があるが、上記堆積膜自体が高純度
のターゲット構成物質であるため、混入によって新たに
形成される堆積膜の純度を低下させることかない。さら
に上記バイアススパッタでは基板表面を直接イオンでた
たかないため、上記基板にダメージを与えることが少な
い。
As described above, in the present invention, first, the target power source is operated, sputtering is performed without applying a bias to the substrate, and target constituent elements are deposited on the substrate. This deposited film is formed of highly pure target constituent elements that are not mixed with substrate constituent substances. Next, bias sputtering is performed by applying a bias to the substrate, but at this time, the deposited film is subjected to an etching action, and there is a possibility that constituent materials may be mixed into the newly formed deposited film, but the deposited film itself Since it is a highly pure target constituent material, its contamination will not reduce the purity of the newly formed deposited film. Furthermore, since the bias sputtering does not directly hit the substrate surface with ions, the substrate is less likely to be damaged.

〔実施例〕〔Example〕

つぎに本発明の実施例を図面とともに説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明によるバイアススパッタ装置の一実施例
を示す構成図、第2図は上記実施例のターゲット電源と
基板電源との電力入力の一例を示す図、第3図は上記第
2図のt□待時間対するアルミニウム膜の抵抗率の変化
を示す図、第4図は上記t1が60秒の時のバイアスス
パッタアルミニウム膜表面の走査型電子顕微鏡写真を示
す図、第5図は全膜厚(初期膜厚+バイアススパッタ膜
厚)が1.5−の初期膜厚に対するステップカバレッジ
(d、とdoとの比)の関係を示す図、第6図はライン
アンドスペースが24−24、深さ0.8−の溝がある
基板上に、アルミニウム膜をバイアススパッタしたとき
の走査型電子顕微鏡による断面写真を示す図である。第
1図において、真空室l内に基板2とターゲット3とを
相対して設け、上記ターゲット3と電気的に接続したタ
ーゲット電源4には直流あるいは高周波電源のいずれか
を用いるが、上記ターゲット3が絶縁物で構成される場
合には高周波電源を用いる。基板2と電気的に接続する
基板側電源5は高周波発生器あるいは直流電圧発生器を
用いることができる。上記基板側電源5およびターゲッ
ト電源4、真空排気装置6、ガスコントローラ9.シャ
ッタ10などは、シーケンスコントローラ8から送出さ
れる信号によりそれぞれ駆動あるいは停止などの状態に
保持される。
FIG. 1 is a block diagram showing an embodiment of a bias sputtering apparatus according to the present invention, FIG. 2 is a diagram showing an example of power input between the target power supply and the substrate power supply in the above embodiment, and FIG. Fig. 4 shows a scanning electron micrograph of the surface of the bias sputtered aluminum film when t1 is 60 seconds, and Fig. 5 shows the change in resistivity of the aluminum film with respect to the waiting time of t□. A diagram showing the relationship between the step coverage (ratio of d and do) with respect to the initial film thickness when the thickness (initial film thickness + bias sputtering film thickness) is 1.5-. It is a figure which shows the cross-sectional photograph taken by the scanning electron microscope when bias-sputtering an aluminum film on the board|substrate with the 0.8-depth groove|channel. In FIG. 1, a substrate 2 and a target 3 are provided facing each other in a vacuum chamber l, and a target power source 4 electrically connected to the target 3 is either a direct current or a high frequency power source. A high frequency power source is used when the power source is made of an insulator. The substrate side power supply 5 electrically connected to the substrate 2 can be a high frequency generator or a DC voltage generator. The substrate side power supply 5, the target power supply 4, the vacuum exhaust device 6, the gas controller 9. The shutter 10 and the like are each held in a driven or stopped state by a signal sent from the sequence controller 8.

真空室1に基板2を設置し、真空排気装置6により真空
室1の排気を行うとともに、ガスコントローラ9を用い
てスパッタガスを真空室1に導入し一定の圧力に保つ、
この時のスパッタガスとしてはアルゴンなどの不活性ガ
スを用いる。つぎにターゲット電源4を作動させる。こ
の時、上記ターゲット電極3が平行平板型の2極スパツ
タの場合には、ターゲット電極3と基板2との間にプラ
ズマ7が発生する。またターゲット電極3に併設したマ
グネトロンを用いた場合には、ターゲット電極3の近傍
にプラズマ7′が発生する。この時、ターゲット電極3
とプラズマ7または7′間に生じるバイアスによるスパ
ッタ作用により、基板2上にターゲット構成元素が堆積
しようとする。シャッタ10を開き、基板2上にターゲ
ット構成元素を堆積してt1時間経過後、基板2に高周
波または直流バイアスを加えて堆積を行う。この場合イ
オン衝突によるエツチング作用が存在する状態で堆積が
行われるため、基板2の表面に凹凸がある場合でも平坦
な平面を有する膜を堆積することができる。
A substrate 2 is installed in a vacuum chamber 1, and the vacuum chamber 1 is evacuated by a vacuum exhaust device 6, and a sputtering gas is introduced into the vacuum chamber 1 using a gas controller 9 to maintain a constant pressure.
An inert gas such as argon is used as the sputtering gas at this time. Next, the target power source 4 is activated. At this time, if the target electrode 3 is a parallel plate type bipolar sputter, plasma 7 is generated between the target electrode 3 and the substrate 2. Furthermore, when a magnetron attached to the target electrode 3 is used, plasma 7' is generated near the target electrode 3. At this time, target electrode 3
The target constituent elements tend to be deposited on the substrate 2 due to the sputtering effect due to the bias generated between the plasma 7 or 7'. The shutter 10 is opened and the target constituent elements are deposited on the substrate 2, and after a time t1 has elapsed, deposition is performed by applying high frequency or DC bias to the substrate 2. In this case, since the deposition is performed in the presence of etching action due to ion bombardment, a film having a flat surface can be deposited even if the surface of the substrate 2 is uneven.

上記の工程における基板電力とターゲット電力との時間
変化の一例を第2図に示す。このような時間制御は手動
でも可能であるが、シーケンスコントローラ8からの信
号によって制御することにより精度が高い制御を行うこ
とができる。t1時間までに堆積した薄膜は、基板2に
高周波または直流バイアスを加えていないから基板構成
物質の混入がない高純度のものである。つぎに行うt1
時間以後のバイアスを印加した状態で行う堆積は、上記
t□待時間基板2に堆積した薄膜がエツチング作用を受
けて堆積膜に混入する可能性があるが、この薄膜自体が
高純度のターゲット構成物質であるため、上記堆積膜の
純度を劣化させるということはない。さらに、基板2の
表面を直接イオンでたたかないため、基板に与えるダメ
ージは少なくなる。基板2としてS io、を用いたバ
イアススパッタによるアルミニウム膜形成時におけるt
□待時間アルミニウム膜の抵抗率との関係を第3図に示
す。t1時間が0の場合、つまり最初から基板にバイア
スを印加した状態でアルミニウム堆積したときには、抵
抗率が無限大になる。この時のアルミニウムの表面状態
は第7図に示すとおりである。第7図に示す走査型電子
顕微鏡写真から判るように、結晶間に隙間がある結晶粒
成長が生じている。一方、t1時間を3.6.15.2
00秒と増すにしたがい抵抗率は減少し、ばらつきも少
なくなり、第4図の走査型電子顕微鏡写真に示すような
均一性がより平滑表面を有するアルミニウム膜の堆積が
可能になる。また、t工が長すぎた場合にはバイアスを
基板2に加えることなく堆積する膜の膜厚が厚くなるた
め、つづいてバイアスを印加しアルミニウムを堆積して
所望の膜厚を得た場合、カバレッジがよい平坦な表面形
状を得ることができなくなる。
FIG. 2 shows an example of temporal changes in substrate power and target power in the above process. Although such time control can be performed manually, control using signals from the sequence controller 8 allows highly accurate control. The thin film deposited by time t1 is of high purity and is free from contamination with substrate constituent substances because no high frequency or direct current bias is applied to the substrate 2. Next t1
If the deposition is performed with a bias applied after the above t□ waiting time, there is a possibility that the thin film deposited on the substrate 2 will be mixed into the deposited film due to the etching action, but this thin film itself is a highly pure target composition. Since it is a substance, it does not deteriorate the purity of the deposited film. Furthermore, since the surface of the substrate 2 is not directly bombarded with ions, damage to the substrate is reduced. t when forming an aluminum film by bias sputtering using Sio as the substrate 2
□The relationship between waiting time and resistivity of the aluminum film is shown in Figure 3. When the t1 time is 0, that is, when aluminum is deposited with a bias applied to the substrate from the beginning, the resistivity becomes infinite. The surface condition of the aluminum at this time is as shown in FIG. As can be seen from the scanning electron micrograph shown in FIG. 7, grain growth occurs with gaps between crystals. On the other hand, t1 time is 3.6.15.2
As the time increases to 00 seconds, the resistivity decreases and the variation becomes smaller, allowing the deposition of an aluminum film with a more uniform and smooth surface as shown in the scanning electron micrograph of FIG. In addition, if the t process is too long, the thickness of the film deposited without applying a bias to the substrate 2 will become thicker, so if a bias is subsequently applied and aluminum is deposited to obtain the desired film thickness, It becomes impossible to obtain a flat surface shape with good coverage.

幅2−1深さ0.871mの段差上に、初期堆積膜厚(
バイアスなし、t工時間堆積)を変化させて堆積したの
ち、引続きバイアスを印加して全膜厚(初期膜厚+バイ
アススパッタ膜厚)を1.5.ca (d、)としたと
き、溝のエツジから溝の中心線上の膜表面までの距離(
d工)との比、d、/d工と初期堆積膜厚との関係を第
5図に示す0図より初期膜厚(11時間で堆積する膜厚
)が厚くなるほどd□とd、どの比が小さくなり、カバ
レッジが悪くなることがわかる。第6図に、本発明によ
る方法および装置を用いて、ラインアンドスペースが2
4−2−1深さ0.8t1mの溝がある基板上に、適切
なt4を選びアルミニウム膜を堆積したときの走査型電
子顕微鏡写真を示す、上記写真から明らかなように、ア
ルミニウムが基板の溝に完全に埋込まれ、カバレッジが
非常によい膜を形成している。
The initial deposited film thickness (
After the deposition was performed by varying the deposition time (without bias, t process time), the total film thickness (initial film thickness + bias sputtering film thickness) was increased to 1.5. When ca (d,), the distance from the edge of the groove to the film surface on the center line of the groove (
Figure 5 shows the relationship between the ratio of d and /d and the initial deposited film thickness. It can be seen that the ratio becomes smaller and the coverage becomes worse. FIG. 6 shows that, using the method and apparatus according to the present invention, two lines and spaces are
4-2-1 This is a scanning electron micrograph showing an aluminum film deposited on a substrate with a groove of 0.8t1m in depth by selecting an appropriate t4. It is completely embedded in the groove, forming a film with very good coverage.

上記に説明したように適切なt工を選びシーケンスコン
トローラ8で高精度の制御を行うことにより、表面が平
滑で抵抗率が低く、また基板へのダメージが少なく、均
一でカバレッジがよい良質な薄膜を堆積することができ
る。
As explained above, by selecting an appropriate t-process and performing high-precision control using the sequence controller 8, a high-quality thin film with a smooth surface, low resistivity, little damage to the substrate, and uniform coverage can be produced. can be deposited.

〔発明の効果〕〔Effect of the invention〕

上記のように本発明によるバイアススパッタ法およびバ
イアススパッタ装置は、真空室内の基板に負の電位を印
加した状態で上記基板と対向して設けたターゲットをイ
オンによりスパッタし、スパッタされた上記ターゲット
の構成元素を上記基板上に堆積させるバイアススパッタ
法において、上記基板に負の電位を印加しない状態で上
記ターゲット構成元素を基板上に堆積したのち、上記基
板に負の電位を印加した状態でターゲット構成元素を上
記基板上に堆積して薄膜を形成したことにより、基板構
成物質が薄膜に混入することがなく高純度で、基板表面
に凹凸があっても平坦で均一な、しかもカバレッジが非
常によく、基板に与えるダメージが少ない薄膜の堆積を
行うことができる。したがって半導体集積回路の配線な
どの多層化に対しても1段差切れがなく信頼性が高い配
線形成が得られるという効果がある。
As described above, the bias sputtering method and bias sputtering apparatus according to the present invention sputters a target provided facing the substrate with ions while applying a negative potential to the substrate in a vacuum chamber, and sputters the sputtered target. In the bias sputtering method for depositing constituent elements on the substrate, the target constituent elements are deposited on the substrate without applying a negative potential to the substrate, and then the target constituent elements are deposited on the substrate while a negative potential is applied to the substrate. By depositing the elements on the above substrate to form a thin film, the substrate constituent materials do not mix into the thin film, resulting in high purity, flat and uniform even if the substrate surface has irregularities, and very good coverage. , thin films can be deposited with less damage to the substrate. Therefore, even when the wiring of a semiconductor integrated circuit is multilayered, there is an effect that highly reliable wiring can be formed without any breakage in one step.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるバイアススパッタ装置の一実施例
を示す構成図、第2図は上記実施例のターゲット電源と
基板電源との電力入力の一例を示す図、第3図はt□時
間に対するアルミニウム膜の抵抗率の変化を示す図、第
4図は上記t1が60秒のときのバイアススパッタアル
ミニウム膜表面の走査型電子顕微鏡写真を示す図、第5
図は全膜厚がλ、5Isの時の初期膜厚に対するステッ
プカバレッジの関係を示す図、第6図はラインアンドス
ペースが2pm  2Bra、深さ0.8.の溝を有す
る基板上にアルミニウム膜をバイアススパッタした時の
走査型電子顕微鏡による断面写真を示す図、第7図は従
来のバイアススパッタでS i O2上に形成したアル
ミニウム膜表面の走査型電子顕微鏡写真を示す図である
。 1・・・真空室      2・・・基板3・・・ター
ゲット    4・・・ターゲット電源5・・・基板側
電源 8・・・シーケンスコントロール 喝′51゛出願人 口本電信電話?tg式会社代理人弁
理士  中 村 純之助 第2図 時間 第3図 し1の時間(sec) 第4図 2P″′L 第5図 橢−(、Lm) 1区m 手続補正書(自発) 昭和60年 6月28日 特許庁長官 志 賀   学 殿 1、事件の表示   昭和60年特許願第99505号
2、発明の名称   バイアススパッタ法およびその装
置3、補正をする者 事件との関係     特許出願人 名  称   (422)日本電信電話 株式会社5、
補正の対象   図 面 6、補正の内容   第3図を添付のとおり訂正する。 ノー=−\\ 第3図 し1の時間(sec)
FIG. 1 is a configuration diagram showing an embodiment of a bias sputtering apparatus according to the present invention, FIG. 2 is a diagram showing an example of power input between the target power supply and the substrate power supply in the above embodiment, and FIG. Figure 4 shows the change in resistivity of the aluminum film. Figure 4 is a scanning electron micrograph of the surface of the bias sputtered aluminum film when t1 is 60 seconds.
The figure shows the relationship between the step coverage and the initial film thickness when the total film thickness is λ and 5Is. In Fig. 6, the line and space is 2pm, 2Bra, and the depth is 0.8. Figure 7 shows a cross-sectional photograph taken by a scanning electron microscope when an aluminum film was bias-sputtered onto a substrate having grooves. It is a figure showing a photograph. 1...Vacuum chamber 2...Substrate 3...Target 4...Target power supply 5...Substrate side power supply 8...Sequence control system 51゛Applicant Telegraph and Telephone? TG type company representative patent attorney Junnosuke Nakamura Figure 2 Time Figure 3 Time 1 (sec) Figure 4 2P'''L Figure 5 - (, Lm) Section 1 m Procedural amendment (voluntary) Showa June 28, 1960 Manabu Shiga, Commissioner of the Patent Office1, Indication of the case Patent Application No. 99505 of 19852, Title of the invention Bias sputtering method and its device3, Relationship with the amendment person case Name of patent applicant (422) Nippon Telegraph and Telephone Corporation 5,
Target of amendment: Drawing 6 and details of amendment: Drawing 3 will be corrected as attached. No=-\\ Fig. 3 Time of 1 (sec)

Claims (2)

【特許請求の範囲】[Claims] (1)真空室内の基板に電位を印加した状態で上記基板
に対向して設けたターゲットをイオンによりスパッタし
、スパッタされた上記ターゲットの構成元素を上記基板
上に堆積させるバイアススパッタ法において、上記基板
に負の電位を印加しない状態で上記ターゲット構成元素
を基板上に堆積したのち、上記基板に負の電位を印加し
た状態でターゲット構成元素を上記基板上に堆積して、
薄膜を形成することを特徴とするバイアススパッタ法。
(1) In the bias sputtering method, a target provided opposite to the substrate is sputtered with ions while a potential is applied to the substrate in a vacuum chamber, and constituent elements of the sputtered target are deposited on the substrate. The target constituent element is deposited on the substrate in a state where no negative potential is applied to the substrate, and then the target constituent element is deposited on the substrate while a negative potential is applied to the substrate,
A bias sputtering method characterized by forming a thin film.
(2)真空室内の基板に電位を印加した状態で上記基板
に対向して設けたターゲットをイオンによりスパッタし
、スパッタされた上記ターゲットの構成元素を上記基板
上に堆積させるバイアススパッタ法において、上記ター
ゲットの電極に直流電圧あるいは高周波電圧を印加する
ターゲット電源と、上記基板に直流電圧あるいは高周波
電圧を印加する基板側電源と、上記ターゲット電源作動
後一定時間遅れて基板側電源が作動するように、上記各
電源の印加および停止を制御するシーケンスコントロー
ル機構とを備えたことを特徴とするバイアススパッタ装
置。
(2) In the bias sputtering method, a target provided opposite to the substrate is sputtered with ions while a potential is applied to the substrate in a vacuum chamber, and constituent elements of the sputtered target are deposited on the substrate. A target power source that applies a DC voltage or high frequency voltage to the electrode of the target, a substrate side power source that applies a DC voltage or high frequency voltage to the substrate, and a substrate side power source that operates after a certain time delay after the target power source is activated. A bias sputtering apparatus characterized by comprising a sequence control mechanism for controlling application and stopping of each of the above-mentioned power supplies.
JP60099505A 1985-05-13 1985-05-13 Bias sputtering method and its apparatus Pending JPS61261472A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP60099505A JPS61261472A (en) 1985-05-13 1985-05-13 Bias sputtering method and its apparatus
DE3650612T DE3650612T2 (en) 1985-05-13 1986-05-12 Process for the planarization of a thin Al layer
DE3689388T DE3689388T2 (en) 1985-05-13 1986-05-12 Process for producing a leveled aluminum thin film.
EP86106432A EP0202572B1 (en) 1985-05-13 1986-05-12 Method for forming a planarized aluminium thin film
EP93102886A EP0544648B1 (en) 1985-05-13 1986-05-12 Method for forming a planarized Al thin film
CA000508851A CA1247464A (en) 1985-05-13 1986-05-12 Method for forming a planarized thin film
KR1019860003683A KR900005785B1 (en) 1985-05-13 1986-05-12 Manufacturing method of planar thin film
US07/075,208 US4816126A (en) 1985-05-13 1987-07-20 Method for forming a planarized thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60099505A JPS61261472A (en) 1985-05-13 1985-05-13 Bias sputtering method and its apparatus

Publications (1)

Publication Number Publication Date
JPS61261472A true JPS61261472A (en) 1986-11-19

Family

ID=14249122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60099505A Pending JPS61261472A (en) 1985-05-13 1985-05-13 Bias sputtering method and its apparatus

Country Status (1)

Country Link
JP (1) JPS61261472A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01195271A (en) * 1988-01-29 1989-08-07 Hitachi Ltd Method and device for sputtering
JPH03180467A (en) * 1989-06-09 1991-08-06 Tadahiro Omi Method and device for forming thin film
JPH0855821A (en) * 1994-08-16 1996-02-27 Nec Corp Thin film forming device and method of forming thin film
JPH10298753A (en) * 1997-02-19 1998-11-10 Canon Inc Reactive sputtering device, and formation of thin film using this
JPH111771A (en) * 1997-02-19 1999-01-06 Canon Inc Thin film forming apparatus and thin film formation using the same
US6559061B2 (en) 1998-07-31 2003-05-06 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58194334A (en) * 1982-05-07 1983-11-12 Nec Corp Formation of thin film
JPS59197567A (en) * 1983-04-19 1984-11-09 Fujitsu General Ltd Sputtering apparatus
JPS61153275A (en) * 1984-12-25 1986-07-11 Anelva Corp Formation of thin film by sputtering

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58194334A (en) * 1982-05-07 1983-11-12 Nec Corp Formation of thin film
JPS59197567A (en) * 1983-04-19 1984-11-09 Fujitsu General Ltd Sputtering apparatus
JPS61153275A (en) * 1984-12-25 1986-07-11 Anelva Corp Formation of thin film by sputtering

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01195271A (en) * 1988-01-29 1989-08-07 Hitachi Ltd Method and device for sputtering
JPH03180467A (en) * 1989-06-09 1991-08-06 Tadahiro Omi Method and device for forming thin film
JPH0855821A (en) * 1994-08-16 1996-02-27 Nec Corp Thin film forming device and method of forming thin film
JPH10298753A (en) * 1997-02-19 1998-11-10 Canon Inc Reactive sputtering device, and formation of thin film using this
JPH111771A (en) * 1997-02-19 1999-01-06 Canon Inc Thin film forming apparatus and thin film formation using the same
US6559061B2 (en) 1998-07-31 2003-05-06 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6709987B2 (en) 1998-07-31 2004-03-23 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6992012B2 (en) 1998-07-31 2006-01-31 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects

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