JPS61258521A - digital filter - Google Patents

Abstract

PURPOSE:To attain operation in the same operation speed as multiplication and accumulative addition linearly by a multiplier with a small circuit size in case of a highway accurate digital filter by providing a companding characteristic to the data and result of multiplication of filter coefficient. CONSTITUTION:A ROM3 storing a filter coefficient of a digital filter is provided in addition to a RAM1 storing data corresponding to coefficients K17-K9 delayed timewise from the center of the filter coefficient and a RAM2 storing a data corresponding to coefficients K1-K9 led timewise from the center of the filter coefficient, and when the data requires a dynamic range over a threshold value, the data with the companding characteristic is stored. Further, the ROM3 is provided with 1-bit information discriminating whether or not the companding characteristic is applied to the coefficient data in addition to the filter coefficient data. The dynamic range of the digital filter coefficient is designed in 20-bit, the dynamic range 17-bit is used as the threshold value and 3-bit companding characteristic is applied to the data having the dynamic range over 17-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital filter having a multiplier, and particularly to a digital filter that is configured to be suitable for reducing the circuit scale of the multiplier and increasing the speed of calculation. Regarding digital filters.

[Background of the invention]

As a method for configuring a highly accurate digital filter without increasing the number of multiplications, for example, Japanese Patent Laid-Open No. 59-3
As shown in Japanese Patent No. 3922, a method is known in which shift information is stored in one of the coefficients of a digital filter and the amount of shift is determined based on the information.

According to this method, the filter operation must wait until the shift is completed based on the maximum shift amount. Also, a timing circuit is required to generate and extract the shift pulse. .

[Purpose of the invention]

An object of the present invention is to provide a companding characteristic to filter coefficient data and multiplication results, so that a high-precision digital filter can be used to perform linear multiplication and cumulative addition using a small-sized multiplier. The object of the present invention is to provide a digital filter that can perform calculations at equivalent calculation speed.

[Summary of the invention]

In order to realize a highly accurate digital filter, it is necessary to have a long truncation range at both ends of the impulse response of the filter transfer function.To do this, the dynamic range of the filter coefficients must be widened.However, Observing the range bits of the actual filter coefficients, it was found that although the range bits are used effectively in the center of the impulse response of the filter transfer function, the dynamic range of the filter coefficients is relatively small elsewhere.

Therefore, if we use a method that increases the precision of the filter coefficients and compands the dynamic range of the filter coefficients by rounding the lower bits when the absolute value of the filter coefficients becomes larger than a certain threshold, it is possible to The idea is that a highly accurate digital filter can be realized without increasing the circuit scale. Additionally, as a method for normalizing the product, shift information is added to all of the filter coefficient registers, thereby reducing the burden on the timing circuit.

Furthermore, in order to reduce calculation time, we decided to use a selector as a normalization circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In the embodiment shown in FIG. 1, in order to increase the calculation time required for data processing, the data is added together and then multiplied by the filter coefficient, taking advantage of the fact that the coefficients of the digital filter are left and right symmetrical. method.

Figure 2 shows the impulse response of the filter.

Here, for simplicity, the filter order is set to 17th.

In Figure 1, 1 is a coefficient that is delayed in time (17 in Figure 2) from the center of the filter coefficients (9 in Figure 2).
FtAM stores data corresponding to 9), and 2 is a coefficient (2) that is ahead in time from the center of the filter coefficients.
RAM that stores data corresponding to 1 to 9) in Figure 2
, 5 is a ROM that stores the filter coefficients of the digital filter, and if the data requires a dynamic range exceeding a certain threshold value, data with companding characteristics is stored therein. .

In addition to the filter coefficient data, the ROM 3 also contains an i
Contains btt information.

4 is an address control circuit that controls the addresses of FLAM i, 2 and ROM3. 5 is a register that temporarily stores the data in RAM1 in synchronization with the latch signal (!1), and transfers the data in RAM1 to RAM2. 6 is the RAM when calculating the center of the filter coefficient (corresponding to 9 in Figure 2)
1. R to prohibit addition of output data of RAM2.
This is a clear circuit for AM2 output.

7 is an addition circuit for the output of RAM1 and the output of RAM2, 8 is a multiplier for the output of adder 7 and the coefficient data stored in ROM3, and 9 is whether companding characteristics are applied to the coefficient data in ROM5. This is a selection circuit that applies inverse companding characteristics to the multiplication result based on information that determines.

10 is a register for temporarily storing the output of the selection circuit 9; 11
1 is an adder that adds the outputs of register 10 and register 12; 12 is a register that temporarily stores the output of adder 11;
3 is a register that temporarily stores output data in synchronization with the latch signal (2) when the digital filter output is determined in the register 12'.

In this embodiment, the dynamic range of the digital filter coefficient is designed to be 23 bits, and the dynamic range of 17 bits is set as the threshold value, and for data having a dynamic range of 17 bits or more,
It was decided to apply a companding characteristic of t.

The data format is 2's complement representation, and the most significant bit is in btt. Further, when performing 5-bit companding, the information of the 3rd bit from the LSB is rounded off so that the rounding error is minimized.

FIG. 6 shows the relationship between the coefficient data of the digital filter and the data stored in the ROM 3 corresponding to the data.

In Figure 6, coefficient data (1) J: Uni, the dynamic range of the coefficient is 17 bits including the sine bit.
The following stores the 5th bit to LSB from the 2nd bit to the 17th bit of ROM data, and
As the data sign bit, the MSH data of the coefficient data is stored in the MSB of the ROM data. Further, to indicate that this data has been subjected to companding characteristics, 0'' is given to the 18th bit of the ROM data as companding information btt.

For coefficient data (2) where the dynamic range of the coefficient is 18 bits or more including the sign bit, after rounding off the information of the 18th bit of the coefficient data,
．． 19. Cut off 20 bits. In other words, after rounding off the 18b-th information, 17 from the MSB of the coefficient data
From the MSB of the ROM data to the 17th bit
Store up to the it-th item. In order to show that this data has not been subjected to companding characteristics, the companding information bit is R.
Give to 1 xp to the 18th bit of the OM data.

In this embodiment, the data is 16 bits, but since the data is added in the adder 7, the data is input to the multiplier 8 in 17 bits. The configuration of the multiplier 8 in this embodiment is 17 bits x 17 bits.

The multiplication result of the multiplier 80 is temporarily stored in the register 10, and the length required in the register 10 is determined by the bit length of the output data and the number of cumulative additions performed in the adder 11. The btt length is determined to absorb the propagation of the truncation error. In this embodiment, bits of register 10 are set for 16 bits of output data.
The t length was set to 25 bits to prevent product truncation errors from propagating to the output data due to cumulative addition.

Also, since it is sufficient to calculate the product with 25-bit precision,
In the multiplier 8 of 17blt x 17bit, the output is 3
Requiring all three bits only increases the circuit scale and has nothing to do with the accuracy of the output data. Therefore, in the multiplier 8 of this embodiment, the product is rounded down in the part where the product is derived, and the output btt of the multiplier 8 is set to 24 bits.

Among the 24 bits output from the multiplier 8, the lower 3 bits may include a truncation error due to the truncation of the product derivation part. If this is restored to a linear product using the companding information bit, the filter coefficient dynamic range is 17 b
2 from the MSB as a product without error propagation when it is less than or equal to it.
When 4 bits are valid and the filter coefficient dynamic range is 18 bits or more, the MSB is the product without error propagation.
From then on, 21 bits are valid.

There are 53 filter coefficients used in this example, of which 6 have a dynamic range of 18 bits or more.
It was. In other words, by giving the companding characteristic, the dynamic range of most of the products (50 out of 53) is apparently increased by 3 bits. It has a circuit configuration of scale.

FIG. 4 shows the relationship between the dynamic range of the filter coefficient and the dynamic range of the product output of the multiplier 8 when the product output is set to 24 bits.

In FIG. 4, the broken line shows the case of this embodiment, and the solid line shows the case where the coefficient dynamic range is 20 bits linear and the multiplier 8 is 1
This is the case when the configuration is 7 bits x 20 bits.

The dashed line indicates the filter coefficient dynamic range is 17
Bit linear, multiplier 8 is 17 bits x 17 bits
This is a case where it is configured as follows.

From FIG. 4, according to this embodiment, 17bit x 17bit
It can be seen that the calculation precision equivalent to 17 bits x 20 bits can be obtained with a multiplier of t.

FIG. 5 shows a circuit as a specific example of the selection circuit 9 used in this embodiment. The circuit shown in FIG. 5 is similar to the ROM shown in FIG.
3, the companding information bi stored as shown in FIG.
This circuit selects the multiplier output Qn when the companding information pit is "1" and selects Qn+s when the companding information pit is "1" as the linear multiplication result Mn (1≦n≦20) according to t.

For M21 + M22, the companding information bit is '1
'', Q211 and Q22 are selected respectively, and when PA is 0'', Q23, which is a sign bit, is selected.

Regarding M2°, the sign bit Q23 is selected regardless of the state of the companding information pit.

In this embodiment, the adder 11 adds 2 bits to the MSB side for overflow prevention so that the 23-bit addition result data does not overflow during cumulative addition.
It has a 5-bit full adder configuration.

The register 12 is a register that temporarily stores 25 bits of addition result data, and uses 5 bits from the MSB to detect whether or not an overflow has occurred in the data output to the register 16.

When the accuracy of the product output data input to the adder 11 is considered, the area of the multiplier of this embodiment can be reduced by about 8% compared to a multiplier with a 17 bit x 17 bit configuration. Also, 1
The area can be reduced by about 18% compared to a multiplier with a 7b x 20 bit configuration.

In addition, the filter characteristics of this example are 9 as a cutoff characteristic.
Achieved 6dB. - 10,000, the filter characteristic with linear filter coefficients is 20 bits.
When it was made linear, the cutoff characteristic was 97dB. Furthermore, when the filter coefficient is set to 17 bit linear, the cutoff characteristic is 90.5 dB, which not only increases the circuit scale but also significantly deteriorates the characteristics.

〔Effect of the invention〕

According to the present invention, the design values of the coefficients of the digital filter are given companding characteristics in advance, and the apparent calculation accuracy can be improved.
Conventionally, an n-bit x m-bit multiplier was used with m bits and filter coefficients, but m1
By giving a companding property of (ml<m), n
Equivalent filter characteristics can be achieved with a bit x (m-ml) bit multiplier.

Also, with linear filter coefficients, n bits x (m-m
l) Compared to a digital filter configured with bit multipliers, it is possible to configure a digital filter with the same calculation speed and smaller circuit scale.

Further, according to the present invention, it can be applied to all digital filters that perform sampling frequency conversion, and it is possible to increase the speed and reduce the circuit scale without reducing the filter accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention;
Figure 2 is a characteristic diagram showing an example of the impulse response of the filter transfer function, Figure 3 is an explanatory diagram showing the format conversion of filter coefficients, and Figure 4 is a diagram showing the dynamic range of the filter coefficients and the dynamic range of the multiplication result. FIG. 5 is a graph showing the relationship, and a circuit diagram showing an example of the inverse companding circuit used in the present invention. Explanation of symbols

Claims (1)

[Claims] 1) Digital signal data obtained by sampling and digitizing an input signal is written in a randomly accessible memory, and the digital signal data sequentially read from the memory is read out within a sampling period. In a digital filter that performs arithmetic processing by multiplying filter coefficients as data stored in a dedicated memory and cumulatively adding the multiplication results and outputs the result, the filter coefficients as data are stored in the read-only memory. A dynamic range companding characteristic is applied to a predetermined value of 1. A digital filter comprising means for applying a characteristic inverse to the companding characteristic to the multiplication result using the information indicating the companding characteristic.