JPS61258520A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To obtain a variable delay circuit suitable for miniaturization and LSI while no deterioration of waveform and attenuation exists and a minute delay is limited by selecting a signal passing through plural stages of amplifier circuit comprising active elements so as to decide the delay. CONSTITUTION:A signal inputted from an input highway 1 passes sequentially through amplifier circuits 3-l-3-n comprising transistors and is outputted as a signal delayed by an integer multiple of the delay time of each amplifier circuit. An output of each amplifier circuit connects to a selector 4c, one of connected output lines is selected based on a delay selection signal inputted from a delay selection signal terminal 5, the selector 4c selects a desired delay output and the result is sent to a delay output highway 2. In realizing the amplifier circuits 3-l-3-n by active elements, the propagatio delay time per one is adjusted minutely by using the current flowing to them. Thus, any delay is obtained by using the signal at the terminal 5 and a potential at a minute delay adjusting terminal 6.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a variable delay circuit, and more specifically, the present invention relates to a variable delay circuit, and more specifically, a variable delay circuit that has relatively little waveform deterioration or amplitude change, and has a large number of steps with a very fine division width. The present invention relates to a variable delay circuit that can finely adjust the amount of delay per step.

[Summary of the invention]

The present invention connects a plurality of amplifiers such as transistors in series, takes out the output of each amplifier, connects it to a selector, and adds a delay amount selection signal to the selector, so that the input signal can be connected in series. The number of steps that the signal passes through the amplifier is determined arbitrarily, and the signal that has passed through the determined number of steps is taken out as an output.It is possible to obtain steps with a fine amount of delay, and there is no problem with waveform deterioration or amplitude. This makes it possible to make fine adjustments to the amount of delay in each step, and to enable compactness and integration.

[Conventional technology]

Conventionally, delay circuits include delay lines, RC integration circuits, monostable multivibrators, D flip-flops, master-slave JK flip-flops, and the like. In order to make these delay circuits variable, usually a plurality of delay circuits having different delay values are switched to obtain various delay values.

, FIG. 2 is a configuration diagram showing an example of a conventional variable delay circuit.

In FIG. 2, 1 is an input highway, 2 is a delayed output highway, 3a to 3e are fixed delay lines, 4a is an input side selector that selects each delay edge, and 4b is a selector /la.
This is an output side selector that selects in synchronization with.

FIG. 2 shows a case where a variable delay circuit using delay lines is used in a time division switch, and the signal transmitted through the input highway 1 is selected by the input side selector 4a to one of the predetermined delay lines 3a to 3e. Selectively connected to. Delay line 38~3e
is fixedly delayed by the amount of propagation delay (delay due to electrical length) determined by the material. The delayed output is selected by the output side selector 4b and transferred to the delayed output highway 2.

The variable delay circuit having the configuration shown in Figure 2 has the advantage of having little waveform distortion due to impedance mismatching and being able to generate an arbitrary amount of delay depending on the length of the fixed delay line. When the number of steps, that is, many types of delay amounts are required, a large number of fixed delays 111A 3 a to 3Z must be prepared.
In addition, if a large amount of delay is required, the fixed delay a3
The lengths of a to 3e become large. Furthermore, there is a drawback that the amplitude of the signal is attenuated due to propagation, and once the one-step amount is set, the amount cannot be changed or adjusted.

FIG. 3 is a block diagram of a variable delay circuit that improves the drawbacks of FIG. 2.

In FIG. 3, 1 is an input highway, 2 is a delayed output highway, 3 is a delay circuit in which a capacitance C and an inductance L are combined in stages, and 4 is a selector for selecting the amount of delay.

The input signal is input from one terminal of the selector 4, passes through the selector 4, moves the selector 4, passes through the selected terminal, passes through the number of delay stages connected to the right side of that terminal, and then is sent to the output highway 2. Output. Therefore, selecting the leftmost terminal will result in a large delay, and selecting the rightmost terminal will result in a signal that is not delayed at all. This variable delay circuit combines capacitance C and inductance L in stages to form a line i-valently.
□゛It is a true device that causes a propagation delay and adjusts the amount of delay by the number of stages of capacitance C and inductance ``L''.

In the configuration shown in Figure 3, the delay amount of the silk step can be configured to a large number of steps and is suitable for miniaturization, but on the other hand, it is easy to cause 1 reflection and waveform deterioration. is significant, making it unsuitable for delaying high-frequency Shingetsu. Further, in this case as well, there is a problem that the amount of delay per step cannot be changed or adjusted, and it is difficult to obtain a very small amount of delay in terms of accuracy.

[Problem that the invention seeks to solve]

In this way, with conventional variable delay circuits, it is not possible to obtain fine delay steps, the waveform deteriorates and the amplitude changes, and the amount of each delay step cannot be adjusted. It was impossible to

The purpose of the present invention is to improve these problems, to obtain fine delay steps, to have relatively little waveform deterioration and amplitude changes, to be able to finely adjust the amount of each delay step, and to be compact and easy to integrate. The object of the present invention is to provide a suitable variable delay circuit.

[Means for solving problems]

In order to achieve the above object, the variable delay circuit of the present invention is composed of an active element, which is connected to a plurality of amplifier circuits connected in series, and which is connected to the output of each amplifier circuit, and by selecting one of the outputs. A selector circuit that determines the number of delay steps is provided, and when input data is passed through the plurality of amplifier circuits, the selector determines the number of amplifier circuit stages to be passed.

[For production]

The present invention utilizes the propagation delay of an active element as a means for giving a delay to a signal, thereby achieving
Less waveform deterioration and amplitude attenuation.

A small amount of delay is applied, and the step width can also be finely adjusted.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to FIG.

In FIG. 1, 1 is an input highway, 2 is a delayed output highway, 3-1.3-2. ... 3-n is an amplifier circuit realized by a transistor that provides a delay, 4c is a selector that selects an arbitrary delay output, 5 is a delay selection signal terminal,
6 is a minute delay adjustment terminal.

The signal input from the input highway 1 is sent to an amplification port g3-1.3-2...3-n composed of transistors.
By sequentially propagating the signals, a signal delayed by an integral multiple of the delay time of the amplifier circuit is output. The output of each amplifier circuit is connected to the selector 4c, and by selecting one of the connected output lines based on the delay amount selection signal inputted from the delay selection signal terminal 5, the desired delayed output is set to the selector 4c. is selected and sent to delayed output highway 2.

Note that in order to suppress fluctuations in the output signal level due to differences in the number of stages of the amplifier circuits 3-1 to 3-n, the amplification factor of each amplifier circuit is set to approximately 1. In this embodiment, an emitter follower circuit is used as the amplifier circuit, and the amplification factor per stage is approximately l.

The signal inputted from the delay selection signal terminal 5 may be a pulse signal or a predetermined level signal. When the signal is a pulse signal, a counter is provided in the selector 4c to count the pulses, and when the signal is a level signal, a counter is provided to count the pulses. By displaying a binary number using signal lines (for example, 1°0.1” with three signal lines to represent “5”),
Select the output line with the indicated number. In addition, the amplifier circuit 3
-1°...3-n, the capacitor C and the resistor R1°R2 are used to block and shunt the direct current.

Furthermore, as shown in FIG. 1, the amplifier circuit 3-1. ...3
When -n is realized by an active element, the propagation delay time per element can be finely adjusted by the flowing current. Utilizing this, the propagation delay time per step is finely adjusted by changing the potential of the minute delay adjustment terminal 6. That is, any value of delay amount can be obtained by the signal of the delay selection signal terminal 5 and the potential of the minute delay adjustment terminal 6.

According to this embodiment, compared to conventional variable delay circuits, it is possible to make the circuit smaller (IsI, IC), and waveform deterioration and attenuation do not occur, making it possible to realize a small variable delay circuit.

Furthermore, since the selector 4c allows various delay signals to be output to the output terminal, it is extremely effective when designing a system and adjusting the amount of delay after the wiring pattern has been determined. Furthermore, a simple limit signal allows any delayed signal to be output to the same output bin, resulting in less delay limitations than inserting individual gates into the signal line or changing the length of the wiring. It's easy. This is more noticeable when the circuit is integrated and realized using an IC or LSI.

〔Effect of the invention〕

As explained above, according to the present invention, the amount of delay is determined by selecting the signal that has passed through multiple stages of amplifier circuits composed of active elements, so there is no waveform deterioration or attenuation, and the amount of delay is small. This makes it possible to realize a variable delay circuit suitable for miniaturization and LSI integration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a variable delay circuit showing an embodiment of the present invention, and FIGS. 2 and 3 are configuration diagrams each showing an example of a conventional variable delay circuit. 1: Input highway, 2: Delayed output highway, 3.3
a to 3e, 3-1 to 3-n: delay element, 4°4a, 4b
, 4'c: selector, 5: delay selection signal terminal, 6: minute delay adjustment terminal.

Claims (2)

[Claims] (1) It has a plurality of amplifier circuits made of active elements and connected in series, and a selector circuit connected to the output of each amplifier circuit and determining the number of delay steps by selecting one of the outputs, A variable delay circuit characterized in that, when input data is passed through the plurality of amplifier circuits, the number of stages of amplifier circuits to be passed is determined by the selector. (2) The variable delay circuit according to claim 1, characterized in that the propagation delay time of one delay step is adjusted by changing the value of the voltage or current applied to each amplifier circuit. .