JPS61258397A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To relieve defects where a raw line is disconnected at its middle point by driving the row line with a pulse signal supplied from the side opposite to a row decoder. CONSTITUTION:A switch 21 connected to a row line 12 having disconnection after production is energized. Thus an row address signal is supplied to a row decoder 14 and said line 12 is driven at its single end by the decoding output of the decoder 14. Then the line 12 is driven at its end of the other side by the pulse signal phi produced from a pulse generating circuit 20 via the circuit 21 kept under a conduction state. Thus all memory cells 11 connected to the line 12 are selected. This can relieve defects due to the disconnection of the line 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which defective cells caused by disconnection of row lines are relieved.

[Technical Background of the Invention and Problems Therewith] Various methods have been considered in the past as memory relief methods when a defective cell occurs in a semiconductor memory device (hereinafter simply referred to as a memory). For example, by setting up a spare cell,
There is a device that switches to a spare cell when an address for accessing a defective cell is input, and writes data to or reads data from the spare cell.

Further, in a read-only memory such as a mask ROM in which data is programmed during manufacturing, data programming to spare cells is performed after the integrated circuit is completed. Therefore, when programming data to spare cells using fuses made of polycrystalline silicon, for example, it is necessary to program one row of cells, which increases the time and cost required for programming. There is. Furthermore, the probability of failure in programming the spare cells increases, which is undesirable. Therefore, a Hamming code bit is prepared instead of a spare cell, Hamming code data is programmed into this bit during manufacturing, and the error data read from the defective bit is corrected by using this Hamming code data. Some have. FIG. 5 shows a circuit configuration of a conventional mask ROM using such Hamming codes. In FIG. 5, reference numeral 10 denotes a memory cell array composed of a plurality of memory cells 11 including one for storing Hamming code data. Each memory cell 11 has a plurality of row lines 1
2 and a plurality of column lines 13, respectively. A row decoder 14 outputs a decode signal in response to a row address signal and selectively drives the row line 12 based on this decode signal. 15 is a column decoder to which a column address signal is supplied; 16 selects the column line 13 based on the decode signal output from the column decoder 15, and transmits Hamming code data read to the selected column line 13; This is a column gate circuit that has a sense amplifier function that amplifies the data contained in it. 11 is an error correction circuit including a decoding circuit, which is selected by the column gate circuit 16;
The amplified data is decoded, data errors are detected, and if there are errors, they are corrected and supplied to the output buffer 18.

In such conventional memories, the number of cells that can be rescued is limited to one bit. This is because when repairing 2 bits, the configuration of the decoding circuit in the error correction circuit 17 becomes complicated, which is not practical. Moreover, even in such a memory, if the row line 12 is broken in the middle as shown in FIG. 6, the memory cells after the broken line will not be selected, and such a defect cannot be repaired.

[Purpose of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide relief even for products with defects such as line breaks in the middle. The object of the present invention is to provide a semiconductor memory device that can perform the following steps.

[Summary of the invention] In order to achieve the above objects, this invention has the following features:
A pulse generating means is provided, and the pulse generating means generates a pulse signal every time a predetermined row address signal is supplied to the row decoder, and a switch means is provided between the pulse generating means and the row line to prevent disconnection in the middle. By selectively controlling in advance only the switch means inserted between the row line where the disconnection occurs, the row line with the disconnection can be switched on when the row line is driven by the row decoder. It is driven by a pulse signal from the side opposite to the row decoder.

Examples of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a semiconductor memory device according to the present invention. In the figure, 10 is a memory cell array having a plurality of memory cells 11. Each of the memory cells 11 is arranged at each intersection of a plurality of row lines 12 and a plurality of column lines 13.

Reference numeral 14 denotes a row decoder which outputs a decode signal in accordance with the row address signal and selectively drives the row lines 12 based on this decode signal. Each end is connected.

20 is a pulse generating circuit. This pulse generating circuit 20
The above-mentioned row address signal is also supplied to the pulse generating circuit 20, and each time a predetermined address signal is supplied, the pulse generating circuit 20
A pulse signal φ having the same pulse width as the decode signal output from the row decoder 14 is generated. A switch circuit 21 is inserted between the pulse generating circuit 20 and each row line 12, which can control conduction after manufacturing.

Although only the peripheral portion of the memory cell array is shown in the circuit of this embodiment, it goes without saying that column decoders, column gate circuits, sense amplifiers, output buffers, etc. are provided as in the conventional circuit.

In such a configuration, the switch circuit 21 connected to the row line 12 which has been disconnected after manufacturing is made conductive. Then, a row address signal is supplied to the row decoder 14, and when the broken row line 12 is driven from one end by the decoded output of the row decoder 14, the pulse signal φ generated by the pulse generation circuit 20 becomes conductive. It is driven from the other end of the row line 12 where the disconnection has occurred via the switch circuit 21 that is connected. Therefore, the row line 12 where this disconnection has occurred
All the memory cells 11 connected to the row line 12 are selected, and a defect caused by a disconnection of the row line 12 can be repaired.

FIGS. 2 to 4 are circuit diagrams showing specific configurations of the switch circuit 21 in the above embodiment circuit, respectively. The one in FIG. 2 is an example in which each switch circuit 21 is constituted by a resistance element 31 made of a high-resistance polycrystalline silicon layer. This resistance element 31 has a high resistance value immediately after manufacture, and is then selectively reduced in resistance by laser annealing to make it conductive.

The one in FIG. 3 connects each switch circuit 21 with a load resistance element 41 made of a polycrystalline silicon layer of high resistance similar to the above and a fuse element 42 made of a polycrystalline silicon layer inserted in series between the power supplies, and the load. This is an example configured with a MoS transistor 43 whose gate is connected to a connection point between a resistance element 41 and a fuse element 42. In this case, by selectively blowing out the fuse element 42 by irradiation with a laser or the like, the gate of the MOS transistor 43 is set to a high potential and turned on, thereby making it conductive. Note that in this case, a load MOS transistor or the like may be used instead of the load resistance element 41.

In the one shown in FIG. 4, MOS transistors 51 and 52 are inserted between the row line 12 and the high potential and low potential power supplies,
The output terminal of an inverter 53 to which an inverted signal of the pulse signal φ is input is connected to the gate of the S transistor 51,
The pulse signal φ is applied to the gate of the MOS transistor 52.
is connected to the output terminal of the inverter 54 to which the input voltage is input, and a fuse 55 is connected between the output terminal of the inverter 53 and a low-potential power source, and a fuse 56 is connected between the output terminal of the inverter 54 and the low-potential power source. Connect each switch circuit 21
This is an example of configuring . In this case, fuse element 55.5
By selectively fusing both the inverters 53 and 6, the inverter 53
．． The output of 54 is supplied to the gates of MOS transistors 51 and 52. At this time, the pulse signal φ is buffer-amplified and supplied to the gate of the MoS transistor 51.

[Effects of the Invention] As explained above, the present invention provides a semiconductor memory device that can be repaired even in cases where a defect such as a break in a row line occurs. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
4 to 4 are circuit diagrams each showing a specific configuration of a part of the above embodiment circuit, FIG. 5 is a block diagram of a conventional memory, and FIG. 6 is a circuit diagram showing a part of the configuration of the conventional memory. It is. 10... memory cell array, 11... memory cell,
12... Row line, 13... Column line, 14... Row decoder, 20... Pulse generation circuit, 21... Switch circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] A row decoder that is supplied with a row address signal and outputs a decode signal in accordance with the row address signal, a row line that has one end connected to the decode signal output terminal of the row decoder, and a row line that is selected based on the signal of the row line. a memory cell that is driven automatically, a pulse generating means that generates a pulse signal every time a predetermined row address signal is supplied to the row decoder, and a pulse generating means inserted between the pulse generating means and the other end of the row line. is,
1. A semiconductor memory device comprising a switch means which selectively conducts only those inserted between a row line and a row line having a disconnection in advance.