JPS61254398A - IC card - Google Patents
IC cardInfo
- Publication number
- JPS61254398A JPS61254398A JP60095431A JP9543185A JPS61254398A JP S61254398 A JPS61254398 A JP S61254398A JP 60095431 A JP60095431 A JP 60095431A JP 9543185 A JP9543185 A JP 9543185A JP S61254398 A JPS61254398 A JP S61254398A
- Authority
- JP
- Japan
- Prior art keywords
- card
- semiconductor integrated
- integrated circuit
- terminals
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims 1
- 239000000696 magnetic material Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 24
- 230000000694 effects Effects 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000006378 damage Effects 0.000 description 11
- 230000005611 electricity Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000011111 cardboard Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Credit Cards Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体集積回路を含むICカードに係り、特
に半導体集積回路の静電破壊防止に好適な電気的接続方
式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an IC card including a semiconductor integrated circuit, and particularly to an electrical connection method suitable for preventing electrostatic damage of a semiconductor integrated circuit.
従来のICカードは、実開昭59−70262号に記載
のように、接点端子を外部環境から保護するために摺動
可能なカバーを設けるようになっていた。Conventional IC cards are provided with a slidable cover to protect the contact terminals from the external environment, as described in Japanese Utility Model Application Publication No. 70262/1983.
この方法は接点の汚れや機械的破損に対しては効果があ
るものの、永久的な破壊となる半導体集積回路の静電破
壊に対しては効果が無かった。Although this method was effective against soiled contacts and mechanical damage, it was not effective against electrostatic damage to semiconductor integrated circuits, which would result in permanent damage.
本発明の目的は、上記の欠点を無くし、ICカード中に
含んだ半導体集積回路の静電破壊を防止することのでき
る外部装置との電気的接続方式を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an electrical connection method with an external device that eliminates the above-mentioned drawbacks and can prevent electrostatic damage to semiconductor integrated circuits contained in an IC card.
半導体集積回路の静電気による破壊は、上部との接続端
子がオープンの状態で、静電気の混入により各端子が異
なった電位状態になり、その各端子間の電位差が、接合
破壊強度あるいはゲート破壊強度などを上まわった場合
に起こる永久破壊である。従って、この破壊を防止する
ためには、外部装置との接続時以外は全ての接続端子を
同電位に保持すればよい。Destruction of semiconductor integrated circuits due to static electricity occurs when the connection terminals connected to the top are open, and each terminal has a different potential due to the introduction of static electricity, and the potential difference between the terminals causes a breakdown such as junction breakdown strength or gate breakdown strength. Permanent destruction occurs when the Therefore, in order to prevent this destruction, all connection terminals may be held at the same potential except when connected to an external device.
又、他の手段としては、半導体集積回路の給電端子にコ
ンデンサを接続することでも効果が得られる。Moreover, as another means, an effect can be obtained by connecting a capacitor to the power supply terminal of the semiconductor integrated circuit.
以下、本発明の一実施例を第1図〜第4図により説明す
る。第1図は、本実施例で説明するICカード1の外観
図であり、その中に半導体集積回路を埋め込み外部装置
との電気的接続端部7(78〜7c)を設けている。An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is an external view of the IC card 1 described in this embodiment, in which a semiconductor integrated circuit is embedded and electrical connection ends 7 (78 to 7c) for connection with external devices are provided.
次に第2図〜第4図により本実施例の構成および動作を
説明する。第2図は、第1図におけるX−X′の断面構
造を示している。第2図において半導体集積回路2は、
ICカード基板3上に設けた凹部に収納され、外部装置
との接続端子5に配線4を介して結線し、上記の半導体
集積回路2と配線4は保護膜6で被う。以上の保!!膜
6および接続端子5および基板3は外部装置との接触点
7だけを残し、全体をICカードの上面カバー8で被う
と共に、本発明である端子間を短絡するための短絡用金
属9を設ける。なお外部端子との接続端子5に弾性のあ
る金属を用い、更に外部端子との接触点7の下方には空
洞を設ける。Next, the configuration and operation of this embodiment will be explained with reference to FIGS. 2 to 4. FIG. 2 shows a cross-sectional structure taken along line XX' in FIG. In FIG. 2, the semiconductor integrated circuit 2 is
It is housed in a recess provided on the IC card board 3 and connected to a connection terminal 5 with an external device via wiring 4, and the semiconductor integrated circuit 2 and wiring 4 are covered with a protective film 6. More protection! ! The membrane 6, the connection terminals 5, and the substrate 3 are covered with an IC card top cover 8, leaving only the contact point 7 with the external device, and a shorting metal 9 for shorting between the terminals according to the present invention. establish. Note that the connection terminal 5 with the external terminal is made of elastic metal, and a cavity is provided below the contact point 7 with the external terminal.
第3図は第2図におけるA−A’およびB−B’の断面
図を示す。本実施例では7a〜7cの3端子を同時に短
絡する構成で示した。FIG. 3 shows a cross-sectional view taken along lines AA' and BB' in FIG. In this embodiment, three terminals 7a to 7c are short-circuited at the same time.
第4図は第2図における接触点7付近の拡大図であり、
第4図(a)は外部装置の接触針10が未接触の状態で
あり、第3図(b)のB−B’断面で示した78〜7c
の各端子は、短絡用金属9により全て同電位になる。FIG. 4 is an enlarged view of the vicinity of contact point 7 in FIG.
FIG. 4(a) shows a state in which the contact needle 10 of the external device is not in contact, and 78 to 7c shown in the BB' cross section of FIG. 3(b).
The respective terminals are all at the same potential due to the shorting metal 9.
第4図(b)は外部装置の接触針10が接触点7に接触
し、接触点7をおし下げることで、外部接続端子5と短
絡用金属9は離れ、ICカード中に含む半導体集積回路
と外部装置との電気的接続が成される。FIG. 4(b) shows that when the contact needle 10 of the external device contacts the contact point 7 and pushes down the contact point 7, the external connection terminal 5 and the shorting metal 9 are separated, and the semiconductor integrated circuit included in the IC card is removed. An electrical connection is made between the circuit and an external device.
本実施例によれば、外部装置との接触が行なわれていな
い場合には、半導体集積回路の全端子が常に同電位に保
たれ静電気による半導体集積回路の破壊を防止すること
ができる。According to this embodiment, when there is no contact with an external device, all terminals of the semiconductor integrated circuit are always kept at the same potential, making it possible to prevent destruction of the semiconductor integrated circuit due to static electricity.
第5図は、上記の実施例で述べた効果を維持し、かつ、
接触点7の下面を開放にすることで、外部装置との接触
点を7および7′の両面で取ることができる第2の実施
例である。第2の実施例では、電気的接点の両面を開放
にすることにより接点の洗浄が容易になるという効果が
ある。FIG. 5 maintains the effects described in the above embodiment, and
This is a second embodiment in which by opening the lower surface of the contact point 7, the contact points with the external device can be obtained at both sides of the contact point 7 and 7'. The second embodiment has the effect that cleaning of the contacts is facilitated by leaving both sides of the electrical contacts open.
次に、本発明の他の実施例を第6図〜第8図により説明
する。Next, another embodiment of the present invention will be described with reference to FIGS. 6 to 8.
第6図は1本実施例で述べるICカード100の外観図
であり、カード100の中には半導体集積回路が内蔵さ
れ、その半導体集積回路と外部データ送信装置と電気的
な接続を行なうための接続端子11 (lla〜11e
)を有している。FIG. 6 is an external view of the IC card 100 described in this embodiment. The card 100 has a built-in semiconductor integrated circuit, and a circuit board for electrically connecting the semiconductor integrated circuit to an external data transmitting device. Connection terminal 11 (lla~11e
)have.
第゛7図は第6図のICカードのx−x’の断面構造で
ある。第7図において、半導体集積回路12は、カード
基板13の凹部14に収納され、外部装置との電気的接
点11に配線15′および16を介して接続する。上記
の半導体集積回路12および配線16は機械的強度と耐
湿性を与えるために保護膜17で被う。FIG. 7 is a cross-sectional structure of the IC card shown in FIG. 6 taken along line xx'. In FIG. 7, a semiconductor integrated circuit 12 is housed in a recess 14 of a card board 13, and is connected to an electrical contact 11 with an external device via wirings 15' and 16. The semiconductor integrated circuit 12 and wiring 16 described above are covered with a protective film 17 to provide mechanical strength and moisture resistance.
次に第7図および第8図により、本発明に係る構成につ
いて説明する。第8図はICカードの各層構成を示し、
(D)はコンデンサの一方の電極となる金属層15であ
り、本実施例では第7図に示した半導体集積回路12と
外部データ送信装置を電気的に結合する配線15′と同
一の層で構成している。前記の金属層15の上部は、誘
電体膜18を介して更にその上部にコンデンサの他方の
電極となる金属層19を積層する。前記の金属層15お
よび19を、別々の給電端子に接続することで、第9図
に示すような回路構成となり、給電端子11aと給電端
子11bの間に、上記のコンデンサ22を配線すること
ができる。この時の静電容量は次のように求まる。第8
図(D)のコンデンサの電極となる金属層15の面積を
S、第8図(C)の誘電体膜18の厚さをQ、18のI
!率をεとすると、静電容量Cは
C= i・−[F]
になる。Next, the configuration according to the present invention will be explained with reference to FIGS. 7 and 8. Figure 8 shows the structure of each layer of the IC card.
(D) is a metal layer 15 that becomes one electrode of the capacitor, and in this embodiment, it is the same layer as the wiring 15' that electrically couples the semiconductor integrated circuit 12 and the external data transmitting device shown in FIG. It consists of A metal layer 19 that will become the other electrode of the capacitor is further laminated on top of the metal layer 15 with a dielectric film 18 interposed therebetween. By connecting the metal layers 15 and 19 to separate power supply terminals, a circuit configuration as shown in FIG. 9 is obtained, and the capacitor 22 described above can be wired between the power supply terminals 11a and 11b. can. The capacitance at this time is determined as follows. 8th
The area of the metal layer 15 that becomes the electrode of the capacitor in FIG. 8(D) is S, the thickness of the dielectric film 18 in FIG. 8(C) is Q, and the I of 18 is
! When the rate is ε, the capacitance C becomes C=i·−[F].
以上説明したコンデンサを第8図の接続端子11の上部
だけを開放にするための窓21(21a〜21e)を設
けた保護膜20で被うことでICカードを構成する。以
上説明した本実施例によれな、以下に述べる効果がある
。第1の効果は給電端子にコンデンサーを結合すること
で、給電端子に給電中は、給電端子に混入するノイズを
吸収し、半導体集積回路に安定な電圧を供給することが
できる。第2の効果は、給電端子が開放状態の時に。An IC card is constructed by covering the capacitor described above with a protective film 20 provided with a window 21 (21a to 21e) for opening only the upper part of the connection terminal 11 shown in FIG. This embodiment described above has the following effects. The first effect is that by coupling a capacitor to the power supply terminal, while power is being supplied to the power supply terminal, noise that enters the power supply terminal can be absorbed and a stable voltage can be supplied to the semiconductor integrated circuit. The second effect occurs when the power supply terminal is open.
給電端子から混入する静電気による半導体集積回路の破
壊強度を強化することができる。第3の効果は、半導体
集積回路の上部を金属層で被覆することができ、湿気の
混入を防止することができる6更に金属層に機械的な強
度を持たせることで、ICカードの機械的破損を防止す
ることができる。It is possible to strengthen the strength of the semiconductor integrated circuit to break down due to static electricity that enters from the power supply terminal. The third effect is that the upper part of the semiconductor integrated circuit can be covered with a metal layer, which prevents moisture from entering.6 Furthermore, by giving the metal layer mechanical strength, the mechanical strength of the IC card Damage can be prevented.
第3の効果は、半導体集積回路として内部昇圧回路をも
つ電気的に消去および書込みのできるEEFROM(E
lectrically Erasabla an
d ProgrammableRead 0nly
Men+ory)を含む場合は、停電時の誤消去および
誤書込みを防止するためのバックアップ・コンデンサと
して使用することができる6以上の実施例および効果は
給電端子にコンデンサを結合した例で述べたが、前記コ
ンデンサを、その他の端子(例えば入出力端子)に結合
して使用することも可能である。The third effect is that EEFROM (EEFROM), which has an internal booster circuit and can be electrically erased and written, is a semiconductor integrated circuit.
Electrically Erasabla an
d ProgrammableRead 0nly
(Men+ory), it can be used as a backup capacitor to prevent erroneous erasing and erroneous writing during power outages.The above six embodiments and effects have been described using the example of connecting a capacitor to the power supply terminal. It is also possible to use the capacitor coupled to other terminals (for example, input/output terminals).
本発明の第1の手段によれば、ICカードに含んだ半導
体集積回路の外部装置との接続端子は、未使用状態では
全て同電位になり、接続端子に静電気などによる高電圧
が印加された場合でも、半導体集積回路の破壊を防止す
る効果がある。According to the first means of the present invention, the connection terminals of the semiconductor integrated circuit included in the IC card with external devices are all at the same potential when not in use, and high voltage due to static electricity or the like is applied to the connection terminals. Even in such cases, it has the effect of preventing damage to the semiconductor integrated circuit.
本発明の第2の手段によれば、給電端子にコンデンサを
結線したICカードを得ることができるので、給電中の
電圧安定化と、給電端子開放時の静電破壊強度向上の効
果がある。According to the second means of the present invention, it is possible to obtain an IC card in which a capacitor is connected to the power supply terminal, which has the effect of stabilizing the voltage during power supply and improving the electrostatic breakdown strength when the power supply terminal is opened.
第1図は本発明の実施例のICカードの外観図、第2図
は第1図のx−x’線の断面図、第3図は第2図のA−
A’およびB−B’線の断面図、第4図は第2図の7付
近の拡大図、第5図は第2の実施例を説明する第1図の
x−x’線の断面図、第6図は本発明の他の実施例のI
Cカードの外観図、第7図は第6図のx−x’線の断面
図、第8図はICカードの各層構成図、第9図は本発明
の実施例の回線図である。
3.13・・・ICカード基板、2.12・・・半導体
集積回路、4.5・・・接続配線、7,11・・・接触
端子。
8・・・保護カバー、9・・・短絡用金属、10・・・
外部装置の接触針、15.19・・・電極板、18・・
・誘電体/−ゝ
、゛。
41図
A 冨2図
第3図
不 、! 図
茗5図
冨 〆 図
蔓 7 図
■3 図
ZρFIG. 1 is an external view of an IC card according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line xx' in FIG. 1, and FIG.
4 is an enlarged view of the vicinity of 7 in FIG. 2, and FIG. 5 is a sectional view taken along line xx' in FIG. 1, explaining the second embodiment. , FIG. 6 shows I of another embodiment of the present invention.
FIG. 7 is a cross-sectional view taken along line xx' in FIG. 6, FIG. 8 is a diagram showing the structure of each layer of the IC card, and FIG. 9 is a circuit diagram of an embodiment of the present invention. 3.13...IC card board, 2.12...semiconductor integrated circuit, 4.5...connection wiring, 7,11...contact terminal. 8...Protective cover, 9...Short circuit metal, 10...
Contact needle of external device, 15.19... Electrode plate, 18...
・Dielectric material/−ゝ、゛. Figure 41 A Figure 2 Figure 3 Not ,! Figure 5 Figure 5 Figure vine 7 Figure■3 Figure Zρ
Claims (1)
的に接続するための複数の接続端子を有するカードにお
いて、そのカード中に、前記の接続端子間を短絡する導
電性材料、又はコンデンサを設けたことを特徴とするI
Cカード。 2、特許請求の範囲第1項記載のICカードにおいて、
外部装置と接触し、電気的な接点となる端子の、接点と
反対側の面の周囲を空洞または開放にしたことを特徴と
するICカード。[Claims] 1. In a card including an IC and having a plurality of connection terminals for electrically connecting the IC and an external data transmission device, there is a conductive device in the card that short-circuits the connection terminals. I characterized by being provided with a magnetic material or a capacitor.
C card. 2. In the IC card according to claim 1,
An IC card characterized in that a terminal that contacts an external device and serves as an electrical contact has a hollow or open area around the surface opposite to the contact.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60095431A JPS61254398A (en) | 1985-05-07 | 1985-05-07 | IC card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60095431A JPS61254398A (en) | 1985-05-07 | 1985-05-07 | IC card |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61254398A true JPS61254398A (en) | 1986-11-12 |
Family
ID=14137505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60095431A Pending JPS61254398A (en) | 1985-05-07 | 1985-05-07 | IC card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61254398A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01186392A (en) * | 1988-01-21 | 1989-07-25 | Nec Corp | Information card |
-
1985
- 1985-05-07 JP JP60095431A patent/JPS61254398A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01186392A (en) * | 1988-01-21 | 1989-07-25 | Nec Corp | Information card |
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