JPS61253867A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to basic devices of large-capacity integrated circuits (VLSI), and particularly to MOS devices that require high breakdown voltage.

[Background of the invention]

As the miniaturization of MOS devices progresses, the elements are required to have higher breakdown voltages in order to ensure their reliability. The LDD (lightly topple drain) shown in Figure 1 was devised for that purpose.
It is a device called tly Doped Drain. Such a structure is disclosed in Japanese Unexamined Patent Publication No. 13177/1983. It has a structure in which a low concentration impurity diffusion layer 3 is provided adjacent to the high concentration impurity diffusion layer source/drain 2 in the channel direction. This low concentration impurity layer 3 serves as a resistor, lowers the voltage applied to the actual device, and increases the withstand voltage. However, as described above, this low concentration diffusion layer 3 is a component of resistance, so while it increases the withstand voltage, it lowers the transfer characteristics. Even worse,
During operation, electrons (electrons in the case of an N channel, holes in the case of a P channel) are injected and captured into the sidewall insulating film 11 adjacent to the upper part of the low concentration diffusion layer 3 (31 in FIG. 1), and the electrons are The low concentration diffusion layer 3 is made into a depletion layer (pinch-off) to further increase the resistance of this layer. Therefore, the transfer characteristics will further deteriorate. This problem poses a major problem in terms of reliability of LDD transistors.

[Purpose of the invention]

The purpose of this invention is to overcome the above problems.

The object of the present invention is to provide a device structure that makes injection of electrons (or holes) less likely to occur.

[Summary of the invention]

In order to suppress the electron (or hole) injection described above, it is necessary to reduce the electric field within the low concentration impurity layer 3 and to bring the peak position of the electric field where injection is most likely to occur inside the substrate. Since the former method has a trade-off relationship with the transfer characteristics, this invention uses the latter concept and provides a device structure that realizes it.

[Embodiments of the invention]

Example 1 FIG. 2(a) is a sectional view showing the element structure of this example.

As shown in FIG. 3(a), a gate oxide film 4 is grown to a thickness of 20 nm on a 100 Ω·G p-type Si substrate 1 having a channel implantation 50.

Thereon, a conductor 6 made of polycrystalline Si (metal silicide, pure metal - for example, W or Mo may be used) is deposited in rows of 300 nm by the CVD method. On top of that, a photosensitive resin film 5
2 is applied, a pattern is formed by photolithography, and the underlying laminated films 6 and 4 are etched to form a gate portion. In this etching, the photosensitive resin film is removed by a zero-order process using μ-wave plasma, and the entire wafer is oxidized. The oxide film thickness 51 at this time was approximately 15 nm. Next, from above, sources and drains with low concentration and having a concentration peak on the substrate were formed as shown diagrammatically by the arrows in FIG. 3(b). To form, 10
Phosphorus (P) ions were implanted at 0 KaV. The profile of the low impurity concentration formed at that time is shown in FIG. 5(b).The peak of this impurity concentration is about 0.1
It was at a distance of μm. Incidentally, the concentration profile 82 of the source/drain of the conventional structure is shown in FIG. 5(a).

Next, the whole wafer is CVD-8i 0.11 or PS
Cover with G (phosphosilicate glass) 300 nm and RIE it.
(Reactive ion etching: Reacti
ve ion etching) so as to leave SiO□ on the gate sidewalls (FIG. 3(C)). At this time, S i O remained on the side wall.

The width 90 of was 0.3 μm. Then again.

The entire wafer is oxidized to form an oxide film 53. In this state, As (arsenic) 61 ions were implanted at 80 K e V and 5 X to form sources and drains in high concentration regions.
The arsenic profile (81) at that time is shown in FIG. 5(b).

After this, phosphosilicate glass 5 is deposited to a thickness of about 400 nm over the entire wafer as a protective film, contact holes are made for contacting the source and drain (Figure 3 (a)), and then aluminum is deposited for wiring. Then, aluminum wiring is formed in a predetermined shape. The subsequent steps are standard processes and will therefore be omitted.

Example 2 An example for realizing the structure shown in FIG. 2(b) (the substrate surface of the high concentration source and drain is silicided) will be described.

After carrying out the process shown in FIG. 3(b), the thin oxide film 53 is removed, and then the source and drain are silicided (FIG. 4(a)).
Deposit 0 on the entire surface of the wafer.

Then argon (Ar) or nitrogen (N2) at 600'C
Heat treatment is performed in an atmosphere for 20 to 30 minutes.

By this treatment, titanium silicide TiSi 241 is formed at the portion where the surface of the high concentration diffusion layer or the silicon surface of the gate (in the case of polysilicon) is in contact with titanium metal. The film thickness at this time was approximately 0.15 μm.

Next, only the titanium metal is removed by selective etching, and the process proceeds to the step shown in FIG. 3(e). The subsequent steps are the same as in Example 1.

Embodiment 3 In order to realize the structure shown in FIG. 2(c) (three-layer source/drain structure), boron ions are implanted after the step shown in FIG. 3(b) (FIG. 4(b)). The acceleration voltage at that time is 6
It was 0 K eV. The obtained impurity profile 84 is shown in FIG. 5(c).

The subsequent steps are the same as in Example 1.

It is clear that these three types of device structures are not limited to n-channel devices, but can also be applied to p-channel devices.

〔Effect of the invention〕

As shown in FIG. 6, in a MOS transistor with effective channel length Laff = 1 μm and gate oxide film thickness Tox = 20 nm, the transistor 91 according to the present invention exhibits higher DC stress resistance than the LDD with the conventional structure 90. I understand that. FIG. 6 shows the DC stress application time on the horizontal axis and the deterioration of the transfer conductance on the vertical axis. According to this invention, the amount of charge trapped in the gate sidewall insulating film 11 is reduced, and the absolute value of the deterioration of the transfer conductance is significantly reduced.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional LDD structure, Figure 2 (a), (
b) and (c) are sectional views of elements according to embodiments of the present invention, FIGS. 3 and 4 are flowcharts of the process for producing the structures of the above-mentioned embodiments of the present invention, and FIG. Diffusion layer impurity concentration profile of the device in the example, FIG. 6 is a comparison graph of transfer conductance deterioration in the device of the present invention and the conventional device. 1... Semiconductor substrate, 2... High concentration diffusion layer, 3...
Low concentration diffusion layer, 4... Gate insulating film, 5... Protective film, 6... Gate electrode (polysilicon, pure metal, silicide), 7... Wiring, 11... Gate side wall insulating film ,
41... Silicide or metal, 42... Diffusion layer, 5
0...Channel impurity, 51°"° oxide film or insulating film, 60-"° ion implantation, 61...Ion implantation, 62...Ion implantation, 81-84...Each impurity profile number l Country strike 9!

Claims (1)

[Claims] 1. In an insulation effect transistor having a source and a drain formed of two types of impurity concentration layers fabricated on a semiconductor substrate, the peak concentration of at least one of the low concentration impurity layers of the source and drain is A semiconductor device characterized by being embedded within a semiconductor substrate rather than on its surface. 2. The semiconductor device according to item 1, wherein the substrate surface of the high concentration region of the source and drain is made of silicide, pure metal, or polysilicon. 3. The semiconductor device according to item 1, wherein there are different types of impurity layers on the substrate surface side of the low concentration impurity layer (source or drain) of the semiconductor device.