JPS61251072A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PURPOSE:To control easily work function of a gate electrode, by introducing conductivity-deciding impurities into a portion of the gate electrode where high melting-point metal silicide containing a very large ratio of Si ingredient is used. CONSTITUTION:On a portion of a semiconductor substrate 1, SiO2 2 is formed, and on the other portion a thin gate SiO2 3 is formed. On the SiO2 3, excess MoSix 4 (x=3-20) is formed, TiSix 5 (x=2-2.5) is then formed, and ions 6 such as P<+>, As<+>, B<+>, BF2<+> are implanted so as to attain a desired work function. Next, an amorphous film such as SiN 7 is deposited. After the SiN 7, TiSix 5 and MoSix 4 are removed and a gate electrode is formed, implantation of P<+> ions 8 forms a low-concentration diffusion region 9 and CVD forms an SiO2 film 10. After the film 10 is removed with a portion being left on the side wall of the gate electrode, implantation of As<+> ions 11 and heat treatment are done to make source-drain 12. The SiN 7 prevents the implanted ions from invading thus to vary the work function. After the implantation, SiO2 10 is grown, a contact window is opened, and an electrode 13 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, particularly its low resistance gate electrode and wiring.

(Prior Art) In conventional semiconductor devices, particularly MO3 type semiconductor integrated circuit devices, molybdenum, molybdenum,
Refractory metals such as tungsten, or MoSi,
, VSi, , TaSi, , TiSi, and other high-melting point metal silicides are used as materials for gate electrodes and wiring. The above-mentioned high melting point metal silicide is different from metal in terms of oxidation resistance and chemical resistance.
It is a low resistance material with excellent compatibility with gate processes.

FIG. 4 shows the structure of a gate electrode using a high melting point metal silicide film.

FIG. 4(a) is a cross-sectional view of an MO5 type transistor,
21 is a semiconductor substrate, 22 is SiO□, 23 is a gate 5i
02, and 24 is a compositionally uniform monolayer film made of a compound satisfying stoichiometry, such as Mo5iO, or with a slight excess of silicon.

FIG. 4(b) is a cross-sectional view of the same MO3 type transistor, and 25 is a PolySi film.

As a silicide, a compound that satisfies the stoichiometry has a low resistance, so conventionally it has been used without changing the component ratio much from the stoichiometry.

References: (1) T., Mochizuki et.
al, Japanese.

Journal of Appl, Phys, 17
(1978) 5upplesent17-1. p3
7. (2) H, J, Ge1pel JRat
al, IEEE Trans, Electron D
evices, HD-271417 (1980).

(Problems to be Solved by the Invention) Conventional electrode grooves are replaced by MOs with a channel length of 1 μm to several μm.
Although it was possible to design a type 5 transistor to obtain optimal electrical characteristics, when trying to design a transistor with a submicron channel length in order to manufacture a semiconductor device with a higher degree of integration. In this case, it becomes extremely difficult to freely obtain desired electrical characteristics. For example, as shown in FIG. 4(b), the transistor is an n-channel transistor, the substrate is p-type (100), and the impurity concentration is 1×.
10"/a#, Po1ySi film is n-type with high concentration of phosphorus diffused, gate oxide film is 10μm to prevent short channel effect of threshold voltage, +0
．． In order to obtain a threshold voltage of 6V, an n-type Po1yS
Since the work function of the i film is low, boron is added at 2 to 5 x 10"/cd in the region directly under the gate oxide film that will become the channel.
This implantation dose is about one order of magnitude larger than that of a transistor with a large channel length.
The high concentration of boron implanted reduces the mobility of the channel, resulting in a reduction in operating speed. Also, P
When a high concentration of boron is added to an oly Si film to make it p-type, the work function of the poly Si film increases by about 1v, making it higher, so n-type impurities must be implanted into the channel region.

Only so-called embedded channels will be possible.

As mentioned above, restrictions are added to the setting of characteristics.

This is because the work relationship of PolySi containing impurities at a high concentration is fixed.

On the other hand, in the single-layer silicide gate transistor shown in FIG. 4(a), the work function is an appropriate value, but the
A gate insulating film as thin as 10 .mu.m has the disadvantage that its dielectric strength easily deteriorates when subjected to heat treatment at .degree.

The purpose of the present invention is to eliminate the conventional drawbacks and reduce the work function to about 1.
An object of the present invention is to provide a semiconductor device having a gate structure that can be arbitrarily set with a width of v, does not cause deterioration of gate dielectric breakdown voltage, and facilitates optimal design of transistor characteristics.

(Means for Solving the Problems) The semiconductor device of the present invention provides an insulating film on an insulating film formed on a semiconductor substrate. containing less S than the Si content at the contact interface.
By including i, the resistance becomes low, and the electrode and wiring are made of a single layer or multilayer high melting point metal silicide film.

Further, the metal silicide film contains a desired amount of conductivity type determining impurities.

Further, a step of depositing a first high melting point metal silicide film containing St such that the work function is almost equal to that of polycrystalline Si on the insulating film formed on the semiconductor substrate; a step of laminating a second high melting point metal silicide film having a lower Si content and lower resistance than the first high melting point metal silicide film; and sequentially depositing the first and second high melting point metal silicide films. This includes a step of selectively removing the material to form electrodes and wiring.

Furthermore, on the insulating film formed on the semiconductor substrate, at least at the contact interface with the insulating film, a surface with a high Si concentration that allows the work function to be almost equal to that of polycrystalline Si has a Si concentration lower than the Si concentration at the contact interface. The method includes a step of depositing a single layer of a high melting point metal silicide film that has a high resistance and a low resistance, and a step of selectively removing this high melting point metal silicide film to form electrodes and wiring.

(for production) The effects of the means of the present invention are as follows.

If the Si content in the high melting point metal silicide is made extremely high, its work function can be made almost equal to that of PolySi.

In Figure 2, a gate electrode is made of molybdenum silicide into which phosphorus, which is a conductivity type determining impurity, is introduced at about 10"/ci?, as shown by the solid line, or boron is introduced at about 101" to 10"/d, as shown by the broken line. In a MOS capacitor, its flat band voltage (which can be considered equivalent to the work function)
This is an experimental example showing the relationship between Mo and Si component ratio Mo/Si.
When it is higher than 5iO□ (Mo/Si mi 0.5), (N
o/Si=O to 0.3) The flat band voltage of molybdenum silicide is shown to be approximately equal to the value for the Po1ySi gate.

Furthermore, as is well known, the flat band voltage of the Poly Si gate can be reduced to about 1 in principle if the type and concentration of impurities introduced into the Poly Si are appropriately selected.
V changes arbitrarily within the range of v (approximately -1 in the example shown in Figure 2).
. Furthermore, the silicide portion with a low Si concentration existing in the upper layer of the silicide contributes to lowering the resistance of the electrode. Furthermore, the high-melting-point metal silicide with a high Si concentration in the lower layer has properties similar to that of PolySi, which does not deteriorate the dielectric breakdown voltage of the underlying gate oxide film even when subjected to high-temperature heat treatment necessary for semiconductor device manufacturing. In comparison, the dielectric strength can be significantly improved.

(Example) An example of the present invention will be described based on FIGS. 1 to 3.

Figure 1 shows an n-channel MO using the manufacturing method of the present invention.
FIG. 5 is a process cross-sectional view of a type 5 transistor.

In FIG. 1(a), a portion of the semiconductor substrate 1 has a thickness of approximately 6 mm.
00 μm of Sin,2 is embedded, and a 10 μm thick gate 5in23 is formed in the other part.

Next, as shown in FIG. 1(b), a Si-excess silicide layer (MoSi (4 (x = 3 to 20)) with a thickness of 10 μm to 10 μm is deposited on the gate SiO□s by sputtering or CVD. 150 μm, and then the silicide layer, TiSix5 (x = 2 to 2.
5) is formed to a thickness of about 200 μm, and P", As", B
”, BF2+, etc. ions 6 are implanted into Ti5ixS so as to obtain a desired work function.

Next, as shown in FIG. 1(C), silicon nitride SiN
An amorphous film such as No. 7 is deposited on the TiSix 5 by CVD or sputtering.

Next, as shown in FIG. 1(d), the deposited film, SiN
7, TiSix5. MoSix4 was sequentially and selectively removed by anisotropic dry etching to form a gate electrode.

・P+ ions 8 are implanted at 1012 to 1013/al to form a low concentration diffusion region 9, and further ICCVD Sin
, the film 10 is formed to a thickness of 100 μm to 150 μm.

Next, as shown in FIG. 1(e), CVD 5in2 film 1
When 0 is removed by an anisotropic etching method, a part remains on the side wall of the gate electrode as a so-called sidewall, and As+ ions 11 are injected at 80 keV 4 XIO"/a onto this.
I? and heat treated at 850°C to 900°C,
Create source/drain 12.

Here, as shown in FIG. 1(f), in SiN 7, the implanted ions shown in FIG. 1(d) and FIG. 1(e) directly enter the inside of the gate electrode and change the work function. It has the role of effectively preventing this from happening.

After source/drain implantation, C
VD Sin, 10 is grown, a contact window is opened, and an electrode 13 whose main component is aluminum is formed.

In the above embodiment, the lower silicide layer 4 is NoSix
However, any material can be used as long as it can withstand heat treatment at around 900°C as in step (e) and does not deteriorate the dielectric strength of the gate Sin, 3, and WSi! .

Examples include T a S x x. Moreover, as the upper silicide layer, in addition to TiSi, osix, WSix
, TaSix t VSi, , HfSix tN
Refractory metal silicides such as bSi can also be used.

Furthermore, the number of implanted ions used for work function control need not be one type, and a combination of multiple types may be implanted.

In the second embodiment, the lower silicide layer 4 in FIG.
．． Alternatively, instead of a composite film gate electrode of the upper and lower silicide layers 5 and 4, as shown in FIG. A silicide film with a low Si concentration profile that provides low resistance is used.

Even if such a silicide film is used, the same effects as in the first embodiment can be obtained.

(Effects of the Invention) According to the present invention, the work function of the gate electrode can be adjusted by a simple method of using high-melting metal silicide with a very large Si content as a part of the gate electrode and introducing conductivity type determining impurities into it. It can be easily controlled, and does not cause deterioration in gate insulating film breakdown voltage unlike conventional single-layer silicide gates. These advantages increase the degree of freedom in optimal design of fine transistors, particularly those with a channel length of 1 μm or less, and are therefore extremely effective in practice.

[Brief explanation of the drawing]

FIG. 1 <a> to f) are cross-sectional views showing the steps of the semiconductor device manufacturing method according to the first embodiment of the present invention, and FIG. 2 is the dependence of the flat band voltage on the Mo/Si ratio in a molybdenum silicide gate MOS capacitor. Figure 3 is a Si concentration profile diagram in a silicide electrode in the second embodiment of the present invention, and Figures 4 (a) and (b) are cross-sectional views showing the gate electrode structure of a conventional semiconductor device. It is. 1.21...Semiconductor substrate, 2,22...SiO□,
3, 23-...geone SiO,,4-MoSi,,
6- Ions such as P'', As'', B'', BF,'',
7-=SiN, 8...P'' ion, 9...
・Low concentration diffusion region, 10...-CVD5iO, film, 1
1- As” ion, 12...source/drain, 1
3... Electrode, 24... Single layer film, 25- Po1
y Si film. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 1 Funeral Figure 2 Figure 3 Figure 4 (a) 2m (b) 2m

Claims (4)

[Claims] (1) On the insulating film formed on the semiconductor substrate, at least the contact interface with the insulating film contains enough Si to have a work function almost equal to that of polycrystalline Si, and the Si content on the surface is less than the Si content at the contact interface. 1. A semiconductor device characterized by having low resistance due to the inclusion of Si and comprising electrodes and wiring made of a single layer or multilayer high melting point metal silicide film. (2) The semiconductor device according to claim (1), wherein the metal silicide film contains a desired amount of conductivity type determining impurity. (3) depositing a first high melting point metal silicide film containing enough Si to have a work function almost equal to that of polycrystalline Si on an insulating film formed on a semiconductor substrate; a step of laminating a second high melting point metal silicide film having a lower Si content and lower resistance than the first high melting point metal silicide film on the silicide film; and a step of laminating the first and second high melting point metal silicide films. 1. A method of manufacturing a semiconductor device, comprising a step of sequentially and selectively removing electrodes and wiring. (4) On the insulating film formed on the semiconductor substrate, at least at the contact interface with the insulating film, the work function is approximately equal to that of polycrystalline Si, and the Si concentration is as high as possible, and at the surface, the Si concentration is lower than the Si concentration at the contact interface. The method is characterized by comprising a step of depositing a single layer of high melting point metal silicide film having a Si concentration and low resistance, and a step of selectively removing the high melting point metal silicide film to form electrodes and wiring. A method for manufacturing a semiconductor device according to claim (3).