JPS61246790A - Address control system for frame memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scrolling screen related to an image display device.
This invention relates to an address control system for system memory.

[Conventional technology]

A conventional device of this type is shown in FIG. In the figure, 11 is a data input section that takes in data and classifies it into 1 display, drawing address, and drawing data, and sends the data to each control section, 12 is a display mode control section that holds scroll 0N10FF, and 13 is an input section. Convert the address to the corresponding frame-memory address and store the frame.
Also, when scrolling, a drawing address control section calculates a scroll offset value and outputs it to the CRT control section. 14 is a drawing data control unit which converts the input data into a drawing pattern KK and writes it into the frame memory; 16
Reference numeral 17 is a CRT control unit that sequentially reads the frame memory and displays the CRT. Reference numeral 17 is a frame memory that stores screen information and has a capacity for two screens for scrolling. 1
Reference numeral 8 is a C-T for displaying a screen.

The mK operation will be explained. First, the input data (
1 byte] is classified by the data input unit 11 and delivered to one of the display mode control unit 12, drawing address control unit 13, and drawing data control unit 14. Then, the display mode control section 12 detects scroll ON or OFF based on the input data, holds it, and sends a control signal to the drawing address control section 13. The drawing address control unit 13 converts the input data (address) into a corresponding frame memory address (corresponding to -) and selects the frame memory 17. Also, when scrolling is ON, the scroll offset value (OR, The T control unit calculates the start address command () when reading the frame memory, and
Send it to the RT control unit. The drawing data control unit 14 converts the input data into a drawing pattern and writes it into a selected portion of the frame memory 17. CRT control unit 1
6 sequentially reads out the frame memory 17 according to the scroll offset value and outputs it to the CRT 18 together with a synchronizing signal.

Next, using CAPTAIN PLP as an example, the necessity of having two frame memories will be explained.

CAPTAIN PLP pattern data is displayed fixedly,
Or, regardless of the scroll display, the J opcode and address are transferred every four lines as shown in Figure 7. P.L.
The address of the standard screen on P is 192. The lowest end is 1. When scrolling, the data of the currently specified address is displayed at the bottom of the screen, and when the data of the address below it comes,
The data at the address above will increase accordingly. Therefore, in the example of Figure 7, when ID data is received,
The ID is displayed on lines 1 to 4 from the bottom of the screen, and when 2D data is processed, 2D is displayed on lines 1 to 4 from the bottom of the screen, and the ID is raised to lines 5 to 8. When the drawing at 48D in FIG. 7 is completed, the ID data (address 192) is displayed at the top of the screen.

By the way, if we consider the case where we continue to display scroll data after the end of one screen display, the address at the beginning of the next screen is also 192, so considering the continuity with the previous screen, the address The address displayed under 1 will be 192. Therefore, if such an address system is to be implemented on the frame memory 17, it must be the size of two frames as shown in FIG. 8, and the structure must be such that the end and start of the two frames are continuous.

As an example, an example of displaying detailed crawl data using this method is shown in FIG. In the figure, the shaded area indicates CR in the frame.
The part displayed at T18 is shown. (a) is the seventh
In the example shown in the figure, the ID data is being drawn, (b) is the I
(C) is a state where drawing of 2D data is completed. (d) is a state where drawing of 48D data is completed. (e) is a state where drawing of data of 48D is completed. (e) is a state where drawing of data of 48D is completed. 192) Indicates a state in which IDA drawing has been completed.

[Problem that the invention seeks to solve]

Since the conventional frame memory address control system was configured as described above, the drawing address control unit 13 and the frame memory 17 were directly connected, so image data was received one after another following the address, and images were sequentially generated. In order to scroll and display the data, it was necessary to have two sides of the frame memory 17 each having the size of one specified screen.

Furthermore, the 1 drawing address control section 13 controls the CRT@J leg section 1.
6 needs to perform address control for reading out the frame memory 17, resulting in problems such as complicated processing.

This invention was made in order to eliminate the problems of the conventional ones as described above, and by providing a frame memory address control section before the frame memory and CRT control section, it is possible to control the input data format and the frame memory. The purpose is to increase the degree of freedom in configuration and enable continuous scrolling display without having frame memory for two screens.

[Means for solving problems]

The frame memory address control method according to the present invention converts the drawing address on the data writing side into the real address of the frame memory by detecting the drawing address of the screen division in the display state of the CRT screen. 〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇　〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇　〇　Operation　〇　〇　〇　〇　〇　Function]・Comprehensive understanding of memory, scroll offset values, and screen display status, converts the address from the drawing address control unit into a frame memory address, and also calculates the scroll offset value when in the scroll status to control the CRT. Send to the department.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same parts as in Fig. 6 are designated by the same reference numerals.
In the figure, 15 is a newly added frame memory skewer address control unit that comprehensively grasps the frame memory 17, scroll offset value, and screen display state.
It converts the address from the drawing address control section into a frame memory address, and when in the scroll state, calculates a scroll offset value and sends it to the CRT control section 16. Reference numeral 17 denotes a frame memory whose capacity is sufficient for one screen + 12 lines (backer for scrolling).

FIG. 2 also shows the frame memory address control section 15.
In the figure, 21 indicates the specified address and frame.
Address matcher for matching memory address formats, 2
2 is a one-screen judger that detects a break in one screen according to the address from the drawing address control unit 13 and sends a signal to a displacement register; 23 is a displacement register that holds the amount of displacement between the specified address and the frame memory address. An amount register 24 adds a displacement amount to a designated drawing address, and an adder 25 for calculating a frame memory address is a scroll offset transmitter that transmits a scroll offset when scrolling is specified. In addition, in Fig. 2, thin lines indicate control signals,
Bold lines indicate data.

Next, the overall flow of operation will be explained using FIG. 1. First, as in the conventional example, input data is classified by a data input section 11, a display mode control section 12, and a drawing address control section 13.
．． The data is sent to the drawing data control section 14. In the display mode control unit 12, depending on the input data, scrolling is turned ON1.
0FF is determined and held, and a signal is sent to the frame memory address control section 15. The drawing address control section 13 sends the input address as it is to the frame memory address control section 15, which is different from the conventional example. - Also, the drawing data control unit 14 converts the input data into a drawing pattern and outputs it to the frame memory 17 as in the conventional example. The frame memory address control unit 15 converts the address sent from the drawing address control unit 13 into a frame memory address and sends it to the frame memory 17, and when scrolling, the data at the current address is always at the bottom of the screen. Controls the scroll offset so that it is displayed in The CRT control unit 16 causes the CRT 18 to display the given scroll offset value and the υ frame memory read synchronization signal.

Next, the operation of the frame memory address control section 15 shown in FIG. 2 will be explained. First, the data sent from the drawing address control section 13 is sent to the address matching unit 21.
The address format of the frame memory 17 can be matched with the address format of the frame memory 17. For example, if the address of the frame memory 17 is a trap as shown in FIG. 3, the specified address can be subtracted from 192. The displacement register 23 initially contains 0, and the third
Assume that the shaded area in the figure is displayed on the CRT 18.

The first address 192 of the data in FIG.

Here, it is 0 even after addition, so the ID data is frame
Drawing starts from address 0 in the memory 17.

After drawing, a scroll offset is sent from the scroll offset sender 25, and an ID is displayed at the bottom of the screen. (IX4 figure (a)). Data is drawn one after another and 48D
When the data is drawn (FIG. 4(b)), the one-screen determiner 22 determines the end of the screen and gives a designation to the displacement register 23. The displacement register 23 takes out the frame memory address to be drawn next from the register in the adder 24 and holds it as a new displacement. In this example, since drawing is done up to address 191, 192 is held as the new displacement amount. Next, when the next screen top data (address 192) IDA comes, the address matching unit 21 sets the address 192 to 0, and the adder 24 sets the displacement register 2.
Since the value 192 of 3 is added, 1 of the frame memory
Address 92 is selected and after drawing, IDA is placed at the bottom of the CRT.
is displayed (Fig. 4 (C)).If the adder 24 is set to take the remainder of 204, it will be possible to display the data continuously no matter how many pages are scrolled. I can do it.

In addition, if it is not scrolling, the size of the scroll memory is unconditionally stored in the displacement register 23, which is 20 in this example.
If K is set to add 4-192=123, continuous display can be performed even if the scroll screen and fixed screen alternate.

Note that although the above embodiment shows a method suitable for CAPTAIN PLP data, the same effect can be achieved for other data formats as well. Furthermore, if the address matcher 21 is made changeable, the frame memory and CRT control section can easily realize various drawing methods such as one-screen division.

〔Effect of the invention〕

As described above, according to the present invention, the frame memory capacity is composed of one screen + scroll buffer, and is controlled by the frame memory address control section.
Even if the memory capacity is small, it appears to the drawing address control unit that there is an infinite number of continuous frame memories, which has the effect of significantly saving memory capacity without complicating the processing of the drawing address control unit. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a frame memory address control section, and FIG. 3 is a block diagram of a frame memory address control section for explaining the present invention. 4 is an explanatory diagram of the writing order of the frame memory according to the present invention and the reading order by the CRT control section. FIG. 5 is a structural diagram of the frame memory as seen from the drawing address control section according to the present invention. The figure is a configuration diagram of a conventional image display device, and Figure 7 is a CAPTAIN PLP.
FIG. 8 is an image diagram of a frame memory according to the conventional method, and FIG. 9 is an explanatory diagram of the order of writing to the frame memory and reading from the CRT control unit according to the conventional method. In the figure, 11...data input unit, 12...display mode control unit, 13...drawing address control unit, 14...
...Drawing data control unit, 15...Frame memory...
Address control section, 16... CRT control section, 17...
Frame memory, 18... CB, T, 21... Address matcher, 22... 1 screen determiner, 23... Displacement amount register, 24... Adder, 25... Scroll offset It is a transmitter. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4 (a) (b) (c) Figure 6 Figure 7 Figure 1D Figure 8 Figure 9 (a) (b) (C) Figure 9 (d (e)

Claims (1)

[Claims] In an address control method for a frame memory having an image display device that receives image data through an input data section, scrolls and displays the received image data, and displays the image on a CRT, the display mode is selected from the data input section. Output signals are input to the control section, the drawing address control section, and the drawing data control section, and the outputs of the display mode and drawing address control section are received by the frame memory address control section and sent to the CRT control section and the frame memory. At the same time, the output of the drawing data control section is input to the frame memory, the contents of the frame memory are controlled by the CRT control section, and the drawing address on the data writing side is detected as a screen break based on the display state of the screen. 1. A frame memory address control system characterized in that the frame memory address control unit converts the contents of the frame memory into a real address and outputs the contents of the frame memory as an image on a CRT.