JPS61242057A - Manufacturing method of polycrystalline silicon resistor - Google Patents
Manufacturing method of polycrystalline silicon resistorInfo
- Publication number
- JPS61242057A JPS61242057A JP60083648A JP8364885A JPS61242057A JP S61242057 A JPS61242057 A JP S61242057A JP 60083648 A JP60083648 A JP 60083648A JP 8364885 A JP8364885 A JP 8364885A JP S61242057 A JPS61242057 A JP S61242057A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- wiring
- resistor
- manufacturing
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Landscapes
- Non-Adjustable Resistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野ｊ
本発明は、多結晶シリコン層中に電気抵抗体及び配線を
形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming electrical resistors and wiring in a polycrystalline silicon layer.
〔発明の概要」
本発明は、多結晶シリコン層中に電気抵抗体及び配線を
形成する方法において、配線抵抗体化のための不純物拡
散を配線パターン形成後に行うことにより、ＭＯＳ）ラ
ンシスターのような能動素子の歩留を向上できるように
したものである。[Summary of the Invention] The present invention provides a method for forming electrical resistors and wiring in a polycrystalline silicon layer, in which impurity diffusion for forming a wiring resistor is performed after wiring pattern formation. This makes it possible to improve the yield of active devices.
従来、配線低抵抗化のための不純物拡散全配線パターン
形成前に行う方法では、第２図に示すように、多結晶シ
リコン層４（第２図（ａ））に中ドーズイオン注入を行
い、高抵抗多結晶シリコン層５を形成する（第２図（ｂ
））工程と、５ｉＯ１１！ｉ でマスキングして高濃
度不純物を熱拡散で導入し、低抵抗多結晶シリコン層１
２を形成する（第２図（Ｃ））工程と、しかる後に、レ
ジスト１５でマスキングし、ゲート１６、配線１７、抵
抗１８′ｔ−エツチング形成する（第２図（ｄ））及び
第２図（θ）参照）工程とからなる製造方法が知られて
いる。Conventionally, in the method of doping impurity diffusion before forming the entire wiring pattern for lowering wiring resistance, as shown in FIG. A high-resistance polycrystalline silicon layer 5 is formed (Fig. 2(b)
)) process and 5iO11! i, high concentration impurities are introduced by thermal diffusion, and low resistance polycrystalline silicon layer 1 is formed.
2 (FIG. 2(C)), and then masking with resist 15 and forming gate 16, wiring 17, and resistor 18't-etching (FIG. 2(d)); (see (θ)) step is known.
しかし、従来の多結晶シリコン抵抗の製造方法では、多
結晶シリコンのエツチング速度は高不純物濃度多結晶シ
リコンが低不純物濃度多結晶シリコンよりもはるかに大
きいため、抵抗１８のエツチング終了時点で、配線１７
とゲート１６が１−バーエッチのため細り、ゲート酸化
膜３が薄くなる（第２図（ｅ））。そのため、短チヤネ
ル効果や配線抵抗の増大のように素子特性が劣化すると
いう問題があつ九。However, in the conventional manufacturing method of polycrystalline silicon resistors, since the etching speed of polycrystalline silicon with high impurity concentration is much higher than that of polycrystalline silicon with low impurity concentration, when etching of resistor 18 is completed, wiring 17
The gate 16 becomes thinner due to the 1-bar etch, and the gate oxide film 3 becomes thinner (FIG. 2(e)). As a result, there are problems such as deterioration of device characteristics such as short channel effects and increased wiring resistance.
上記のように、配線低抵抗化のための不純物拡散を配線
パターン形成後に行うことにより、素子特性の劣化を防
止し歩留向上に寄与する。As described above, by performing impurity diffusion to lower the resistance of the wiring after forming the wiring pattern, deterioration of device characteristics is prevented and the yield is improved.
以下に本発明の実施例を図面にもとづいて説明する。第
１図（ａ）〜（ｄ）は１本発明の多結晶シリコン抵抗の
製造方法を説明するための工程順の断面図である。第１
図（ａ）は、８１基板１上にフィールド酸化膜１及びゲ
ート酸化膜Ｓｆ形成した後、厚さ５０００〜６０００文
のノンドープｐｏ１７８１層４を化学気相成長法（ＯＶ
Ｄ法）により形成する工程を示す。次に、イオン注入法
により、ドーズ量ｔｘｔｏｌｉべ１Ｘ１０”♂１のリン
イオンを注入した後、９００〜１１００℃の熱処理を行
うことにより、ｎ型の高抵抗ｐｏｌｙｓｉ層５を形成す
る（第１図（’ｂ） ）。Embodiments of the present invention will be described below based on the drawings. FIGS. 1(a) to 1(d) are cross-sectional views in order of steps for explaining a method of manufacturing a polycrystalline silicon resistor according to the present invention. 1st
Figure (a) shows that after forming a field oxide film 1 and a gate oxide film Sf on an 81 substrate 1, a non-doped PO1781 layer 4 with a thickness of 5000 to 6000 mm is deposited using chemical vapor deposition (OV).
The process of forming the film by method D) is shown below. Next, by ion implantation, phosphorus ions are implanted at a dose of 1×10”♂1, and then heat treatment is performed at 900 to 1100° C. to form an n-type high-resistance polysilicon layer 5 (see FIG. 1). 'b)).
次にレジストをマスクして高抵抗ｐｏ１７８１層５をエ
ツチングする。高抵抗ｐｏ１７８１層の面内不純物濃度
均一性は〜５％以内と良好なため、各エツチングパター
ンのエツチングは同時に終了するためレジストマスクに
忠実なパターニングができ、オーバーエッチによるゲー
）ｓｉ□、３の膜ぺりも生じない（第１図（Ｃ））。次
に、抵抗７のみレジストでマキシングした後、イオン注
入法により、ドース量Ｉ Ｘ ＩＱ−１１〜Ｉ Ｘ １
０’″” ｃｍ−” （Ｄ リフ イオ７を注入し、ゲ
ート６、配線８を低抵抗にする。同時に、’ＮＭＯ８の
ソース１０、ドレイン１１が形成できる（第１図（ｄ）
）。Next, the high resistance PO1781 layer 5 is etched using a resist mask. Since the in-plane impurity concentration uniformity of the high-resistance PO1781 layer is within ~5%, etching for each etching pattern is completed at the same time, making it possible to pattern faithfully to the resist mask. No membrane peeling occurred (Fig. 1(C)). Next, after masking only the resistor 7 with a resist, the dose amount I
0'''"cm-" (D) Ion 7 is implanted to make the gate 6 and wiring 8 have low resistance. At the same time, the source 10 and drain 11 of 'NMO8 can be formed (Fig. 1(d)
).
以上のような実施例において示したように、本発明によ
れば、ポリＳ１工ツチング時におけるゲートや配線の細
りがなく、ゲート酸化膜の民べりがないため、短チヤネ
ル効果や配線抵抗の増大の゛ような素子特性の劣化を防
止できる。As shown in the above embodiments, according to the present invention, there is no thinning of the gate or wiring during poly S1 processing, and there is no cracking of the gate oxide film, so there is no short channel effect or increase in wiring resistance. It is possible to prevent the deterioration of device characteristics as described in the following.
〔発明の効果」
この発明は以上説明し念ように、素子特性の劣化を防止
し歩留向上の効果がある。また、配線の低抵抗化のため
の不純物拡散とソース番ドレイン形成のための不純物拡
散音同時にできるため、工程数削減という効果もある。[Effects of the Invention] As explained above, the present invention has the effect of preventing deterioration of device characteristics and improving yield. In addition, impurity diffusion for lowering the resistance of wiring and impurity diffusion sound for forming source and drain can be performed simultaneously, which has the effect of reducing the number of steps.
第１図（ａ）〜第１図（ｄ）は本発明の多結晶シリコン
抵抗の製造方法にかかる工程順の断面図、第２図（ａ）
〜第２図（ｅ）は従来の多結晶シリコン抵抗の製造方法
にかかる工程順の断面図である。
１・・・８１基板、
２・・・フィールド酸化膜、
５・・・ゲート酸化膜、
４・・・ノンドープ多結晶シリコン層、５．１４・・・
高抵抗多結晶シリコン層、６．１６・・・ゲート、
７．１７・・・抵抗、
８．１８・・・配線、
９．１５・・・レジスト、
１０・・・ソース、
１１・・・ドレイン、
１２・−・低抵抗多結晶シリコン層、
１３・・・８１０ｚ０
以 上FIGS. 1(a) to 1(d) are cross-sectional views of the steps in the method of manufacturing a polycrystalline silicon resistor of the present invention, and FIG. 2(a) is
-FIG. 2(e) are cross-sectional views showing the steps of a conventional method for manufacturing a polycrystalline silicon resistor. DESCRIPTION OF SYMBOLS 1... 81 substrate, 2... Field oxide film, 5... Gate oxide film, 4... Non-doped polycrystalline silicon layer, 5.14...
High resistance polycrystalline silicon layer, 6.16...gate, 7.17...resistance, 8.18...wiring, 9.15...resist, 10...source, 11...drain , 12...Low resistance polycrystalline silicon layer, 13...810z0 or more
Claims (1)
オン注入を行なつた後、多結晶シリコン抵抗及び多結晶
シリコン配線のパターンを形成し、前記抵抗パターンを
マスキングして、前記配線パターンを低抵抗化するため
の高ドーズイオン注入を行うことを特徴とする多結晶シ
リコン抵抗の製造方法。After performing medium-dose ion implantation to form a resistor in the polycrystalline silicon layer, a pattern of a polycrystalline silicon resistor and a polycrystalline silicon wiring is formed, the resistor pattern is masked, and the wiring pattern is A method for manufacturing a polycrystalline silicon resistor, characterized by performing high-dose ion implantation to make it resistive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083648A JPS61242057A (en) | 1985-04-19 | 1985-04-19 | Manufacturing method of polycrystalline silicon resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60083648A JPS61242057A (en) | 1985-04-19 | 1985-04-19 | Manufacturing method of polycrystalline silicon resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61242057A true JPS61242057A (en) | 1986-10-28 |
Family
ID=13808267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60083648A Pending JPS61242057A (en) | 1985-04-19 | 1985-04-19 | Manufacturing method of polycrystalline silicon resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61242057A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190911B1 (en) * | 1993-03-17 | 2001-02-20 | Canon Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
-
1985
- 1985-04-19 JP JP60083648A patent/JPS61242057A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190911B1 (en) * | 1993-03-17 | 2001-02-20 | Canon Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
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